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30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
48#include "iwl-3945-core.h"
49#include "iwl-3945.h"
50#include "iwl-helpers.h"
51
52#ifdef CONFIG_IWL3945_DEBUG
53u32 iwl3945_debug_level;
54#endif
55
56static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
57 struct iwl3945_tx_queue *txq);
58
59
60
61
62
63
64
65
66static int iwl3945_param_disable_hw_scan;
67static int iwl3945_param_debug;
68static int iwl3945_param_disable;
69static int iwl3945_param_antenna;
70int iwl3945_param_hwcrypto;
71static int iwl3945_param_qos_enable = 1;
72int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES;
73
74
75
76
77
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
82#ifdef CONFIG_IWL3945_DEBUG
83#define VD "d"
84#else
85#define VD
86#endif
87
88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
89#define VS "s"
90#else
91#define VS
92#endif
93
94#define IWLWIFI_VERSION "1.2.26k" VD VS
95#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
96#define DRV_VERSION IWLWIFI_VERSION
97
98
99MODULE_DESCRIPTION(DRV_DESCRIPTION);
100MODULE_VERSION(DRV_VERSION);
101MODULE_AUTHOR(DRV_COPYRIGHT);
102MODULE_LICENSE("GPL");
103
104static const struct ieee80211_supported_band *iwl3945_get_band(
105 struct iwl3945_priv *priv, enum ieee80211_band band)
106{
107 return priv->hw->wiphy->bands[band];
108}
109
110static int iwl3945_is_empty_essid(const char *essid, int essid_len)
111{
112
113 if (essid_len == 1 && essid[0] == ' ')
114 return 1;
115
116
117 while (essid_len) {
118 essid_len--;
119 if (essid[essid_len] != '\0')
120 return 0;
121 }
122
123 return 1;
124}
125
126static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
127{
128 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
129 const char *s = essid;
130 char *d = escaped;
131
132 if (iwl3945_is_empty_essid(essid, essid_len)) {
133 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
134 return escaped;
135 }
136
137 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
138 while (essid_len--) {
139 if (*s == '\0') {
140 *d++ = '\\';
141 *d++ = '0';
142 s++;
143 } else
144 *d++ = *s++;
145 }
146 *d = '\0';
147 return escaped;
148}
149
150
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153
154
155
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158
159
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161
162
163
164
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173
174
175int iwl3945_queue_space(const struct iwl3945_queue *q)
176{
177 int s = q->read_ptr - q->write_ptr;
178
179 if (q->read_ptr > q->write_ptr)
180 s -= q->n_bd;
181
182 if (s <= 0)
183 s += q->n_window;
184
185 s -= 2;
186 if (s < 0)
187 s = 0;
188 return s;
189}
190
191int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
192{
193 return q->write_ptr > q->read_ptr ?
194 (i >= q->read_ptr && i < q->write_ptr) :
195 !(i < q->read_ptr && i >= q->write_ptr);
196}
197
198
199static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
200{
201
202 if (is_huge)
203 return q->n_window;
204
205
206 return index & (q->n_window - 1);
207}
208
209
210
211
212static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
213 int count, int slots_num, u32 id)
214{
215 q->n_bd = count;
216 q->n_window = slots_num;
217 q->id = id;
218
219
220
221 BUG_ON(!is_power_of_2(count));
222
223
224
225 BUG_ON(!is_power_of_2(slots_num));
226
227 q->low_mark = q->n_window / 4;
228 if (q->low_mark < 4)
229 q->low_mark = 4;
230
231 q->high_mark = q->n_window / 8;
232 if (q->high_mark < 2)
233 q->high_mark = 2;
234
235 q->write_ptr = q->read_ptr = 0;
236
237 return 0;
238}
239
240
241
242
243static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
244 struct iwl3945_tx_queue *txq, u32 id)
245{
246 struct pci_dev *dev = priv->pci_dev;
247
248
249
250 if (id != IWL_CMD_QUEUE_NUM) {
251 txq->txb = kmalloc(sizeof(txq->txb[0]) *
252 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
253 if (!txq->txb) {
254 IWL_ERROR("kmalloc for auxiliary BD "
255 "structures failed\n");
256 goto error;
257 }
258 } else
259 txq->txb = NULL;
260
261
262
263 txq->bd = pci_alloc_consistent(dev,
264 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
265 &txq->q.dma_addr);
266
267 if (!txq->bd) {
268 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
269 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
270 goto error;
271 }
272 txq->q.id = id;
273
274 return 0;
275
276 error:
277 kfree(txq->txb);
278 txq->txb = NULL;
279
280 return -ENOMEM;
281}
282
283
284
285
286int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
287 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
288{
289 struct pci_dev *dev = priv->pci_dev;
290 int len;
291 int rc = 0;
292
293
294
295
296
297
298
299
300
301 len = sizeof(struct iwl3945_cmd) * slots_num;
302 if (txq_id == IWL_CMD_QUEUE_NUM)
303 len += IWL_MAX_SCAN_SIZE;
304 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
305 if (!txq->cmd)
306 return -ENOMEM;
307
308
309 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
310 if (rc) {
311 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
312
313 return -ENOMEM;
314 }
315 txq->need_update = 0;
316
317
318
319 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
320
321
322 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
323
324
325 iwl3945_hw_tx_queue_init(priv, txq);
326
327 return 0;
328}
329
330
331
332
333
334
335
336
337
338void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
339{
340 struct iwl3945_queue *q = &txq->q;
341 struct pci_dev *dev = priv->pci_dev;
342 int len;
343
344 if (q->n_bd == 0)
345 return;
346
347
348 for (; q->write_ptr != q->read_ptr;
349 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
350 iwl3945_hw_txq_free_tfd(priv, txq);
351
352 len = sizeof(struct iwl3945_cmd) * q->n_window;
353 if (q->id == IWL_CMD_QUEUE_NUM)
354 len += IWL_MAX_SCAN_SIZE;
355
356
357 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
358
359
360 if (txq->q.n_bd)
361 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
362 txq->q.n_bd, txq->bd, txq->q.dma_addr);
363
364
365 kfree(txq->txb);
366 txq->txb = NULL;
367
368
369 memset(txq, 0, sizeof(*txq));
370}
371
372const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
373
374
375
376
377
378
379
380#if 0
381
382
383
384
385
386static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
387{
388 int index = IWL_INVALID_STATION;
389 int i;
390 unsigned long flags;
391
392 spin_lock_irqsave(&priv->sta_lock, flags);
393
394 if (is_ap)
395 index = IWL_AP_ID;
396 else if (is_broadcast_ether_addr(addr))
397 index = priv->hw_setting.bcast_sta_id;
398 else
399 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
400 if (priv->stations[i].used &&
401 !compare_ether_addr(priv->stations[i].sta.sta.addr,
402 addr)) {
403 index = i;
404 break;
405 }
406
407 if (unlikely(index == IWL_INVALID_STATION))
408 goto out;
409
410 if (priv->stations[index].used) {
411 priv->stations[index].used = 0;
412 priv->num_stations--;
413 }
414
415 BUG_ON(priv->num_stations < 0);
416
417out:
418 spin_unlock_irqrestore(&priv->sta_lock, flags);
419 return 0;
420}
421#endif
422
423
424
425
426
427
428static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
429{
430 unsigned long flags;
431
432 spin_lock_irqsave(&priv->sta_lock, flags);
433
434 priv->num_stations = 0;
435 memset(priv->stations, 0, sizeof(priv->stations));
436
437 spin_unlock_irqrestore(&priv->sta_lock, flags);
438}
439
440
441
442
443u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
444{
445 int i;
446 int index = IWL_INVALID_STATION;
447 struct iwl3945_station_entry *station;
448 unsigned long flags_spin;
449 DECLARE_MAC_BUF(mac);
450 u8 rate;
451
452 spin_lock_irqsave(&priv->sta_lock, flags_spin);
453 if (is_ap)
454 index = IWL_AP_ID;
455 else if (is_broadcast_ether_addr(addr))
456 index = priv->hw_setting.bcast_sta_id;
457 else
458 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
459 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
460 addr)) {
461 index = i;
462 break;
463 }
464
465 if (!priv->stations[i].used &&
466 index == IWL_INVALID_STATION)
467 index = i;
468 }
469
470
471
472 if (unlikely(index == IWL_INVALID_STATION)) {
473 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
474 return index;
475 }
476
477 if (priv->stations[index].used &&
478 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
479 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
480 return index;
481 }
482
483 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
484 station = &priv->stations[index];
485 station->used = 1;
486 priv->num_stations++;
487
488
489 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
490 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
491 station->sta.mode = 0;
492 station->sta.sta.sta_id = index;
493 station->sta.station_flags = 0;
494
495 if (priv->band == IEEE80211_BAND_5GHZ)
496 rate = IWL_RATE_6M_PLCP;
497 else
498 rate = IWL_RATE_1M_PLCP;
499
500
501 station->sta.rate_n_flags =
502 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
503 station->current_rate.rate_n_flags =
504 le16_to_cpu(station->sta.rate_n_flags);
505
506 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
507
508
509 iwl3945_send_add_station(priv, &station->sta, flags);
510 return index;
511
512}
513
514
515
516static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
517{
518
519
520 return test_bit(STATUS_READY, &priv->status) &&
521 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
522 !test_bit(STATUS_EXIT_PENDING, &priv->status);
523}
524
525static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
526{
527 return test_bit(STATUS_ALIVE, &priv->status);
528}
529
530static inline int iwl3945_is_init(struct iwl3945_priv *priv)
531{
532 return test_bit(STATUS_INIT, &priv->status);
533}
534
535static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
536{
537 return test_bit(STATUS_RF_KILL_SW, &priv->status);
538}
539
540static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
541{
542 return test_bit(STATUS_RF_KILL_HW, &priv->status);
543}
544
545static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
546{
547 return iwl3945_is_rfkill_hw(priv) ||
548 iwl3945_is_rfkill_sw(priv);
549}
550
551static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
552{
553
554 if (iwl3945_is_rfkill(priv))
555 return 0;
556
557 return iwl3945_is_ready(priv);
558}
559
560
561
562#define IWL_CMD(x) case x : return #x
563
564static const char *get_cmd_string(u8 cmd)
565{
566 switch (cmd) {
567 IWL_CMD(REPLY_ALIVE);
568 IWL_CMD(REPLY_ERROR);
569 IWL_CMD(REPLY_RXON);
570 IWL_CMD(REPLY_RXON_ASSOC);
571 IWL_CMD(REPLY_QOS_PARAM);
572 IWL_CMD(REPLY_RXON_TIMING);
573 IWL_CMD(REPLY_ADD_STA);
574 IWL_CMD(REPLY_REMOVE_STA);
575 IWL_CMD(REPLY_REMOVE_ALL_STA);
576 IWL_CMD(REPLY_3945_RX);
577 IWL_CMD(REPLY_TX);
578 IWL_CMD(REPLY_RATE_SCALE);
579 IWL_CMD(REPLY_LEDS_CMD);
580 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
581 IWL_CMD(RADAR_NOTIFICATION);
582 IWL_CMD(REPLY_QUIET_CMD);
583 IWL_CMD(REPLY_CHANNEL_SWITCH);
584 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
585 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
586 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
587 IWL_CMD(POWER_TABLE_CMD);
588 IWL_CMD(PM_SLEEP_NOTIFICATION);
589 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
590 IWL_CMD(REPLY_SCAN_CMD);
591 IWL_CMD(REPLY_SCAN_ABORT_CMD);
592 IWL_CMD(SCAN_START_NOTIFICATION);
593 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
594 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
595 IWL_CMD(BEACON_NOTIFICATION);
596 IWL_CMD(REPLY_TX_BEACON);
597 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
598 IWL_CMD(QUIET_NOTIFICATION);
599 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
600 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
601 IWL_CMD(REPLY_BT_CONFIG);
602 IWL_CMD(REPLY_STATISTICS_CMD);
603 IWL_CMD(STATISTICS_NOTIFICATION);
604 IWL_CMD(REPLY_CARD_STATE_CMD);
605 IWL_CMD(CARD_STATE_NOTIFICATION);
606 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
607 default:
608 return "UNKNOWN";
609
610 }
611}
612
613#define HOST_COMPLETE_TIMEOUT (HZ / 2)
614
615
616
617
618
619
620
621
622
623
624static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
625{
626 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
627 struct iwl3945_queue *q = &txq->q;
628 struct iwl3945_tfd_frame *tfd;
629 u32 *control_flags;
630 struct iwl3945_cmd *out_cmd;
631 u32 idx;
632 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
633 dma_addr_t phys_addr;
634 int pad;
635 u16 count;
636 int ret;
637 unsigned long flags;
638
639
640
641
642 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
643 !(cmd->meta.flags & CMD_SIZE_HUGE));
644
645
646 if (iwl3945_is_rfkill(priv)) {
647 IWL_DEBUG_INFO("Not sending command - RF KILL");
648 return -EIO;
649 }
650
651 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
652 IWL_ERROR("No space for Tx\n");
653 return -ENOSPC;
654 }
655
656 spin_lock_irqsave(&priv->hcmd_lock, flags);
657
658 tfd = &txq->bd[q->write_ptr];
659 memset(tfd, 0, sizeof(*tfd));
660
661 control_flags = (u32 *) tfd;
662
663 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
664 out_cmd = &txq->cmd[idx];
665
666 out_cmd->hdr.cmd = cmd->id;
667 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
668 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
669
670
671
672
673 out_cmd->hdr.flags = 0;
674 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
675 INDEX_TO_SEQ(q->write_ptr));
676 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
677 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
678
679 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
680 offsetof(struct iwl3945_cmd, hdr);
681 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
682
683 pad = U32_PAD(cmd->len);
684 count = TFD_CTL_COUNT_GET(*control_flags);
685 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
686
687 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
688 "%d bytes at %d[%d]:%d\n",
689 get_cmd_string(out_cmd->hdr.cmd),
690 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
691 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
692
693 txq->need_update = 1;
694
695
696 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
697 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
698
699 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
700 return ret ? ret : idx;
701}
702
703static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
704{
705 int ret;
706
707 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
708
709
710 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
711
712
713 BUG_ON(!cmd->meta.u.callback);
714
715 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
716 return -EBUSY;
717
718 ret = iwl3945_enqueue_hcmd(priv, cmd);
719 if (ret < 0) {
720 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
721 get_cmd_string(cmd->id), ret);
722 return ret;
723 }
724 return 0;
725}
726
727static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
728{
729 int cmd_idx;
730 int ret;
731
732 BUG_ON(cmd->meta.flags & CMD_ASYNC);
733
734
735 BUG_ON(cmd->meta.u.callback != NULL);
736
737 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
738 IWL_ERROR("Error sending %s: Already sending a host command\n",
739 get_cmd_string(cmd->id));
740 ret = -EBUSY;
741 goto out;
742 }
743
744 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
745
746 if (cmd->meta.flags & CMD_WANT_SKB)
747 cmd->meta.source = &cmd->meta;
748
749 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
750 if (cmd_idx < 0) {
751 ret = cmd_idx;
752 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
753 get_cmd_string(cmd->id), ret);
754 goto out;
755 }
756
757 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
758 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
759 HOST_COMPLETE_TIMEOUT);
760 if (!ret) {
761 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
762 IWL_ERROR("Error sending %s: time out after %dms.\n",
763 get_cmd_string(cmd->id),
764 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
765
766 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
767 ret = -ETIMEDOUT;
768 goto cancel;
769 }
770 }
771
772 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
773 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
774 get_cmd_string(cmd->id));
775 ret = -ECANCELED;
776 goto fail;
777 }
778 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
779 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
780 get_cmd_string(cmd->id));
781 ret = -EIO;
782 goto fail;
783 }
784 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
785 IWL_ERROR("Error: Response NULL in '%s'\n",
786 get_cmd_string(cmd->id));
787 ret = -EIO;
788 goto out;
789 }
790
791 ret = 0;
792 goto out;
793
794cancel:
795 if (cmd->meta.flags & CMD_WANT_SKB) {
796 struct iwl3945_cmd *qcmd;
797
798
799
800
801
802 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
803 qcmd->meta.flags &= ~CMD_WANT_SKB;
804 }
805fail:
806 if (cmd->meta.u.skb) {
807 dev_kfree_skb_any(cmd->meta.u.skb);
808 cmd->meta.u.skb = NULL;
809 }
810out:
811 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
812 return ret;
813}
814
815int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
816{
817 if (cmd->meta.flags & CMD_ASYNC)
818 return iwl3945_send_cmd_async(priv, cmd);
819
820 return iwl3945_send_cmd_sync(priv, cmd);
821}
822
823int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
824{
825 struct iwl3945_host_cmd cmd = {
826 .id = id,
827 .len = len,
828 .data = data,
829 };
830
831 return iwl3945_send_cmd_sync(priv, &cmd);
832}
833
834static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
835{
836 struct iwl3945_host_cmd cmd = {
837 .id = id,
838 .len = sizeof(val),
839 .data = &val,
840 };
841
842 return iwl3945_send_cmd_sync(priv, &cmd);
843}
844
845int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
846{
847 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
848}
849
850
851
852
853
854
855
856
857
858
859
860static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
861 enum ieee80211_band band,
862 u16 channel)
863{
864 if (!iwl3945_get_channel_info(priv, band, channel)) {
865 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
866 channel, band);
867 return -EINVAL;
868 }
869
870 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
871 (priv->band == band))
872 return 0;
873
874 priv->staging_rxon.channel = cpu_to_le16(channel);
875 if (band == IEEE80211_BAND_5GHZ)
876 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
877 else
878 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
879
880 priv->band = band;
881
882 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
883
884 return 0;
885}
886
887
888
889
890
891
892
893
894static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
895{
896 int error = 0;
897 int counter = 1;
898
899 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
900 error |= le32_to_cpu(rxon->flags &
901 (RXON_FLG_TGJ_NARROW_BAND_MSK |
902 RXON_FLG_RADAR_DETECT_MSK));
903 if (error)
904 IWL_WARNING("check 24G fields %d | %d\n",
905 counter++, error);
906 } else {
907 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
908 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
909 if (error)
910 IWL_WARNING("check 52 fields %d | %d\n",
911 counter++, error);
912 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
913 if (error)
914 IWL_WARNING("check 52 CCK %d | %d\n",
915 counter++, error);
916 }
917 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
918 if (error)
919 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
920
921
922 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
923 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
924 if (error)
925 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
926
927 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
928 if (error)
929 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
930
931 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
932 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
933 if (error)
934 IWL_WARNING("check CCK and short slot %d | %d\n",
935 counter++, error);
936
937 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
938 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
939 if (error)
940 IWL_WARNING("check CCK & auto detect %d | %d\n",
941 counter++, error);
942
943 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
944 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
945 if (error)
946 IWL_WARNING("check TGG and auto detect %d | %d\n",
947 counter++, error);
948
949 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
950 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
951 RXON_FLG_ANT_A_MSK)) == 0);
952 if (error)
953 IWL_WARNING("check antenna %d %d\n", counter++, error);
954
955 if (error)
956 IWL_WARNING("Tuning to channel %d\n",
957 le16_to_cpu(rxon->channel));
958
959 if (error) {
960 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
961 return -1;
962 }
963 return 0;
964}
965
966
967
968
969
970
971
972
973
974static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
975{
976
977
978 if (!(iwl3945_is_associated(priv)) ||
979 compare_ether_addr(priv->staging_rxon.bssid_addr,
980 priv->active_rxon.bssid_addr) ||
981 compare_ether_addr(priv->staging_rxon.node_addr,
982 priv->active_rxon.node_addr) ||
983 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
984 priv->active_rxon.wlap_bssid_addr) ||
985 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
986 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
987 (priv->staging_rxon.air_propagation !=
988 priv->active_rxon.air_propagation) ||
989 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
990 return 1;
991
992
993
994
995
996
997 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
998 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
999 return 1;
1000
1001
1002 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1003 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1004 return 1;
1005
1006 return 0;
1007}
1008
1009static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
1010{
1011 int rc = 0;
1012 struct iwl3945_rx_packet *res = NULL;
1013 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1014 struct iwl3945_host_cmd cmd = {
1015 .id = REPLY_RXON_ASSOC,
1016 .len = sizeof(rxon_assoc),
1017 .meta.flags = CMD_WANT_SKB,
1018 .data = &rxon_assoc,
1019 };
1020 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1021 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
1022
1023 if ((rxon1->flags == rxon2->flags) &&
1024 (rxon1->filter_flags == rxon2->filter_flags) &&
1025 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1026 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1027 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1028 return 0;
1029 }
1030
1031 rxon_assoc.flags = priv->staging_rxon.flags;
1032 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1033 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1034 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1035 rxon_assoc.reserved = 0;
1036
1037 rc = iwl3945_send_cmd_sync(priv, &cmd);
1038 if (rc)
1039 return rc;
1040
1041 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
1042 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1043 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1044 rc = -EIO;
1045 }
1046
1047 priv->alloc_rxb_skb--;
1048 dev_kfree_skb_any(cmd.meta.u.skb);
1049
1050 return rc;
1051}
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
1062{
1063
1064 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1065 int rc = 0;
1066 DECLARE_MAC_BUF(mac);
1067
1068 if (!iwl3945_is_alive(priv))
1069 return -1;
1070
1071
1072 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1073
1074
1075 priv->staging_rxon.flags &=
1076 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1077 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1078
1079 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
1080 if (rc) {
1081 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1082 return -EINVAL;
1083 }
1084
1085
1086
1087
1088 if (!iwl3945_full_rxon_required(priv)) {
1089 rc = iwl3945_send_rxon_assoc(priv);
1090 if (rc) {
1091 IWL_ERROR("Error setting RXON_ASSOC "
1092 "configuration (%d).\n", rc);
1093 return rc;
1094 }
1095
1096 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1097
1098 return 0;
1099 }
1100
1101
1102
1103
1104
1105 if (iwl3945_is_associated(priv) &&
1106 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1107 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1108 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1109
1110 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1111 sizeof(struct iwl3945_rxon_cmd),
1112 &priv->active_rxon);
1113
1114
1115
1116 if (rc) {
1117 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1118 IWL_ERROR("Error clearing ASSOC_MSK on current "
1119 "configuration (%d).\n", rc);
1120 return rc;
1121 }
1122 }
1123
1124 IWL_DEBUG_INFO("Sending RXON\n"
1125 "* with%s RXON_FILTER_ASSOC_MSK\n"
1126 "* channel = %d\n"
1127 "* bssid = %s\n",
1128 ((priv->staging_rxon.filter_flags &
1129 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1130 le16_to_cpu(priv->staging_rxon.channel),
1131 print_mac(mac, priv->staging_rxon.bssid_addr));
1132
1133
1134 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1135 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
1136 if (rc) {
1137 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1138 return rc;
1139 }
1140
1141 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1142
1143 iwl3945_clear_stations_table(priv);
1144
1145
1146
1147 rc = iwl3945_hw_reg_send_txpower(priv);
1148 if (rc) {
1149 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1150 return rc;
1151 }
1152
1153
1154 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
1155 IWL_INVALID_STATION) {
1156 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1157 return -EIO;
1158 }
1159
1160
1161
1162 if (iwl3945_is_associated(priv) &&
1163 (priv->iw_mode == NL80211_IFTYPE_STATION))
1164 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
1165 == IWL_INVALID_STATION) {
1166 IWL_ERROR("Error adding AP address for transmit.\n");
1167 return -EIO;
1168 }
1169
1170
1171 rc = iwl3945_init_hw_rate_table(priv);
1172 if (rc) {
1173 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1174 return -EIO;
1175 }
1176
1177 return 0;
1178}
1179
1180static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
1181{
1182 struct iwl3945_bt_cmd bt_cmd = {
1183 .flags = 3,
1184 .lead_time = 0xAA,
1185 .max_kill = 1,
1186 .kill_ack_mask = 0,
1187 .kill_cts_mask = 0,
1188 };
1189
1190 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1191 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
1192}
1193
1194static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
1195{
1196 int rc = 0;
1197 struct iwl3945_rx_packet *res;
1198 struct iwl3945_host_cmd cmd = {
1199 .id = REPLY_SCAN_ABORT_CMD,
1200 .meta.flags = CMD_WANT_SKB,
1201 };
1202
1203
1204
1205
1206 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1207 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1208 return 0;
1209 }
1210
1211 rc = iwl3945_send_cmd_sync(priv, &cmd);
1212 if (rc) {
1213 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1214 return rc;
1215 }
1216
1217 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
1218 if (res->u.status != CAN_ABORT_STATUS) {
1219
1220
1221
1222
1223
1224
1225 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1226 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1227 clear_bit(STATUS_SCAN_HW, &priv->status);
1228 }
1229
1230 dev_kfree_skb_any(cmd.meta.u.skb);
1231
1232 return rc;
1233}
1234
1235static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1236 struct iwl3945_cmd *cmd,
1237 struct sk_buff *skb)
1238{
1239 return 1;
1240}
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
1253{
1254 struct iwl3945_host_cmd cmd = {
1255 .id = REPLY_CARD_STATE_CMD,
1256 .len = sizeof(u32),
1257 .data = &flags,
1258 .meta.flags = meta_flag,
1259 };
1260
1261 if (meta_flag & CMD_ASYNC)
1262 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
1263
1264 return iwl3945_send_cmd(priv, &cmd);
1265}
1266
1267static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1268 struct iwl3945_cmd *cmd, struct sk_buff *skb)
1269{
1270 struct iwl3945_rx_packet *res = NULL;
1271
1272 if (!skb) {
1273 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1274 return 1;
1275 }
1276
1277 res = (struct iwl3945_rx_packet *)skb->data;
1278 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1279 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1280 res->hdr.flags);
1281 return 1;
1282 }
1283
1284 switch (res->u.add_sta.status) {
1285 case ADD_STA_SUCCESS_MSK:
1286 break;
1287 default:
1288 break;
1289 }
1290
1291
1292 return 1;
1293}
1294
1295int iwl3945_send_add_station(struct iwl3945_priv *priv,
1296 struct iwl3945_addsta_cmd *sta, u8 flags)
1297{
1298 struct iwl3945_rx_packet *res = NULL;
1299 int rc = 0;
1300 struct iwl3945_host_cmd cmd = {
1301 .id = REPLY_ADD_STA,
1302 .len = sizeof(struct iwl3945_addsta_cmd),
1303 .meta.flags = flags,
1304 .data = sta,
1305 };
1306
1307 if (flags & CMD_ASYNC)
1308 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
1309 else
1310 cmd.meta.flags |= CMD_WANT_SKB;
1311
1312 rc = iwl3945_send_cmd(priv, &cmd);
1313
1314 if (rc || (flags & CMD_ASYNC))
1315 return rc;
1316
1317 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
1318 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1319 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1320 res->hdr.flags);
1321 rc = -EIO;
1322 }
1323
1324 if (rc == 0) {
1325 switch (res->u.add_sta.status) {
1326 case ADD_STA_SUCCESS_MSK:
1327 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1328 break;
1329 default:
1330 rc = -EIO;
1331 IWL_WARNING("REPLY_ADD_STA failed\n");
1332 break;
1333 }
1334 }
1335
1336 priv->alloc_rxb_skb--;
1337 dev_kfree_skb_any(cmd.meta.u.skb);
1338
1339 return rc;
1340}
1341
1342static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
1343 struct ieee80211_key_conf *keyconf,
1344 u8 sta_id)
1345{
1346 unsigned long flags;
1347 __le16 key_flags = 0;
1348
1349 switch (keyconf->alg) {
1350 case ALG_CCMP:
1351 key_flags |= STA_KEY_FLG_CCMP;
1352 key_flags |= cpu_to_le16(
1353 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1354 key_flags &= ~STA_KEY_FLG_INVALID;
1355 break;
1356 case ALG_TKIP:
1357 case ALG_WEP:
1358 default:
1359 return -EINVAL;
1360 }
1361 spin_lock_irqsave(&priv->sta_lock, flags);
1362 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1363 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1364 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1365 keyconf->keylen);
1366
1367 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1368 keyconf->keylen);
1369 priv->stations[sta_id].sta.key.key_flags = key_flags;
1370 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1371 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1372
1373 spin_unlock_irqrestore(&priv->sta_lock, flags);
1374
1375 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
1376 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
1377 return 0;
1378}
1379
1380static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
1381{
1382 unsigned long flags;
1383
1384 spin_lock_irqsave(&priv->sta_lock, flags);
1385 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1386 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
1387 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1388 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1389 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1390 spin_unlock_irqrestore(&priv->sta_lock, flags);
1391
1392 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
1393 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
1394 return 0;
1395}
1396
1397static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
1398{
1399 struct list_head *element;
1400
1401 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1402 priv->frames_count);
1403
1404 while (!list_empty(&priv->free_frames)) {
1405 element = priv->free_frames.next;
1406 list_del(element);
1407 kfree(list_entry(element, struct iwl3945_frame, list));
1408 priv->frames_count--;
1409 }
1410
1411 if (priv->frames_count) {
1412 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1413 priv->frames_count);
1414 priv->frames_count = 0;
1415 }
1416}
1417
1418static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
1419{
1420 struct iwl3945_frame *frame;
1421 struct list_head *element;
1422 if (list_empty(&priv->free_frames)) {
1423 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1424 if (!frame) {
1425 IWL_ERROR("Could not allocate frame!\n");
1426 return NULL;
1427 }
1428
1429 priv->frames_count++;
1430 return frame;
1431 }
1432
1433 element = priv->free_frames.next;
1434 list_del(element);
1435 return list_entry(element, struct iwl3945_frame, list);
1436}
1437
1438static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
1439{
1440 memset(frame, 0, sizeof(*frame));
1441 list_add(&frame->list, &priv->free_frames);
1442}
1443
1444unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
1445 struct ieee80211_hdr *hdr,
1446 const u8 *dest, int left)
1447{
1448
1449 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
1450 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1451 (priv->iw_mode != NL80211_IFTYPE_AP)))
1452 return 0;
1453
1454 if (priv->ibss_beacon->len > left)
1455 return 0;
1456
1457 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1458
1459 return priv->ibss_beacon->len;
1460}
1461
1462static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
1463{
1464 u8 i;
1465
1466 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
1467 i = iwl3945_rates[i].next_ieee) {
1468 if (rate_mask & (1 << i))
1469 return iwl3945_rates[i].plcp;
1470 }
1471
1472 return IWL_RATE_INVALID;
1473}
1474
1475static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
1476{
1477 struct iwl3945_frame *frame;
1478 unsigned int frame_size;
1479 int rc;
1480 u8 rate;
1481
1482 frame = iwl3945_get_free_frame(priv);
1483
1484 if (!frame) {
1485 IWL_ERROR("Could not obtain free frame buffer for beacon "
1486 "command.\n");
1487 return -ENOMEM;
1488 }
1489
1490 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
1491 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
1492 0xFF0);
1493 if (rate == IWL_INVALID_RATE)
1494 rate = IWL_RATE_6M_PLCP;
1495 } else {
1496 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
1497 if (rate == IWL_INVALID_RATE)
1498 rate = IWL_RATE_1M_PLCP;
1499 }
1500
1501 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
1502
1503 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
1504 &frame->u.cmd[0]);
1505
1506 iwl3945_free_frame(priv, frame);
1507
1508 return rc;
1509}
1510
1511
1512
1513
1514
1515
1516
1517static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
1518{
1519 memcpy(mac, priv->eeprom.mac_address, 6);
1520}
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1531{
1532 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1533 return 0;
1534}
1535
1536
1537
1538
1539
1540
1541
1542
1543int iwl3945_eeprom_init(struct iwl3945_priv *priv)
1544{
1545 u16 *e = (u16 *)&priv->eeprom;
1546 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
1547 u32 r;
1548 int sz = sizeof(priv->eeprom);
1549 int rc;
1550 int i;
1551 u16 addr;
1552
1553
1554
1555
1556
1557 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1558
1559 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1560 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
1561 return -ENOENT;
1562 }
1563
1564
1565 rc = iwl3945_eeprom_acquire_semaphore(priv);
1566 if (rc < 0) {
1567 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
1568 return -ENOENT;
1569 }
1570
1571
1572 for (addr = 0; addr < sz; addr += sizeof(u16)) {
1573 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1574 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1575
1576 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1577 i += IWL_EEPROM_ACCESS_DELAY) {
1578 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
1579 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1580 break;
1581 udelay(IWL_EEPROM_ACCESS_DELAY);
1582 }
1583
1584 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1585 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
1586 return -ETIMEDOUT;
1587 }
1588 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
1589 }
1590
1591 return 0;
1592}
1593
1594static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
1595{
1596 if (priv->hw_setting.shared_virt)
1597 pci_free_consistent(priv->pci_dev,
1598 sizeof(struct iwl3945_shared),
1599 priv->hw_setting.shared_virt,
1600 priv->hw_setting.shared_phys);
1601}
1602
1603
1604
1605
1606
1607
1608static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
1609 u16 basic_rate, int *left)
1610{
1611 u16 ret_rates = 0, bit;
1612 int i;
1613 u8 *cnt = ie;
1614 u8 *rates = ie + 1;
1615
1616 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1617 if (bit & supported_rate) {
1618 ret_rates |= bit;
1619 rates[*cnt] = iwl3945_rates[i].ieee |
1620 ((bit & basic_rate) ? 0x80 : 0x00);
1621 (*cnt)++;
1622 (*left)--;
1623 if ((*left <= 0) ||
1624 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
1625 break;
1626 }
1627 }
1628
1629 return ret_rates;
1630}
1631
1632
1633
1634
1635static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
1636 struct ieee80211_mgmt *frame,
1637 int left, int is_direct)
1638{
1639 int len = 0;
1640 u8 *pos = NULL;
1641 u16 active_rates, ret_rates, cck_rates;
1642
1643
1644
1645 left -= 24;
1646 if (left < 0)
1647 return 0;
1648 len += 24;
1649
1650 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1651 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
1652 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
1653 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
1654 frame->seq_ctrl = 0;
1655
1656
1657
1658
1659 left -= 2;
1660 if (left < 0)
1661 return 0;
1662 len += 2;
1663 pos = &(frame->u.probe_req.variable[0]);
1664 *pos++ = WLAN_EID_SSID;
1665 *pos++ = 0;
1666
1667
1668 if (is_direct) {
1669
1670 left -= 2 + priv->essid_len;
1671 if (left < 0)
1672 return 0;
1673
1674 *pos++ = WLAN_EID_SSID;
1675 *pos++ = priv->essid_len;
1676 memcpy(pos, priv->essid, priv->essid_len);
1677 pos += priv->essid_len;
1678 len += 2 + priv->essid_len;
1679 }
1680
1681
1682
1683 left -= 2;
1684 if (left < 0)
1685 return 0;
1686
1687
1688 *pos++ = WLAN_EID_SUPP_RATES;
1689 *pos = 0;
1690
1691 priv->active_rate = priv->rates_mask;
1692 active_rates = priv->active_rate;
1693 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1694
1695 cck_rates = IWL_CCK_RATES_MASK & active_rates;
1696 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
1697 priv->active_rate_basic, &left);
1698 active_rates &= ~ret_rates;
1699
1700 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
1701 priv->active_rate_basic, &left);
1702 active_rates &= ~ret_rates;
1703
1704 len += 2 + *pos;
1705 pos += (*pos) + 1;
1706 if (active_rates == 0)
1707 goto fill_end;
1708
1709
1710
1711 left -= 2;
1712 if (left < 0)
1713 return 0;
1714
1715 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1716 *pos = 0;
1717 iwl3945_supported_rate_to_ie(pos, active_rates,
1718 priv->active_rate_basic, &left);
1719 if (*pos > 0)
1720 len += 2 + *pos;
1721
1722 fill_end:
1723 return (u16)len;
1724}
1725
1726
1727
1728
1729static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1730 struct iwl3945_qosparam_cmd *qos)
1731{
1732
1733 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1734 sizeof(struct iwl3945_qosparam_cmd), qos);
1735}
1736
1737static void iwl3945_reset_qos(struct iwl3945_priv *priv)
1738{
1739 u16 cw_min = 15;
1740 u16 cw_max = 1023;
1741 u8 aifs = 2;
1742 u8 is_legacy = 0;
1743 unsigned long flags;
1744 int i;
1745
1746 spin_lock_irqsave(&priv->lock, flags);
1747 priv->qos_data.qos_active = 0;
1748
1749 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1750 if (priv->qos_data.qos_enable)
1751 priv->qos_data.qos_active = 1;
1752 if (!(priv->active_rate & 0xfff0)) {
1753 cw_min = 31;
1754 is_legacy = 1;
1755 }
1756 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
1757 if (priv->qos_data.qos_enable)
1758 priv->qos_data.qos_active = 1;
1759 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1760 cw_min = 31;
1761 is_legacy = 1;
1762 }
1763
1764 if (priv->qos_data.qos_active)
1765 aifs = 3;
1766
1767 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1768 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1769 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1770 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1771 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1772
1773 if (priv->qos_data.qos_active) {
1774 i = 1;
1775 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1776 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1777 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1778 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1779 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1780
1781 i = 2;
1782 priv->qos_data.def_qos_parm.ac[i].cw_min =
1783 cpu_to_le16((cw_min + 1) / 2 - 1);
1784 priv->qos_data.def_qos_parm.ac[i].cw_max =
1785 cpu_to_le16(cw_max);
1786 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1787 if (is_legacy)
1788 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1789 cpu_to_le16(6016);
1790 else
1791 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1792 cpu_to_le16(3008);
1793 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1794
1795 i = 3;
1796 priv->qos_data.def_qos_parm.ac[i].cw_min =
1797 cpu_to_le16((cw_min + 1) / 4 - 1);
1798 priv->qos_data.def_qos_parm.ac[i].cw_max =
1799 cpu_to_le16((cw_max + 1) / 2 - 1);
1800 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1801 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1802 if (is_legacy)
1803 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1804 cpu_to_le16(3264);
1805 else
1806 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1807 cpu_to_le16(1504);
1808 } else {
1809 for (i = 1; i < 4; i++) {
1810 priv->qos_data.def_qos_parm.ac[i].cw_min =
1811 cpu_to_le16(cw_min);
1812 priv->qos_data.def_qos_parm.ac[i].cw_max =
1813 cpu_to_le16(cw_max);
1814 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1815 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1816 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1817 }
1818 }
1819 IWL_DEBUG_QOS("set QoS to default \n");
1820
1821 spin_unlock_irqrestore(&priv->lock, flags);
1822}
1823
1824static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
1825{
1826 unsigned long flags;
1827
1828 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1829 return;
1830
1831 if (!priv->qos_data.qos_enable)
1832 return;
1833
1834 spin_lock_irqsave(&priv->lock, flags);
1835 priv->qos_data.def_qos_parm.qos_flags = 0;
1836
1837 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1838 !priv->qos_data.qos_cap.q_AP.txop_request)
1839 priv->qos_data.def_qos_parm.qos_flags |=
1840 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1841
1842 if (priv->qos_data.qos_active)
1843 priv->qos_data.def_qos_parm.qos_flags |=
1844 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1845
1846 spin_unlock_irqrestore(&priv->lock, flags);
1847
1848 if (force || iwl3945_is_associated(priv)) {
1849 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1850 priv->qos_data.qos_active);
1851
1852 iwl3945_send_qos_params_command(priv,
1853 &(priv->qos_data.def_qos_parm));
1854 }
1855}
1856
1857
1858
1859
1860#define MSEC_TO_USEC 1024
1861
1862#define NOSLP __constant_cpu_to_le32(0)
1863#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1864#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1865#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1866 __constant_cpu_to_le32(X1), \
1867 __constant_cpu_to_le32(X2), \
1868 __constant_cpu_to_le32(X3), \
1869 __constant_cpu_to_le32(X4)}
1870
1871
1872
1873
1874static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
1875 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1876 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1877 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1878 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1879 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1880 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1881};
1882
1883
1884static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
1885 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1886 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1887 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1888 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1889 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1890 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1891 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1892 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1893 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1894 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1895};
1896
1897int iwl3945_power_init_handle(struct iwl3945_priv *priv)
1898{
1899 int rc = 0, i;
1900 struct iwl3945_power_mgr *pow_data;
1901 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
1902 u16 pci_pm;
1903
1904 IWL_DEBUG_POWER("Initialize power \n");
1905
1906 pow_data = &(priv->power_data);
1907
1908 memset(pow_data, 0, sizeof(*pow_data));
1909
1910 pow_data->active_index = IWL_POWER_RANGE_0;
1911 pow_data->dtim_val = 0xffff;
1912
1913 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1914 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1915
1916 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1917 if (rc != 0)
1918 return 0;
1919 else {
1920 struct iwl3945_powertable_cmd *cmd;
1921
1922 IWL_DEBUG_POWER("adjust power command flags\n");
1923
1924 for (i = 0; i < IWL_POWER_AC; i++) {
1925 cmd = &pow_data->pwr_range_0[i].cmd;
1926
1927 if (pci_pm & 0x1)
1928 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1929 else
1930 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1931 }
1932 }
1933 return rc;
1934}
1935
1936static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1937 struct iwl3945_powertable_cmd *cmd, u32 mode)
1938{
1939 int rc = 0, i;
1940 u8 skip;
1941 u32 max_sleep = 0;
1942 struct iwl3945_power_vec_entry *range;
1943 u8 period = 0;
1944 struct iwl3945_power_mgr *pow_data;
1945
1946 if (mode > IWL_POWER_INDEX_5) {
1947 IWL_DEBUG_POWER("Error invalid power mode \n");
1948 return -1;
1949 }
1950 pow_data = &(priv->power_data);
1951
1952 if (pow_data->active_index == IWL_POWER_RANGE_0)
1953 range = &pow_data->pwr_range_0[0];
1954 else
1955 range = &pow_data->pwr_range_1[1];
1956
1957 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
1958
1959#ifdef IWL_MAC80211_DISABLE
1960 if (priv->assoc_network != NULL) {
1961 unsigned long flags;
1962
1963 period = priv->assoc_network->tim.tim_period;
1964 }
1965#endif
1966 skip = range[mode].no_dtim;
1967
1968 if (period == 0) {
1969 period = 1;
1970 skip = 0;
1971 }
1972
1973 if (skip == 0) {
1974 max_sleep = period;
1975 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1976 } else {
1977 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1978 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1979 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1980 }
1981
1982 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1983 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1984 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1985 }
1986
1987 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1988 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1989 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1990 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1991 le32_to_cpu(cmd->sleep_interval[0]),
1992 le32_to_cpu(cmd->sleep_interval[1]),
1993 le32_to_cpu(cmd->sleep_interval[2]),
1994 le32_to_cpu(cmd->sleep_interval[3]),
1995 le32_to_cpu(cmd->sleep_interval[4]));
1996
1997 return rc;
1998}
1999
2000static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
2001{
2002 u32 uninitialized_var(final_mode);
2003 int rc;
2004 struct iwl3945_powertable_cmd cmd;
2005
2006
2007
2008
2009 switch (mode) {
2010 case IWL_POWER_BATTERY:
2011 final_mode = IWL_POWER_INDEX_3;
2012 break;
2013 case IWL_POWER_AC:
2014 final_mode = IWL_POWER_MODE_CAM;
2015 break;
2016 default:
2017 final_mode = mode;
2018 break;
2019 }
2020
2021 iwl3945_update_power_cmd(priv, &cmd, final_mode);
2022
2023 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
2024
2025 if (final_mode == IWL_POWER_MODE_CAM)
2026 clear_bit(STATUS_POWER_PMI, &priv->status);
2027 else
2028 set_bit(STATUS_POWER_PMI, &priv->status);
2029
2030 return rc;
2031}
2032
2033
2034
2035
2036
2037
2038static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
2039{
2040 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2041 clear_bit(STATUS_SCANNING, &priv->status);
2042 return 0;
2043 }
2044
2045 if (test_bit(STATUS_SCANNING, &priv->status)) {
2046 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2047 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2048 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2049 queue_work(priv->workqueue, &priv->abort_scan);
2050
2051 } else
2052 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2053
2054 return test_bit(STATUS_SCANNING, &priv->status);
2055 }
2056
2057 return 0;
2058}
2059
2060
2061
2062
2063
2064
2065
2066static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
2067{
2068 unsigned long now = jiffies;
2069 int ret;
2070
2071 ret = iwl3945_scan_cancel(priv);
2072 if (ret && ms) {
2073 mutex_unlock(&priv->mutex);
2074 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2075 test_bit(STATUS_SCANNING, &priv->status))
2076 msleep(1);
2077 mutex_lock(&priv->mutex);
2078
2079 return test_bit(STATUS_SCANNING, &priv->status);
2080 }
2081
2082 return ret;
2083}
2084
2085#define MAX_UCODE_BEACON_INTERVAL 1024
2086#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2087
2088static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
2089{
2090 u16 new_val = 0;
2091 u16 beacon_factor = 0;
2092
2093 beacon_factor =
2094 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2095 / MAX_UCODE_BEACON_INTERVAL;
2096 new_val = beacon_val / beacon_factor;
2097
2098 return cpu_to_le16(new_val);
2099}
2100
2101static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
2102{
2103 u64 interval_tm_unit;
2104 u64 tsf, result;
2105 unsigned long flags;
2106 struct ieee80211_conf *conf = NULL;
2107 u16 beacon_int = 0;
2108
2109 conf = ieee80211_get_hw_conf(priv->hw);
2110
2111 spin_lock_irqsave(&priv->lock, flags);
2112 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2113 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2114
2115 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2116
2117 tsf = priv->timestamp1;
2118 tsf = ((tsf << 32) | priv->timestamp0);
2119
2120 beacon_int = priv->beacon_int;
2121 spin_unlock_irqrestore(&priv->lock, flags);
2122
2123 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
2124 if (beacon_int == 0) {
2125 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2126 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2127 } else {
2128 priv->rxon_timing.beacon_interval =
2129 cpu_to_le16(beacon_int);
2130 priv->rxon_timing.beacon_interval =
2131 iwl3945_adjust_beacon_interval(
2132 le16_to_cpu(priv->rxon_timing.beacon_interval));
2133 }
2134
2135 priv->rxon_timing.atim_window = 0;
2136 } else {
2137 priv->rxon_timing.beacon_interval =
2138 iwl3945_adjust_beacon_interval(conf->beacon_int);
2139
2140
2141 priv->rxon_timing.atim_window = 0;
2142 }
2143
2144 interval_tm_unit =
2145 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2146 result = do_div(tsf, interval_tm_unit);
2147 priv->rxon_timing.beacon_init_val =
2148 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2149
2150 IWL_DEBUG_ASSOC
2151 ("beacon interval %d beacon timer %d beacon tim %d\n",
2152 le16_to_cpu(priv->rxon_timing.beacon_interval),
2153 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2154 le16_to_cpu(priv->rxon_timing.atim_window));
2155}
2156
2157static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
2158{
2159 if (priv->iw_mode == NL80211_IFTYPE_AP) {
2160 IWL_ERROR("APs don't scan.\n");
2161 return 0;
2162 }
2163
2164 if (!iwl3945_is_ready_rf(priv)) {
2165 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2166 return -EIO;
2167 }
2168
2169 if (test_bit(STATUS_SCANNING, &priv->status)) {
2170 IWL_DEBUG_SCAN("Scan already in progress.\n");
2171 return -EAGAIN;
2172 }
2173
2174 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2175 IWL_DEBUG_SCAN("Scan request while abort pending. "
2176 "Queuing.\n");
2177 return -EAGAIN;
2178 }
2179
2180 IWL_DEBUG_INFO("Starting scan...\n");
2181 if (priv->cfg->sku & IWL_SKU_G)
2182 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2183 if (priv->cfg->sku & IWL_SKU_A)
2184 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
2185 set_bit(STATUS_SCANNING, &priv->status);
2186 priv->scan_start = jiffies;
2187 priv->scan_pass_start = priv->scan_start;
2188
2189 queue_work(priv->workqueue, &priv->request_scan);
2190
2191 return 0;
2192}
2193
2194static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
2195{
2196 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
2197
2198 if (hw_decrypt)
2199 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2200 else
2201 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2202
2203 return 0;
2204}
2205
2206static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2207 enum ieee80211_band band)
2208{
2209 if (band == IEEE80211_BAND_5GHZ) {
2210 priv->staging_rxon.flags &=
2211 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2212 | RXON_FLG_CCK_MSK);
2213 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2214 } else {
2215
2216 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2217 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2218 else
2219 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2220
2221 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2222 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2223
2224 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2225 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2226 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2227 }
2228}
2229
2230
2231
2232
2233static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
2234{
2235 const struct iwl3945_channel_info *ch_info;
2236
2237 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2238
2239 switch (priv->iw_mode) {
2240 case NL80211_IFTYPE_AP:
2241 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2242 break;
2243
2244 case NL80211_IFTYPE_STATION:
2245 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2246 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2247 break;
2248
2249 case NL80211_IFTYPE_ADHOC:
2250 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2251 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2252 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2253 RXON_FILTER_ACCEPT_GRP_MSK;
2254 break;
2255
2256 case NL80211_IFTYPE_MONITOR:
2257 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2258 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2259 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2260 break;
2261 default:
2262 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2263 break;
2264 }
2265
2266#if 0
2267
2268
2269 if (!hw_to_local(priv->hw)->short_preamble)
2270 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2271 else
2272 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2273#endif
2274
2275 ch_info = iwl3945_get_channel_info(priv, priv->band,
2276 le16_to_cpu(priv->active_rxon.channel));
2277
2278 if (!ch_info)
2279 ch_info = &priv->channel_info[0];
2280
2281
2282
2283
2284
2285 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
2286 !(is_channel_ibss(ch_info)))
2287 ch_info = &priv->channel_info[0];
2288
2289 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2290 if (is_channel_a_band(ch_info))
2291 priv->band = IEEE80211_BAND_5GHZ;
2292 else
2293 priv->band = IEEE80211_BAND_2GHZ;
2294
2295 iwl3945_set_flags_for_phymode(priv, priv->band);
2296
2297 priv->staging_rxon.ofdm_basic_rates =
2298 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2299 priv->staging_rxon.cck_basic_rates =
2300 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2301}
2302
2303static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
2304{
2305 if (mode == NL80211_IFTYPE_ADHOC) {
2306 const struct iwl3945_channel_info *ch_info;
2307
2308 ch_info = iwl3945_get_channel_info(priv,
2309 priv->band,
2310 le16_to_cpu(priv->staging_rxon.channel));
2311
2312 if (!ch_info || !is_channel_ibss(ch_info)) {
2313 IWL_ERROR("channel %d not IBSS channel\n",
2314 le16_to_cpu(priv->staging_rxon.channel));
2315 return -EINVAL;
2316 }
2317 }
2318
2319 priv->iw_mode = mode;
2320
2321 iwl3945_connection_init_rx_config(priv);
2322 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2323
2324 iwl3945_clear_stations_table(priv);
2325
2326
2327 if (!iwl3945_is_ready_rf(priv))
2328 return -EAGAIN;
2329
2330 cancel_delayed_work(&priv->scan_check);
2331 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2332 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2333 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2334 return -EAGAIN;
2335 }
2336
2337 iwl3945_commit_rxon(priv);
2338
2339 return 0;
2340}
2341
2342static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
2343 struct ieee80211_tx_info *info,
2344 struct iwl3945_cmd *cmd,
2345 struct sk_buff *skb_frag,
2346 int last_frag)
2347{
2348 struct iwl3945_hw_key *keyinfo =
2349 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
2350
2351 switch (keyinfo->alg) {
2352 case ALG_CCMP:
2353 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2354 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2355 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2356 break;
2357
2358 case ALG_TKIP:
2359#if 0
2360 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2361
2362 if (last_frag)
2363 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2364 8);
2365 else
2366 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2367#endif
2368 break;
2369
2370 case ALG_WEP:
2371 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2372 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2373
2374 if (keyinfo->keylen == 13)
2375 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2376
2377 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2378
2379 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2380 "with key %d\n", info->control.hw_key->hw_key_idx);
2381 break;
2382
2383 default:
2384 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2385 break;
2386 }
2387}
2388
2389
2390
2391
2392static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2393 struct iwl3945_cmd *cmd,
2394 struct ieee80211_tx_info *info,
2395 struct ieee80211_hdr *hdr,
2396 int is_unicast, u8 std_id)
2397{
2398 __le16 fc = hdr->frame_control;
2399 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2400
2401 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2402 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
2403 tx_flags |= TX_CMD_FLG_ACK_MSK;
2404 if (ieee80211_is_mgmt(fc))
2405 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2406 if (ieee80211_is_probe_resp(fc) &&
2407 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2408 tx_flags |= TX_CMD_FLG_TSF_MSK;
2409 } else {
2410 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2411 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2412 }
2413
2414 cmd->cmd.tx.sta_id = std_id;
2415 if (ieee80211_has_morefrags(fc))
2416 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2417
2418 if (ieee80211_is_data_qos(fc)) {
2419 u8 *qc = ieee80211_get_qos_ctl(hdr);
2420 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
2421 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2422 } else {
2423 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2424 }
2425
2426 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
2427 tx_flags |= TX_CMD_FLG_RTS_MSK;
2428 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2429 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
2430 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2431 tx_flags |= TX_CMD_FLG_CTS_MSK;
2432 }
2433
2434 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2435 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2436
2437 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2438 if (ieee80211_is_mgmt(fc)) {
2439 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
2440 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
2441 else
2442 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
2443 } else {
2444 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2445#ifdef CONFIG_IWL3945_LEDS
2446 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2447#endif
2448 }
2449
2450 cmd->cmd.tx.driver_txop = 0;
2451 cmd->cmd.tx.tx_flags = tx_flags;
2452 cmd->cmd.tx.next_frame_len = 0;
2453}
2454
2455
2456
2457
2458static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
2459{
2460 int sta_id;
2461 u16 fc = le16_to_cpu(hdr->frame_control);
2462
2463
2464 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2465 is_multicast_ether_addr(hdr->addr1))
2466 return priv->hw_setting.bcast_sta_id;
2467
2468 switch (priv->iw_mode) {
2469
2470
2471
2472 case NL80211_IFTYPE_STATION:
2473 return IWL_AP_ID;
2474
2475
2476 case NL80211_IFTYPE_AP:
2477 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
2478 if (sta_id != IWL_INVALID_STATION)
2479 return sta_id;
2480 return priv->hw_setting.bcast_sta_id;
2481
2482
2483
2484 case NL80211_IFTYPE_ADHOC: {
2485 DECLARE_MAC_BUF(mac);
2486
2487
2488 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
2489 if (sta_id != IWL_INVALID_STATION)
2490 return sta_id;
2491
2492 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
2493
2494 if (sta_id != IWL_INVALID_STATION)
2495 return sta_id;
2496
2497 IWL_DEBUG_DROP("Station %s not in station map. "
2498 "Defaulting to broadcast...\n",
2499 print_mac(mac, hdr->addr1));
2500 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
2501 return priv->hw_setting.bcast_sta_id;
2502 }
2503
2504
2505 case NL80211_IFTYPE_MONITOR:
2506 return priv->hw_setting.bcast_sta_id;
2507
2508 default:
2509 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
2510 return priv->hw_setting.bcast_sta_id;
2511 }
2512}
2513
2514
2515
2516
2517static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
2518{
2519 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2520 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2521 struct iwl3945_tfd_frame *tfd;
2522 u32 *control_flags;
2523 int txq_id = skb_get_queue_mapping(skb);
2524 struct iwl3945_tx_queue *txq = NULL;
2525 struct iwl3945_queue *q = NULL;
2526 dma_addr_t phys_addr;
2527 dma_addr_t txcmd_phys;
2528 struct iwl3945_cmd *out_cmd = NULL;
2529 u16 len, idx, len_org, hdr_len;
2530 u8 id;
2531 u8 unicast;
2532 u8 sta_id;
2533 u8 tid = 0;
2534 u16 seq_number = 0;
2535 __le16 fc;
2536 u8 wait_write_ptr = 0;
2537 u8 *qc = NULL;
2538 unsigned long flags;
2539 int rc;
2540
2541 spin_lock_irqsave(&priv->lock, flags);
2542 if (iwl3945_is_rfkill(priv)) {
2543 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2544 goto drop_unlock;
2545 }
2546
2547 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
2548 IWL_ERROR("ERROR: No TX rate available.\n");
2549 goto drop_unlock;
2550 }
2551
2552 unicast = !is_multicast_ether_addr(hdr->addr1);
2553 id = 0;
2554
2555 fc = hdr->frame_control;
2556
2557#ifdef CONFIG_IWL3945_DEBUG
2558 if (ieee80211_is_auth(fc))
2559 IWL_DEBUG_TX("Sending AUTH frame\n");
2560 else if (ieee80211_is_assoc_req(fc))
2561 IWL_DEBUG_TX("Sending ASSOC frame\n");
2562 else if (ieee80211_is_reassoc_req(fc))
2563 IWL_DEBUG_TX("Sending REASSOC frame\n");
2564#endif
2565
2566
2567 if (ieee80211_is_data(fc) &&
2568 (priv->iw_mode != NL80211_IFTYPE_MONITOR) &&
2569 (!iwl3945_is_associated(priv) ||
2570 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
2571 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
2572 goto drop_unlock;
2573 }
2574
2575 spin_unlock_irqrestore(&priv->lock, flags);
2576
2577 hdr_len = ieee80211_hdrlen(fc);
2578
2579
2580 sta_id = iwl3945_get_sta_id(priv, hdr);
2581 if (sta_id == IWL_INVALID_STATION) {
2582 DECLARE_MAC_BUF(mac);
2583
2584 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2585 print_mac(mac, hdr->addr1));
2586 goto drop;
2587 }
2588
2589 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2590
2591 if (ieee80211_is_data_qos(fc)) {
2592 qc = ieee80211_get_qos_ctl(hdr);
2593 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
2594 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2595 IEEE80211_SCTL_SEQ;
2596 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2597 (hdr->seq_ctrl &
2598 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2599 seq_number += 0x10;
2600 }
2601
2602
2603 txq = &priv->txq[txq_id];
2604 q = &txq->q;
2605
2606 spin_lock_irqsave(&priv->lock, flags);
2607
2608
2609 tfd = &txq->bd[q->write_ptr];
2610 memset(tfd, 0, sizeof(*tfd));
2611 control_flags = (u32 *) tfd;
2612 idx = get_cmd_index(q, q->write_ptr, 0);
2613
2614
2615 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
2616 txq->txb[q->write_ptr].skb[0] = skb;
2617
2618
2619 out_cmd = &txq->cmd[idx];
2620 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2621 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
2622
2623
2624
2625
2626
2627
2628
2629 out_cmd->hdr.cmd = REPLY_TX;
2630 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2631 INDEX_TO_SEQ(q->write_ptr)));
2632
2633
2634 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645 len = priv->hw_setting.tx_cmd_len +
2646 sizeof(struct iwl3945_cmd_header) + hdr_len;
2647
2648 len_org = len;
2649 len = (len + 3) & ~3;
2650
2651 if (len_org != len)
2652 len_org = 1;
2653 else
2654 len_org = 0;
2655
2656
2657
2658 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2659 offsetof(struct iwl3945_cmd, hdr);
2660
2661
2662
2663 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
2664
2665 if (info->control.hw_key)
2666 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
2667
2668
2669
2670 len = skb->len - hdr_len;
2671 if (len) {
2672 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2673 len, PCI_DMA_TODEVICE);
2674 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
2675 }
2676
2677 if (!len)
2678
2679 *control_flags = TFD_CTL_COUNT_SET(1);
2680 else
2681
2682
2683 *control_flags = TFD_CTL_COUNT_SET(2) |
2684 TFD_CTL_PAD_SET(U32_PAD(len));
2685
2686
2687 len = (u16)skb->len;
2688 out_cmd->cmd.tx.len = cpu_to_le16(len);
2689
2690
2691 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
2692
2693
2694 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
2695
2696 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2697 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2698
2699 if (!ieee80211_has_morefrags(hdr->frame_control)) {
2700 txq->need_update = 1;
2701 if (qc)
2702 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2703 } else {
2704 wait_write_ptr = 1;
2705 txq->need_update = 0;
2706 }
2707
2708 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
2709 sizeof(out_cmd->cmd.tx));
2710
2711 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
2712 ieee80211_hdrlen(fc));
2713
2714
2715 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
2716 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
2717 spin_unlock_irqrestore(&priv->lock, flags);
2718
2719 if (rc)
2720 return rc;
2721
2722 if ((iwl3945_queue_space(q) < q->high_mark)
2723 && priv->mac80211_registered) {
2724 if (wait_write_ptr) {
2725 spin_lock_irqsave(&priv->lock, flags);
2726 txq->need_update = 1;
2727 iwl3945_tx_queue_update_write_ptr(priv, txq);
2728 spin_unlock_irqrestore(&priv->lock, flags);
2729 }
2730
2731 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
2732 }
2733
2734 return 0;
2735
2736drop_unlock:
2737 spin_unlock_irqrestore(&priv->lock, flags);
2738drop:
2739 return -1;
2740}
2741
2742static void iwl3945_set_rate(struct iwl3945_priv *priv)
2743{
2744 const struct ieee80211_supported_band *sband = NULL;
2745 struct ieee80211_rate *rate;
2746 int i;
2747
2748 sband = iwl3945_get_band(priv, priv->band);
2749 if (!sband) {
2750 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2751 return;
2752 }
2753
2754 priv->active_rate = 0;
2755 priv->active_rate_basic = 0;
2756
2757 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2758 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2759
2760 for (i = 0; i < sband->n_bitrates; i++) {
2761 rate = &sband->bitrates[i];
2762 if ((rate->hw_value < IWL_RATE_COUNT) &&
2763 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2764 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2765 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2766 priv->active_rate |= (1 << rate->hw_value);
2767 }
2768 }
2769
2770 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2771 priv->active_rate, priv->active_rate_basic);
2772
2773
2774
2775
2776
2777
2778 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2779 priv->staging_rxon.cck_basic_rates =
2780 ((priv->active_rate_basic &
2781 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2782 else
2783 priv->staging_rxon.cck_basic_rates =
2784 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2785
2786 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2787 priv->staging_rxon.ofdm_basic_rates =
2788 ((priv->active_rate_basic &
2789 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2790 IWL_FIRST_OFDM_RATE) & 0xFF;
2791 else
2792 priv->staging_rxon.ofdm_basic_rates =
2793 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2794}
2795
2796static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
2797{
2798 unsigned long flags;
2799
2800 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2801 return;
2802
2803 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2804 disable_radio ? "OFF" : "ON");
2805
2806 if (disable_radio) {
2807 iwl3945_scan_cancel(priv);
2808
2809 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2810 spin_lock_irqsave(&priv->lock, flags);
2811 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
2812 CSR_UCODE_SW_BIT_RFKILL);
2813 spin_unlock_irqrestore(&priv->lock, flags);
2814 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
2815 set_bit(STATUS_RF_KILL_SW, &priv->status);
2816 }
2817 return;
2818 }
2819
2820 spin_lock_irqsave(&priv->lock, flags);
2821 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2822
2823 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2824 spin_unlock_irqrestore(&priv->lock, flags);
2825
2826
2827 msleep(10);
2828
2829 spin_lock_irqsave(&priv->lock, flags);
2830 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2831 if (!iwl3945_grab_nic_access(priv))
2832 iwl3945_release_nic_access(priv);
2833 spin_unlock_irqrestore(&priv->lock, flags);
2834
2835 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2836 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2837 "disabled by HW switch\n");
2838 return;
2839 }
2840
2841 if (priv->is_open)
2842 queue_work(priv->workqueue, &priv->restart);
2843 return;
2844}
2845
2846void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
2847 u32 decrypt_res, struct ieee80211_rx_status *stats)
2848{
2849 u16 fc =
2850 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2851
2852 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2853 return;
2854
2855 if (!(fc & IEEE80211_FCTL_PROTECTED))
2856 return;
2857
2858 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2859 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2860 case RX_RES_STATUS_SEC_TYPE_TKIP:
2861 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2862 RX_RES_STATUS_BAD_ICV_MIC)
2863 stats->flag |= RX_FLAG_MMIC_ERROR;
2864 case RX_RES_STATUS_SEC_TYPE_WEP:
2865 case RX_RES_STATUS_SEC_TYPE_CCMP:
2866 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2867 RX_RES_STATUS_DECRYPT_OK) {
2868 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2869 stats->flag |= RX_FLAG_DECRYPTED;
2870 }
2871 break;
2872
2873 default:
2874 break;
2875 }
2876}
2877
2878#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
2879
2880#include "iwl-spectrum.h"
2881
2882#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2883#define BEACON_TIME_MASK_HIGH 0xFF000000
2884#define TIME_UNIT 1024
2885
2886
2887
2888
2889
2890
2891
2892
2893static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
2894{
2895 u32 quot;
2896 u32 rem;
2897 u32 interval = beacon_interval * 1024;
2898
2899 if (!interval || !usec)
2900 return 0;
2901
2902 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2903 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2904
2905 return (quot << 24) + rem;
2906}
2907
2908
2909
2910
2911
2912static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
2913{
2914 u32 base_low = base & BEACON_TIME_MASK_LOW;
2915 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2916 u32 interval = beacon_interval * TIME_UNIT;
2917 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2918 (addon & BEACON_TIME_MASK_HIGH);
2919
2920 if (base_low > addon_low)
2921 res += base_low - addon_low;
2922 else if (base_low < addon_low) {
2923 res += interval + base_low - addon_low;
2924 res += (1 << 24);
2925 } else
2926 res += (1 << 24);
2927
2928 return cpu_to_le32(res);
2929}
2930
2931static int iwl3945_get_measurement(struct iwl3945_priv *priv,
2932 struct ieee80211_measurement_params *params,
2933 u8 type)
2934{
2935 struct iwl3945_spectrum_cmd spectrum;
2936 struct iwl3945_rx_packet *res;
2937 struct iwl3945_host_cmd cmd = {
2938 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2939 .data = (void *)&spectrum,
2940 .meta.flags = CMD_WANT_SKB,
2941 };
2942 u32 add_time = le64_to_cpu(params->start_time);
2943 int rc;
2944 int spectrum_resp_status;
2945 int duration = le16_to_cpu(params->duration);
2946
2947 if (iwl3945_is_associated(priv))
2948 add_time =
2949 iwl3945_usecs_to_beacons(
2950 le64_to_cpu(params->start_time) - priv->last_tsf,
2951 le16_to_cpu(priv->rxon_timing.beacon_interval));
2952
2953 memset(&spectrum, 0, sizeof(spectrum));
2954
2955 spectrum.channel_count = cpu_to_le16(1);
2956 spectrum.flags =
2957 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2958 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2959 cmd.len = sizeof(spectrum);
2960 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2961
2962 if (iwl3945_is_associated(priv))
2963 spectrum.start_time =
2964 iwl3945_add_beacon_time(priv->last_beacon_time,
2965 add_time,
2966 le16_to_cpu(priv->rxon_timing.beacon_interval));
2967 else
2968 spectrum.start_time = 0;
2969
2970 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2971 spectrum.channels[0].channel = params->channel;
2972 spectrum.channels[0].type = type;
2973 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2974 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2975 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2976
2977 rc = iwl3945_send_cmd_sync(priv, &cmd);
2978 if (rc)
2979 return rc;
2980
2981 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
2982 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2983 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2984 rc = -EIO;
2985 }
2986
2987 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2988 switch (spectrum_resp_status) {
2989 case 0:
2990 if (res->u.spectrum.id != 0xff) {
2991 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2992 res->u.spectrum.id);
2993 priv->measurement_status &= ~MEASUREMENT_READY;
2994 }
2995 priv->measurement_status |= MEASUREMENT_ACTIVE;
2996 rc = 0;
2997 break;
2998
2999 case 1:
3000 rc = -EAGAIN;
3001 break;
3002 }
3003
3004 dev_kfree_skb_any(cmd.meta.u.skb);
3005
3006 return rc;
3007}
3008#endif
3009
3010static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3011 struct iwl3945_rx_mem_buffer *rxb)
3012{
3013 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3014 struct iwl3945_alive_resp *palive;
3015 struct delayed_work *pwork;
3016
3017 palive = &pkt->u.alive_frame;
3018
3019 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3020 "0x%01X 0x%01X\n",
3021 palive->is_valid, palive->ver_type,
3022 palive->ver_subtype);
3023
3024 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3025 IWL_DEBUG_INFO("Initialization Alive received.\n");
3026 memcpy(&priv->card_alive_init,
3027 &pkt->u.alive_frame,
3028 sizeof(struct iwl3945_init_alive_resp));
3029 pwork = &priv->init_alive_start;
3030 } else {
3031 IWL_DEBUG_INFO("Runtime Alive received.\n");
3032 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3033 sizeof(struct iwl3945_alive_resp));
3034 pwork = &priv->alive_start;
3035 iwl3945_disable_events(priv);
3036 }
3037
3038
3039
3040 if (palive->is_valid == UCODE_VALID_OK)
3041 queue_delayed_work(priv->workqueue, pwork,
3042 msecs_to_jiffies(5));
3043 else
3044 IWL_WARNING("uCode did not respond OK.\n");
3045}
3046
3047static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3048 struct iwl3945_rx_mem_buffer *rxb)
3049{
3050 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3051
3052 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3053 return;
3054}
3055
3056static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3057 struct iwl3945_rx_mem_buffer *rxb)
3058{
3059 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3060
3061 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3062 "seq 0x%04X ser 0x%08X\n",
3063 le32_to_cpu(pkt->u.err_resp.error_type),
3064 get_cmd_string(pkt->u.err_resp.cmd_id),
3065 pkt->u.err_resp.cmd_id,
3066 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3067 le32_to_cpu(pkt->u.err_resp.error_info));
3068}
3069
3070#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3071
3072static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
3073{
3074 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3075 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3076 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
3077 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3078 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3079 rxon->channel = csa->channel;
3080 priv->staging_rxon.channel = csa->channel;
3081}
3082
3083static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3084 struct iwl3945_rx_mem_buffer *rxb)
3085{
3086#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3087 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3088 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
3089
3090 if (!report->state) {
3091 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3092 "Spectrum Measure Notification: Start\n");
3093 return;
3094 }
3095
3096 memcpy(&priv->measure_report, report, sizeof(*report));
3097 priv->measurement_status |= MEASUREMENT_READY;
3098#endif
3099}
3100
3101static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3102 struct iwl3945_rx_mem_buffer *rxb)
3103{
3104#ifdef CONFIG_IWL3945_DEBUG
3105 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3106 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
3107 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3108 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3109#endif
3110}
3111
3112static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3113 struct iwl3945_rx_mem_buffer *rxb)
3114{
3115 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3116 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3117 "notification for %s:\n",
3118 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
3119 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
3120}
3121
3122static void iwl3945_bg_beacon_update(struct work_struct *work)
3123{
3124 struct iwl3945_priv *priv =
3125 container_of(work, struct iwl3945_priv, beacon_update);
3126 struct sk_buff *beacon;
3127
3128
3129 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
3130
3131 if (!beacon) {
3132 IWL_ERROR("update beacon failed\n");
3133 return;
3134 }
3135
3136 mutex_lock(&priv->mutex);
3137
3138 if (priv->ibss_beacon)
3139 dev_kfree_skb(priv->ibss_beacon);
3140
3141 priv->ibss_beacon = beacon;
3142 mutex_unlock(&priv->mutex);
3143
3144 iwl3945_send_beacon_cmd(priv);
3145}
3146
3147static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3148 struct iwl3945_rx_mem_buffer *rxb)
3149{
3150#ifdef CONFIG_IWL3945_DEBUG
3151 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3152 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
3153 u8 rate = beacon->beacon_notify_hdr.rate;
3154
3155 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3156 "tsf %d %d rate %d\n",
3157 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3158 beacon->beacon_notify_hdr.failure_frame,
3159 le32_to_cpu(beacon->ibss_mgr_status),
3160 le32_to_cpu(beacon->high_tsf),
3161 le32_to_cpu(beacon->low_tsf), rate);
3162#endif
3163
3164 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
3165 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3166 queue_work(priv->workqueue, &priv->beacon_update);
3167}
3168
3169
3170static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3171 struct iwl3945_rx_mem_buffer *rxb)
3172{
3173#ifdef CONFIG_IWL3945_DEBUG
3174 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3175 struct iwl3945_scanreq_notification *notif =
3176 (struct iwl3945_scanreq_notification *)pkt->u.raw;
3177
3178 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3179#endif
3180}
3181
3182
3183static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3184 struct iwl3945_rx_mem_buffer *rxb)
3185{
3186 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3187 struct iwl3945_scanstart_notification *notif =
3188 (struct iwl3945_scanstart_notification *)pkt->u.raw;
3189 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3190 IWL_DEBUG_SCAN("Scan start: "
3191 "%d [802.11%s] "
3192 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3193 notif->channel,
3194 notif->band ? "bg" : "a",
3195 notif->tsf_high,
3196 notif->tsf_low, notif->status, notif->beacon_timer);
3197}
3198
3199
3200static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3201 struct iwl3945_rx_mem_buffer *rxb)
3202{
3203 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3204 struct iwl3945_scanresults_notification *notif =
3205 (struct iwl3945_scanresults_notification *)pkt->u.raw;
3206
3207 IWL_DEBUG_SCAN("Scan ch.res: "
3208 "%d [802.11%s] "
3209 "(TSF: 0x%08X:%08X) - %d "
3210 "elapsed=%lu usec (%dms since last)\n",
3211 notif->channel,
3212 notif->band ? "bg" : "a",
3213 le32_to_cpu(notif->tsf_high),
3214 le32_to_cpu(notif->tsf_low),
3215 le32_to_cpu(notif->statistics[0]),
3216 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3217 jiffies_to_msecs(elapsed_jiffies
3218 (priv->last_scan_jiffies, jiffies)));
3219
3220 priv->last_scan_jiffies = jiffies;
3221 priv->next_scan_jiffies = 0;
3222}
3223
3224
3225static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3226 struct iwl3945_rx_mem_buffer *rxb)
3227{
3228 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3229 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
3230
3231 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3232 scan_notif->scanned_channels,
3233 scan_notif->tsf_low,
3234 scan_notif->tsf_high, scan_notif->status);
3235
3236
3237 clear_bit(STATUS_SCAN_HW, &priv->status);
3238
3239
3240 cancel_delayed_work(&priv->scan_check);
3241
3242 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3243 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3244 "2.4" : "5.2",
3245 jiffies_to_msecs(elapsed_jiffies
3246 (priv->scan_pass_start, jiffies)));
3247
3248
3249
3250
3251 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3252 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3253 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3254 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
3255
3256
3257
3258
3259 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3260 IWL_DEBUG_INFO("Aborted scan completed.\n");
3261 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3262 } else {
3263
3264 if (priv->scan_bands > 0)
3265 goto reschedule;
3266 }
3267
3268 priv->last_scan_jiffies = jiffies;
3269 priv->next_scan_jiffies = 0;
3270 IWL_DEBUG_INFO("Setting scan to off\n");
3271
3272 clear_bit(STATUS_SCANNING, &priv->status);
3273
3274 IWL_DEBUG_INFO("Scan took %dms\n",
3275 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3276
3277 queue_work(priv->workqueue, &priv->scan_completed);
3278
3279 return;
3280
3281reschedule:
3282 priv->scan_pass_start = jiffies;
3283 queue_work(priv->workqueue, &priv->request_scan);
3284}
3285
3286
3287
3288static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3289 struct iwl3945_rx_mem_buffer *rxb)
3290{
3291 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3292 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3293 unsigned long status = priv->status;
3294
3295 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3296 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3297 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3298
3299 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
3300 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3301
3302 if (flags & HW_CARD_DISABLED)
3303 set_bit(STATUS_RF_KILL_HW, &priv->status);
3304 else
3305 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3306
3307
3308 if (flags & SW_CARD_DISABLED)
3309 set_bit(STATUS_RF_KILL_SW, &priv->status);
3310 else
3311 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3312
3313 iwl3945_scan_cancel(priv);
3314
3315 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3316 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3317 (test_bit(STATUS_RF_KILL_SW, &status) !=
3318 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3319 queue_work(priv->workqueue, &priv->rf_kill);
3320 else
3321 wake_up_interruptible(&priv->wait_command_queue);
3322}
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
3334{
3335 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3336 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3337 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3338 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
3339 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
3340 iwl3945_rx_spectrum_measure_notif;
3341 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
3342 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
3343 iwl3945_rx_pm_debug_statistics_notif;
3344 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
3345
3346
3347
3348
3349
3350
3351 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3352 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
3353
3354 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3355 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
3356 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
3357 iwl3945_rx_scan_results_notif;
3358 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
3359 iwl3945_rx_scan_complete_notif;
3360 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
3361
3362
3363 iwl3945_hw_rx_handler_setup(priv);
3364}
3365
3366
3367
3368
3369
3370
3371static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3372 int txq_id, int index)
3373{
3374 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3375 struct iwl3945_queue *q = &txq->q;
3376 int nfreed = 0;
3377
3378 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3379 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3380 "is out of range [0-%d] %d %d.\n", txq_id,
3381 index, q->n_bd, q->write_ptr, q->read_ptr);
3382 return;
3383 }
3384
3385 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3386 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3387 if (nfreed > 1) {
3388 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3389 q->write_ptr, q->read_ptr);
3390 queue_work(priv->workqueue, &priv->restart);
3391 break;
3392 }
3393 nfreed++;
3394 }
3395}
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3407 struct iwl3945_rx_mem_buffer *rxb)
3408{
3409 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
3410 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3411 int txq_id = SEQ_TO_QUEUE(sequence);
3412 int index = SEQ_TO_INDEX(sequence);
3413 int huge = sequence & SEQ_HUGE_FRAME;
3414 int cmd_index;
3415 struct iwl3945_cmd *cmd;
3416
3417 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3418
3419 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3420 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3421
3422
3423 if (cmd->meta.flags & CMD_WANT_SKB) {
3424 cmd->meta.source->u.skb = rxb->skb;
3425 rxb->skb = NULL;
3426 } else if (cmd->meta.u.callback &&
3427 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3428 rxb->skb = NULL;
3429
3430 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
3431
3432 if (!(cmd->meta.flags & CMD_ASYNC)) {
3433 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3434 wake_up_interruptible(&priv->wait_command_queue);
3435 }
3436}
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
3507{
3508 int s = q->read - q->write;
3509 if (s <= 0)
3510 s += RX_QUEUE_SIZE;
3511
3512 s -= 2;
3513 if (s < 0)
3514 s = 0;
3515 return s;
3516}
3517
3518
3519
3520
3521int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
3522{
3523 u32 reg = 0;
3524 int rc = 0;
3525 unsigned long flags;
3526
3527 spin_lock_irqsave(&q->lock, flags);
3528
3529 if (q->need_update == 0)
3530 goto exit_unlock;
3531
3532
3533 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3534 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3535
3536 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3537 iwl3945_set_bit(priv, CSR_GP_CNTRL,
3538 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3539 goto exit_unlock;
3540 }
3541
3542 rc = iwl3945_grab_nic_access(priv);
3543 if (rc)
3544 goto exit_unlock;
3545
3546
3547 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
3548 q->write & ~0x7);
3549 iwl3945_release_nic_access(priv);
3550
3551
3552 } else
3553
3554 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
3555
3556
3557 q->need_update = 0;
3558
3559 exit_unlock:
3560 spin_unlock_irqrestore(&q->lock, flags);
3561 return rc;
3562}
3563
3564
3565
3566
3567static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
3568 dma_addr_t dma_addr)
3569{
3570 return cpu_to_le32((u32)dma_addr);
3571}
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
3585{
3586 struct iwl3945_rx_queue *rxq = &priv->rxq;
3587 struct list_head *element;
3588 struct iwl3945_rx_mem_buffer *rxb;
3589 unsigned long flags;
3590 int write, rc;
3591
3592 spin_lock_irqsave(&rxq->lock, flags);
3593 write = rxq->write & ~0x7;
3594 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
3595
3596 element = rxq->rx_free.next;
3597 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
3598 list_del(element);
3599
3600
3601 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
3602 rxq->queue[rxq->write] = rxb;
3603 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3604 rxq->free_count--;
3605 }
3606 spin_unlock_irqrestore(&rxq->lock, flags);
3607
3608
3609 if (rxq->free_count <= RX_LOW_WATERMARK)
3610 queue_work(priv->workqueue, &priv->rx_replenish);
3611
3612
3613
3614
3615 if ((write != (rxq->write & ~0x7))
3616 || (abs(rxq->write - rxq->read) > 7)) {
3617 spin_lock_irqsave(&rxq->lock, flags);
3618 rxq->need_update = 1;
3619 spin_unlock_irqrestore(&rxq->lock, flags);
3620 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
3621 if (rc)
3622 return rc;
3623 }
3624
3625 return 0;
3626}
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
3637{
3638 struct iwl3945_rx_queue *rxq = &priv->rxq;
3639 struct list_head *element;
3640 struct iwl3945_rx_mem_buffer *rxb;
3641 unsigned long flags;
3642 spin_lock_irqsave(&rxq->lock, flags);
3643 while (!list_empty(&rxq->rx_used)) {
3644 element = rxq->rx_used.next;
3645 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
3646
3647
3648 rxb->skb =
3649 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3650 if (!rxb->skb) {
3651 if (net_ratelimit())
3652 printk(KERN_CRIT DRV_NAME
3653 ": Can not allocate SKB buffers\n");
3654
3655
3656
3657 break;
3658 }
3659
3660
3661
3662
3663
3664
3665
3666 skb_reserve(rxb->skb, 4);
3667
3668 priv->alloc_rxb_skb++;
3669 list_del(element);
3670
3671
3672 rxb->dma_addr =
3673 pci_map_single(priv->pci_dev, rxb->skb->data,
3674 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3675 list_add_tail(&rxb->list, &rxq->rx_free);
3676 rxq->free_count++;
3677 }
3678 spin_unlock_irqrestore(&rxq->lock, flags);
3679}
3680
3681
3682
3683
3684static void __iwl3945_rx_replenish(void *data)
3685{
3686 struct iwl3945_priv *priv = data;
3687
3688 iwl3945_rx_allocate(priv);
3689 iwl3945_rx_queue_restock(priv);
3690}
3691
3692
3693void iwl3945_rx_replenish(void *data)
3694{
3695 struct iwl3945_priv *priv = data;
3696 unsigned long flags;
3697
3698 iwl3945_rx_allocate(priv);
3699
3700 spin_lock_irqsave(&priv->lock, flags);
3701 iwl3945_rx_queue_restock(priv);
3702 spin_unlock_irqrestore(&priv->lock, flags);
3703}
3704
3705
3706
3707
3708
3709
3710static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
3711{
3712 int i;
3713 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3714 if (rxq->pool[i].skb != NULL) {
3715 pci_unmap_single(priv->pci_dev,
3716 rxq->pool[i].dma_addr,
3717 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3718 dev_kfree_skb(rxq->pool[i].skb);
3719 }
3720 }
3721
3722 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3723 rxq->dma_addr);
3724 rxq->bd = NULL;
3725}
3726
3727int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
3728{
3729 struct iwl3945_rx_queue *rxq = &priv->rxq;
3730 struct pci_dev *dev = priv->pci_dev;
3731 int i;
3732
3733 spin_lock_init(&rxq->lock);
3734 INIT_LIST_HEAD(&rxq->rx_free);
3735 INIT_LIST_HEAD(&rxq->rx_used);
3736
3737
3738 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3739 if (!rxq->bd)
3740 return -ENOMEM;
3741
3742
3743 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3744 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3745
3746
3747
3748 rxq->read = rxq->write = 0;
3749 rxq->free_count = 0;
3750 rxq->need_update = 0;
3751 return 0;
3752}
3753
3754void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
3755{
3756 unsigned long flags;
3757 int i;
3758 spin_lock_irqsave(&rxq->lock, flags);
3759 INIT_LIST_HEAD(&rxq->rx_free);
3760 INIT_LIST_HEAD(&rxq->rx_used);
3761
3762 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3763
3764
3765 if (rxq->pool[i].skb != NULL) {
3766 pci_unmap_single(priv->pci_dev,
3767 rxq->pool[i].dma_addr,
3768 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3769 priv->alloc_rxb_skb--;
3770 dev_kfree_skb(rxq->pool[i].skb);
3771 rxq->pool[i].skb = NULL;
3772 }
3773 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3774 }
3775
3776
3777
3778 rxq->read = rxq->write = 0;
3779 rxq->free_count = 0;
3780 spin_unlock_irqrestore(&rxq->lock, flags);
3781}
3782
3783
3784static u8 ratio2dB[100] = {
3785
3786 0, 0, 6, 10, 12, 14, 16, 17, 18, 19,
3787 20, 21, 22, 22, 23, 23, 24, 25, 26, 26,
3788 26, 26, 26, 27, 27, 28, 28, 28, 29, 29,
3789 29, 30, 30, 30, 31, 31, 31, 31, 32, 32,
3790 32, 32, 32, 33, 33, 33, 33, 33, 34, 34,
3791 34, 34, 34, 34, 35, 35, 35, 35, 35, 35,
3792 36, 36, 36, 36, 36, 36, 36, 37, 37, 37,
3793 37, 37, 37, 37, 37, 38, 38, 38, 38, 38,
3794 38, 38, 38, 38, 38, 39, 39, 39, 39, 39,
3795 39, 39, 39, 39, 39, 40, 40, 40, 40, 40
3796};
3797
3798
3799
3800
3801int iwl3945_calc_db_from_ratio(int sig_ratio)
3802{
3803
3804 if (sig_ratio >= 1000)
3805 return 60;
3806
3807
3808
3809 if (sig_ratio >= 100)
3810 return 20 + (int)ratio2dB[sig_ratio/10];
3811
3812
3813 if (sig_ratio < 1)
3814 return 0;
3815
3816
3817 return (int)ratio2dB[sig_ratio];
3818}
3819
3820#define PERFECT_RSSI (-20)
3821#define WORST_RSSI (-95)
3822#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3823
3824
3825
3826
3827int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
3828{
3829 int sig_qual;
3830 int degradation = PERFECT_RSSI - rssi_dbm;
3831
3832
3833
3834
3835
3836
3837 if (noise_dbm) {
3838 if (rssi_dbm - noise_dbm >= 40)
3839 return 100;
3840 else if (rssi_dbm < noise_dbm)
3841 return 0;
3842 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3843
3844
3845
3846
3847
3848 } else
3849 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3850 (15 * RSSI_RANGE + 62 * degradation)) /
3851 (RSSI_RANGE * RSSI_RANGE);
3852
3853 if (sig_qual > 100)
3854 sig_qual = 100;
3855 else if (sig_qual < 1)
3856 sig_qual = 0;
3857
3858 return sig_qual;
3859}
3860
3861
3862
3863
3864
3865
3866
3867
3868static void iwl3945_rx_handle(struct iwl3945_priv *priv)
3869{
3870 struct iwl3945_rx_mem_buffer *rxb;
3871 struct iwl3945_rx_packet *pkt;
3872 struct iwl3945_rx_queue *rxq = &priv->rxq;
3873 u32 r, i;
3874 int reclaim;
3875 unsigned long flags;
3876 u8 fill_rx = 0;
3877 u32 count = 8;
3878
3879
3880
3881 r = iwl3945_hw_get_rx_read(priv);
3882 i = rxq->read;
3883
3884 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3885 fill_rx = 1;
3886
3887 if (i == r)
3888 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3889
3890 while (i != r) {
3891 rxb = rxq->queue[i];
3892
3893
3894
3895
3896 BUG_ON(rxb == NULL);
3897
3898 rxq->queue[i] = NULL;
3899
3900 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3901 IWL_RX_BUF_SIZE,
3902 PCI_DMA_FROMDEVICE);
3903 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
3904
3905
3906
3907
3908
3909
3910
3911 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3912 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3913 (pkt->hdr.cmd != REPLY_TX);
3914
3915
3916
3917
3918 if (priv->rx_handlers[pkt->hdr.cmd]) {
3919 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3920 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3921 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3922 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3923 } else {
3924
3925 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3926 "r %d i %d No handler needed for %s, 0x%02x\n",
3927 r, i, get_cmd_string(pkt->hdr.cmd),
3928 pkt->hdr.cmd);
3929 }
3930
3931 if (reclaim) {
3932
3933
3934
3935 if (rxb && rxb->skb)
3936 iwl3945_tx_cmd_complete(priv, rxb);
3937 else
3938 IWL_WARNING("Claim null rxb?\n");
3939 }
3940
3941
3942
3943
3944 if (rxb->skb != NULL) {
3945 priv->alloc_rxb_skb--;
3946 dev_kfree_skb_any(rxb->skb);
3947 rxb->skb = NULL;
3948 }
3949
3950 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3951 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3952 spin_lock_irqsave(&rxq->lock, flags);
3953 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3954 spin_unlock_irqrestore(&rxq->lock, flags);
3955 i = (i + 1) & RX_QUEUE_MASK;
3956
3957
3958 if (fill_rx) {
3959 count++;
3960 if (count >= 8) {
3961 priv->rxq.read = i;
3962 __iwl3945_rx_replenish(priv);
3963 count = 0;
3964 }
3965 }
3966 }
3967
3968
3969 priv->rxq.read = i;
3970 iwl3945_rx_queue_restock(priv);
3971}
3972
3973
3974
3975
3976static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3977 struct iwl3945_tx_queue *txq)
3978{
3979 u32 reg = 0;
3980 int rc = 0;
3981 int txq_id = txq->q.id;
3982
3983 if (txq->need_update == 0)
3984 return rc;
3985
3986
3987 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3988
3989
3990
3991 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3992
3993 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3994 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
3995 iwl3945_set_bit(priv, CSR_GP_CNTRL,
3996 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3997 return rc;
3998 }
3999
4000
4001 rc = iwl3945_grab_nic_access(priv);
4002 if (rc)
4003 return rc;
4004 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
4005 txq->q.write_ptr | (txq_id << 8));
4006 iwl3945_release_nic_access(priv);
4007
4008
4009
4010 } else
4011 iwl3945_write32(priv, HBUS_TARG_WRPTR,
4012 txq->q.write_ptr | (txq_id << 8));
4013
4014 txq->need_update = 0;
4015
4016 return rc;
4017}
4018
4019#ifdef CONFIG_IWL3945_DEBUG
4020static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
4021{
4022 DECLARE_MAC_BUF(mac);
4023
4024 IWL_DEBUG_RADIO("RX CONFIG:\n");
4025 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
4026 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4027 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4028 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4029 le32_to_cpu(rxon->filter_flags));
4030 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4031 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4032 rxon->ofdm_basic_rates);
4033 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
4034 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4035 print_mac(mac, rxon->node_addr));
4036 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4037 print_mac(mac, rxon->bssid_addr));
4038 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4039}
4040#endif
4041
4042static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
4043{
4044 IWL_DEBUG_ISR("Enabling interrupts\n");
4045 set_bit(STATUS_INT_ENABLED, &priv->status);
4046 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
4047}
4048
4049
4050
4051static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4052{
4053
4054 synchronize_irq(priv->pci_dev->irq);
4055 tasklet_kill(&priv->irq_tasklet);
4056}
4057
4058
4059static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
4060{
4061 clear_bit(STATUS_INT_ENABLED, &priv->status);
4062
4063
4064 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
4065
4066
4067
4068 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4069 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
4070 IWL_DEBUG_ISR("Disabled interrupts\n");
4071}
4072
4073static const char *desc_lookup(int i)
4074{
4075 switch (i) {
4076 case 1:
4077 return "FAIL";
4078 case 2:
4079 return "BAD_PARAM";
4080 case 3:
4081 return "BAD_CHECKSUM";
4082 case 4:
4083 return "NMI_INTERRUPT";
4084 case 5:
4085 return "SYSASSERT";
4086 case 6:
4087 return "FATAL_ERROR";
4088 }
4089
4090 return "UNKNOWN";
4091}
4092
4093#define ERROR_START_OFFSET (1 * sizeof(u32))
4094#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4095
4096static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
4097{
4098 u32 i;
4099 u32 desc, time, count, base, data1;
4100 u32 blink1, blink2, ilink1, ilink2;
4101 int rc;
4102
4103 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4104
4105 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
4106 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4107 return;
4108 }
4109
4110 rc = iwl3945_grab_nic_access(priv);
4111 if (rc) {
4112 IWL_WARNING("Can not read from adapter at this time.\n");
4113 return;
4114 }
4115
4116 count = iwl3945_read_targ_mem(priv, base);
4117
4118 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4119 IWL_ERROR("Start IWL Error Log Dump:\n");
4120 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
4121 }
4122
4123 IWL_ERROR("Desc Time asrtPC blink2 "
4124 "ilink1 nmiPC Line\n");
4125 for (i = ERROR_START_OFFSET;
4126 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4127 i += ERROR_ELEM_SIZE) {
4128 desc = iwl3945_read_targ_mem(priv, base + i);
4129 time =
4130 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
4131 blink1 =
4132 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
4133 blink2 =
4134 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
4135 ilink1 =
4136 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
4137 ilink2 =
4138 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
4139 data1 =
4140 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
4141
4142 IWL_ERROR
4143 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4144 desc_lookup(desc), desc, time, blink1, blink2,
4145 ilink1, ilink2, data1);
4146 }
4147
4148 iwl3945_release_nic_access(priv);
4149
4150}
4151
4152#define EVENT_START_OFFSET (6 * sizeof(u32))
4153
4154
4155
4156
4157
4158
4159static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
4160 u32 num_events, u32 mode)
4161{
4162 u32 i;
4163 u32 base;
4164 u32 event_size;
4165 u32 ptr;
4166 u32 ev, time, data;
4167
4168 if (num_events == 0)
4169 return;
4170
4171 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4172
4173 if (mode == 0)
4174 event_size = 2 * sizeof(u32);
4175 else
4176 event_size = 3 * sizeof(u32);
4177
4178 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4179
4180
4181
4182 for (i = 0; i < num_events; i++) {
4183 ev = iwl3945_read_targ_mem(priv, ptr);
4184 ptr += sizeof(u32);
4185 time = iwl3945_read_targ_mem(priv, ptr);
4186 ptr += sizeof(u32);
4187 if (mode == 0)
4188 IWL_ERROR("0x%08x\t%04u\n", time, ev);
4189 else {
4190 data = iwl3945_read_targ_mem(priv, ptr);
4191 ptr += sizeof(u32);
4192 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4193 }
4194 }
4195}
4196
4197static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
4198{
4199 int rc;
4200 u32 base;
4201 u32 capacity;
4202 u32 mode;
4203 u32 num_wraps;
4204 u32 next_entry;
4205 u32 size;
4206
4207 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4208 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
4209 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4210 return;
4211 }
4212
4213 rc = iwl3945_grab_nic_access(priv);
4214 if (rc) {
4215 IWL_WARNING("Can not read from adapter at this time.\n");
4216 return;
4217 }
4218
4219
4220 capacity = iwl3945_read_targ_mem(priv, base);
4221 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4222 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4223 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
4224
4225 size = num_wraps ? capacity : next_entry;
4226
4227
4228 if (size == 0) {
4229 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
4230 iwl3945_release_nic_access(priv);
4231 return;
4232 }
4233
4234 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
4235 size, num_wraps);
4236
4237
4238
4239 if (num_wraps)
4240 iwl3945_print_event_log(priv, next_entry,
4241 capacity - next_entry, mode);
4242
4243
4244 iwl3945_print_event_log(priv, 0, next_entry, mode);
4245
4246 iwl3945_release_nic_access(priv);
4247}
4248
4249
4250
4251
4252static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
4253{
4254
4255 set_bit(STATUS_FW_ERROR, &priv->status);
4256
4257
4258 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4259
4260#ifdef CONFIG_IWL3945_DEBUG
4261 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4262 iwl3945_dump_nic_error_log(priv);
4263 iwl3945_dump_nic_event_log(priv);
4264 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
4265 }
4266#endif
4267
4268 wake_up_interruptible(&priv->wait_command_queue);
4269
4270
4271
4272 clear_bit(STATUS_READY, &priv->status);
4273
4274 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4275 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4276 "Restarting adapter due to uCode error.\n");
4277
4278 if (iwl3945_is_associated(priv)) {
4279 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4280 sizeof(priv->recovery_rxon));
4281 priv->error_recovering = 1;
4282 }
4283 queue_work(priv->workqueue, &priv->restart);
4284 }
4285}
4286
4287static void iwl3945_error_recovery(struct iwl3945_priv *priv)
4288{
4289 unsigned long flags;
4290
4291 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4292 sizeof(priv->staging_rxon));
4293 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
4294 iwl3945_commit_rxon(priv);
4295
4296 iwl3945_add_station(priv, priv->bssid, 1, 0);
4297
4298 spin_lock_irqsave(&priv->lock, flags);
4299 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4300 priv->error_recovering = 0;
4301 spin_unlock_irqrestore(&priv->lock, flags);
4302}
4303
4304static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
4305{
4306 u32 inta, handled = 0;
4307 u32 inta_fh;
4308 unsigned long flags;
4309#ifdef CONFIG_IWL3945_DEBUG
4310 u32 inta_mask;
4311#endif
4312
4313 spin_lock_irqsave(&priv->lock, flags);
4314
4315
4316
4317
4318 inta = iwl3945_read32(priv, CSR_INT);
4319 iwl3945_write32(priv, CSR_INT, inta);
4320
4321
4322
4323
4324 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4325 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
4326
4327#ifdef CONFIG_IWL3945_DEBUG
4328 if (iwl3945_debug_level & IWL_DL_ISR) {
4329
4330 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4331 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4332 inta, inta_mask, inta_fh);
4333 }
4334#endif
4335
4336
4337
4338
4339
4340 if (inta_fh & CSR39_FH_INT_RX_MASK)
4341 inta |= CSR_INT_BIT_FH_RX;
4342 if (inta_fh & CSR39_FH_INT_TX_MASK)
4343 inta |= CSR_INT_BIT_FH_TX;
4344
4345
4346 if (inta & CSR_INT_BIT_HW_ERR) {
4347 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4348
4349
4350 iwl3945_disable_interrupts(priv);
4351
4352 iwl3945_irq_handle_error(priv);
4353
4354 handled |= CSR_INT_BIT_HW_ERR;
4355
4356 spin_unlock_irqrestore(&priv->lock, flags);
4357
4358 return;
4359 }
4360
4361#ifdef CONFIG_IWL3945_DEBUG
4362 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4363
4364 if (inta & CSR_INT_BIT_SCD)
4365 IWL_DEBUG_ISR("Scheduler finished to transmit "
4366 "the frame/frames.\n");
4367
4368
4369 if (inta & CSR_INT_BIT_ALIVE)
4370 IWL_DEBUG_ISR("Alive interrupt\n");
4371 }
4372#endif
4373
4374 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4375
4376
4377 if (inta & CSR_INT_BIT_RF_KILL) {
4378 int hw_rf_kill = 0;
4379 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
4380 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4381 hw_rf_kill = 1;
4382
4383 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4384 "RF_KILL bit toggled to %s.\n",
4385 hw_rf_kill ? "disable radio":"enable radio");
4386
4387
4388
4389
4390
4391 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4392 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4393 queue_work(priv->workqueue, &priv->restart);
4394 }
4395
4396 handled |= CSR_INT_BIT_RF_KILL;
4397 }
4398
4399
4400 if (inta & CSR_INT_BIT_CT_KILL) {
4401 IWL_ERROR("Microcode CT kill error detected.\n");
4402 handled |= CSR_INT_BIT_CT_KILL;
4403 }
4404
4405
4406 if (inta & CSR_INT_BIT_SW_ERR) {
4407 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4408 inta);
4409 iwl3945_irq_handle_error(priv);
4410 handled |= CSR_INT_BIT_SW_ERR;
4411 }
4412
4413
4414 if (inta & CSR_INT_BIT_WAKEUP) {
4415 IWL_DEBUG_ISR("Wakeup interrupt\n");
4416 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4417 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4418 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4419 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4420 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4421 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4422 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
4423
4424 handled |= CSR_INT_BIT_WAKEUP;
4425 }
4426
4427
4428
4429
4430 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4431 iwl3945_rx_handle(priv);
4432 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4433 }
4434
4435 if (inta & CSR_INT_BIT_FH_TX) {
4436 IWL_DEBUG_ISR("Tx interrupt\n");
4437
4438 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4439 if (!iwl3945_grab_nic_access(priv)) {
4440 iwl3945_write_direct32(priv,
4441 FH_TCSR_CREDIT
4442 (ALM_FH_SRVC_CHNL), 0x0);
4443 iwl3945_release_nic_access(priv);
4444 }
4445 handled |= CSR_INT_BIT_FH_TX;
4446 }
4447
4448 if (inta & ~handled)
4449 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4450
4451 if (inta & ~CSR_INI_SET_MASK) {
4452 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4453 inta & ~CSR_INI_SET_MASK);
4454 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4455 }
4456
4457
4458
4459 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4460 iwl3945_enable_interrupts(priv);
4461
4462#ifdef CONFIG_IWL3945_DEBUG
4463 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4464 inta = iwl3945_read32(priv, CSR_INT);
4465 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4466 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4467 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4468 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4469 }
4470#endif
4471 spin_unlock_irqrestore(&priv->lock, flags);
4472}
4473
4474static irqreturn_t iwl3945_isr(int irq, void *data)
4475{
4476 struct iwl3945_priv *priv = data;
4477 u32 inta, inta_mask;
4478 u32 inta_fh;
4479 if (!priv)
4480 return IRQ_NONE;
4481
4482 spin_lock(&priv->lock);
4483
4484
4485
4486
4487
4488 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4489 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
4490
4491
4492 inta = iwl3945_read32(priv, CSR_INT);
4493 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4494
4495
4496
4497
4498 if (!inta && !inta_fh) {
4499 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4500 goto none;
4501 }
4502
4503 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4504
4505 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
4506 goto unplugged;
4507 }
4508
4509 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4510 inta, inta_mask, inta_fh);
4511
4512 inta &= ~CSR_INT_BIT_SCD;
4513
4514
4515 if (likely(inta || inta_fh))
4516 tasklet_schedule(&priv->irq_tasklet);
4517unplugged:
4518 spin_unlock(&priv->lock);
4519
4520 return IRQ_HANDLED;
4521
4522 none:
4523
4524
4525 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4526 iwl3945_enable_interrupts(priv);
4527 spin_unlock(&priv->lock);
4528 return IRQ_NONE;
4529}
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563static const u8 iwl3945_eeprom_band_1[14] = {
4564 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4565};
4566
4567
4568static const u8 iwl3945_eeprom_band_2[] = {
4569 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4570};
4571
4572static const u8 iwl3945_eeprom_band_3[] = {
4573 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4574};
4575
4576static const u8 iwl3945_eeprom_band_4[] = {
4577 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4578};
4579
4580static const u8 iwl3945_eeprom_band_5[] = {
4581 145, 149, 153, 157, 161, 165
4582};
4583
4584static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
4585 int *eeprom_ch_count,
4586 const struct iwl3945_eeprom_channel
4587 **eeprom_ch_info,
4588 const u8 **eeprom_ch_index)
4589{
4590 switch (band) {
4591 case 1:
4592 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
4593 *eeprom_ch_info = priv->eeprom.band_1_channels;
4594 *eeprom_ch_index = iwl3945_eeprom_band_1;
4595 break;
4596 case 2:
4597 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
4598 *eeprom_ch_info = priv->eeprom.band_2_channels;
4599 *eeprom_ch_index = iwl3945_eeprom_band_2;
4600 break;
4601 case 3:
4602 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
4603 *eeprom_ch_info = priv->eeprom.band_3_channels;
4604 *eeprom_ch_index = iwl3945_eeprom_band_3;
4605 break;
4606 case 4:
4607 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
4608 *eeprom_ch_info = priv->eeprom.band_4_channels;
4609 *eeprom_ch_index = iwl3945_eeprom_band_4;
4610 break;
4611 case 5:
4612 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
4613 *eeprom_ch_info = priv->eeprom.band_5_channels;
4614 *eeprom_ch_index = iwl3945_eeprom_band_5;
4615 break;
4616 default:
4617 BUG();
4618 return;
4619 }
4620}
4621
4622
4623
4624
4625
4626
4627const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
4628 enum ieee80211_band band, u16 channel)
4629{
4630 int i;
4631
4632 switch (band) {
4633 case IEEE80211_BAND_5GHZ:
4634 for (i = 14; i < priv->channel_count; i++) {
4635 if (priv->channel_info[i].channel == channel)
4636 return &priv->channel_info[i];
4637 }
4638 break;
4639
4640 case IEEE80211_BAND_2GHZ:
4641 if (channel >= 1 && channel <= 14)
4642 return &priv->channel_info[channel - 1];
4643 break;
4644 case IEEE80211_NUM_BANDS:
4645 WARN_ON(1);
4646 }
4647
4648 return NULL;
4649}
4650
4651#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4652 ? # x " " : "")
4653
4654
4655