1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/types.h>
17#include <linux/netdevice.h>
18#include <linux/ethtool.h>
19#include <linux/mii.h>
20#include <linux/if_ether.h>
21#include <linux/if_vlan.h>
22#include <linux/etherdevice.h>
23#include <linux/pci.h>
24#include <linux/delay.h>
25#include <linux/init.h>
26#include <linux/dma-mapping.h>
27#include <linux/ssb/ssb.h>
28
29#include <asm/uaccess.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32
33
34#include "b44.h"
35
36#define DRV_MODULE_NAME "b44"
37#define PFX DRV_MODULE_NAME ": "
38#define DRV_MODULE_VERSION "2.0"
39
40#define B44_DEF_MSG_ENABLE \
41 (NETIF_MSG_DRV | \
42 NETIF_MSG_PROBE | \
43 NETIF_MSG_LINK | \
44 NETIF_MSG_TIMER | \
45 NETIF_MSG_IFDOWN | \
46 NETIF_MSG_IFUP | \
47 NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR)
49
50
51
52
53#define B44_TX_TIMEOUT (5 * HZ)
54
55
56#define B44_MIN_MTU 60
57#define B44_MAX_MTU 1500
58
59#define B44_RX_RING_SIZE 512
60#define B44_DEF_RX_RING_PENDING 200
61#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
62 B44_RX_RING_SIZE)
63#define B44_TX_RING_SIZE 512
64#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
65#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
66 B44_TX_RING_SIZE)
67
68#define TX_RING_GAP(BP) \
69 (B44_TX_RING_SIZE - (BP)->tx_pending)
70#define TX_BUFFS_AVAIL(BP) \
71 (((BP)->tx_cons <= (BP)->tx_prod) ? \
72 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
73 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
74#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
75
76#define RX_PKT_OFFSET 30
77#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)
78
79
80#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
81
82
83#define B44_PATTERN_BASE 0x400
84#define B44_PATTERN_SIZE 0x80
85#define B44_PMASK_BASE 0x600
86#define B44_PMASK_SIZE 0x10
87#define B44_MAX_PATTERNS 16
88#define B44_ETHIPV6UDP_HLEN 62
89#define B44_ETHIPV4UDP_HLEN 42
90
91static char version[] __devinitdata =
92 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
93
94MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
95MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRV_MODULE_VERSION);
98
99static int b44_debug = -1;
100module_param(b44_debug, int, 0);
101MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
102
103
104#ifdef CONFIG_B44_PCI
105static const struct pci_device_id b44_pci_tbl[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
109 { 0 }
110};
111MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
112
113static struct pci_driver b44_pci_driver = {
114 .name = DRV_MODULE_NAME,
115 .id_table = b44_pci_tbl,
116};
117#endif
118
119static const struct ssb_device_id b44_ssb_tbl[] = {
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
121 SSB_DEVTABLE_END
122};
123MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
124
125static void b44_halt(struct b44 *);
126static void b44_init_rings(struct b44 *);
127
128#define B44_FULL_RESET 1
129#define B44_FULL_RESET_SKIP_PHY 2
130#define B44_PARTIAL_RESET 3
131#define B44_CHIP_RESET_FULL 4
132#define B44_CHIP_RESET_PARTIAL 5
133
134static void b44_init_hw(struct b44 *, int);
135
136static int dma_desc_align_mask;
137static int dma_desc_sync_size;
138static int instance;
139
140static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141#define _B44(x...) # x,
142B44_STAT_REG_DECLARE
143#undef _B44
144};
145
146static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
147 dma_addr_t dma_base,
148 unsigned long offset,
149 enum dma_data_direction dir)
150{
151 ssb_dma_sync_single_range_for_device(sdev, dma_base,
152 offset & dma_desc_align_mask,
153 dma_desc_sync_size, dir);
154}
155
156static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 dma_addr_t dma_base,
158 unsigned long offset,
159 enum dma_data_direction dir)
160{
161 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
162 offset & dma_desc_align_mask,
163 dma_desc_sync_size, dir);
164}
165
166static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
167{
168 return ssb_read32(bp->sdev, reg);
169}
170
171static inline void bw32(const struct b44 *bp,
172 unsigned long reg, unsigned long val)
173{
174 ssb_write32(bp->sdev, reg, val);
175}
176
177static int b44_wait_bit(struct b44 *bp, unsigned long reg,
178 u32 bit, unsigned long timeout, const int clear)
179{
180 unsigned long i;
181
182 for (i = 0; i < timeout; i++) {
183 u32 val = br32(bp, reg);
184
185 if (clear && !(val & bit))
186 break;
187 if (!clear && (val & bit))
188 break;
189 udelay(10);
190 }
191 if (i == timeout) {
192 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
193 "%lx to %s.\n",
194 bp->dev->name,
195 bit, reg,
196 (clear ? "clear" : "set"));
197 return -ENODEV;
198 }
199 return 0;
200}
201
202static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
203{
204 u32 val;
205
206 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
207 (index << CAM_CTRL_INDEX_SHIFT)));
208
209 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
210
211 val = br32(bp, B44_CAM_DATA_LO);
212
213 data[2] = (val >> 24) & 0xFF;
214 data[3] = (val >> 16) & 0xFF;
215 data[4] = (val >> 8) & 0xFF;
216 data[5] = (val >> 0) & 0xFF;
217
218 val = br32(bp, B44_CAM_DATA_HI);
219
220 data[0] = (val >> 8) & 0xFF;
221 data[1] = (val >> 0) & 0xFF;
222}
223
224static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
225{
226 u32 val;
227
228 val = ((u32) data[2]) << 24;
229 val |= ((u32) data[3]) << 16;
230 val |= ((u32) data[4]) << 8;
231 val |= ((u32) data[5]) << 0;
232 bw32(bp, B44_CAM_DATA_LO, val);
233 val = (CAM_DATA_HI_VALID |
234 (((u32) data[0]) << 8) |
235 (((u32) data[1]) << 0));
236 bw32(bp, B44_CAM_DATA_HI, val);
237 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
238 (index << CAM_CTRL_INDEX_SHIFT)));
239 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
240}
241
242static inline void __b44_disable_ints(struct b44 *bp)
243{
244 bw32(bp, B44_IMASK, 0);
245}
246
247static void b44_disable_ints(struct b44 *bp)
248{
249 __b44_disable_ints(bp);
250
251
252 br32(bp, B44_IMASK);
253}
254
255static void b44_enable_ints(struct b44 *bp)
256{
257 bw32(bp, B44_IMASK, bp->imask);
258}
259
260static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
261{
262 int err;
263
264 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
265 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
266 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
267 (phy_addr << MDIO_DATA_PMD_SHIFT) |
268 (reg << MDIO_DATA_RA_SHIFT) |
269 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
270 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
271 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
272
273 return err;
274}
275
276static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
277{
278 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
279 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
280 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
281 (phy_addr << MDIO_DATA_PMD_SHIFT) |
282 (reg << MDIO_DATA_RA_SHIFT) |
283 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
284 (val & MDIO_DATA_DATA)));
285 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
286}
287
288static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
289{
290 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
291 return 0;
292
293 return __b44_readphy(bp, bp->phy_addr, reg, val);
294}
295
296static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
297{
298 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
299 return 0;
300
301 return __b44_writephy(bp, bp->phy_addr, reg, val);
302}
303
304
305static int b44_mii_read(struct net_device *dev, int phy_id, int location)
306{
307 u32 val;
308 struct b44 *bp = netdev_priv(dev);
309 int rc = __b44_readphy(bp, phy_id, location, &val);
310 if (rc)
311 return 0xffffffff;
312 return val;
313}
314
315static void b44_mii_write(struct net_device *dev, int phy_id, int location,
316 int val)
317{
318 struct b44 *bp = netdev_priv(dev);
319 __b44_writephy(bp, phy_id, location, val);
320}
321
322static int b44_phy_reset(struct b44 *bp)
323{
324 u32 val;
325 int err;
326
327 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
328 return 0;
329 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
330 if (err)
331 return err;
332 udelay(100);
333 err = b44_readphy(bp, MII_BMCR, &val);
334 if (!err) {
335 if (val & BMCR_RESET) {
336 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
337 bp->dev->name);
338 err = -ENODEV;
339 }
340 }
341
342 return 0;
343}
344
345static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
346{
347 u32 val;
348
349 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
350 bp->flags |= pause_flags;
351
352 val = br32(bp, B44_RXCONFIG);
353 if (pause_flags & B44_FLAG_RX_PAUSE)
354 val |= RXCONFIG_FLOW;
355 else
356 val &= ~RXCONFIG_FLOW;
357 bw32(bp, B44_RXCONFIG, val);
358
359 val = br32(bp, B44_MAC_FLOW);
360 if (pause_flags & B44_FLAG_TX_PAUSE)
361 val |= (MAC_FLOW_PAUSE_ENAB |
362 (0xc0 & MAC_FLOW_RX_HI_WATER));
363 else
364 val &= ~MAC_FLOW_PAUSE_ENAB;
365 bw32(bp, B44_MAC_FLOW, val);
366}
367
368static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
369{
370 u32 pause_enab = 0;
371
372
373
374
375
376
377 if ((local & ADVERTISE_PAUSE_CAP) &&
378 (local & ADVERTISE_PAUSE_ASYM)){
379 if ((remote & LPA_PAUSE_ASYM) &&
380 !(remote & LPA_PAUSE_CAP))
381 pause_enab |= B44_FLAG_RX_PAUSE;
382 }
383
384 __b44_set_flow_ctrl(bp, pause_enab);
385}
386
387#ifdef SSB_DRIVER_MIPS
388extern char *nvram_get(char *name);
389static void b44_wap54g10_workaround(struct b44 *bp)
390{
391 const char *str;
392 u32 val;
393 int err;
394
395
396
397
398
399
400 str = nvram_get("boardnum");
401 if (!str)
402 return;
403 if (simple_strtoul(str, NULL, 0) == 2) {
404 err = __b44_readphy(bp, 0, MII_BMCR, &val);
405 if (err)
406 goto error;
407 if (!(val & BMCR_ISOLATE))
408 return;
409 val &= ~BMCR_ISOLATE;
410 err = __b44_writephy(bp, 0, MII_BMCR, val);
411 if (err)
412 goto error;
413 }
414 return;
415error:
416 printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
417}
418#else
419static inline void b44_wap54g10_workaround(struct b44 *bp)
420{
421}
422#endif
423
424static int b44_setup_phy(struct b44 *bp)
425{
426 u32 val;
427 int err;
428
429 b44_wap54g10_workaround(bp);
430
431 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
432 return 0;
433 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
434 goto out;
435 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
436 val & MII_ALEDCTRL_ALLMSK)) != 0)
437 goto out;
438 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
439 goto out;
440 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
441 val | MII_TLEDCTRL_ENABLE)) != 0)
442 goto out;
443
444 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
445 u32 adv = ADVERTISE_CSMA;
446
447 if (bp->flags & B44_FLAG_ADV_10HALF)
448 adv |= ADVERTISE_10HALF;
449 if (bp->flags & B44_FLAG_ADV_10FULL)
450 adv |= ADVERTISE_10FULL;
451 if (bp->flags & B44_FLAG_ADV_100HALF)
452 adv |= ADVERTISE_100HALF;
453 if (bp->flags & B44_FLAG_ADV_100FULL)
454 adv |= ADVERTISE_100FULL;
455
456 if (bp->flags & B44_FLAG_PAUSE_AUTO)
457 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
458
459 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
460 goto out;
461 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
462 BMCR_ANRESTART))) != 0)
463 goto out;
464 } else {
465 u32 bmcr;
466
467 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
468 goto out;
469 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
470 if (bp->flags & B44_FLAG_100_BASE_T)
471 bmcr |= BMCR_SPEED100;
472 if (bp->flags & B44_FLAG_FULL_DUPLEX)
473 bmcr |= BMCR_FULLDPLX;
474 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
475 goto out;
476
477
478
479
480
481 b44_set_flow_ctrl(bp, 0, 0);
482 }
483
484out:
485 return err;
486}
487
488static void b44_stats_update(struct b44 *bp)
489{
490 unsigned long reg;
491 u32 *val;
492
493 val = &bp->hw_stats.tx_good_octets;
494 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
495 *val++ += br32(bp, reg);
496 }
497
498
499 reg += 8*4UL;
500
501 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
503 }
504}
505
506static void b44_link_report(struct b44 *bp)
507{
508 if (!netif_carrier_ok(bp->dev)) {
509 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
510 } else {
511 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
512 bp->dev->name,
513 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
514 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
515
516 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
517 "%s for RX.\n",
518 bp->dev->name,
519 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
520 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
521 }
522}
523
524static void b44_check_phy(struct b44 *bp)
525{
526 u32 bmsr, aux;
527
528 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
529 bp->flags |= B44_FLAG_100_BASE_T;
530 bp->flags |= B44_FLAG_FULL_DUPLEX;
531 if (!netif_carrier_ok(bp->dev)) {
532 u32 val = br32(bp, B44_TX_CTRL);
533 val |= TX_CTRL_DUPLEX;
534 bw32(bp, B44_TX_CTRL, val);
535 netif_carrier_on(bp->dev);
536 b44_link_report(bp);
537 }
538 return;
539 }
540
541 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
542 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
543 (bmsr != 0xffff)) {
544 if (aux & MII_AUXCTRL_SPEED)
545 bp->flags |= B44_FLAG_100_BASE_T;
546 else
547 bp->flags &= ~B44_FLAG_100_BASE_T;
548 if (aux & MII_AUXCTRL_DUPLEX)
549 bp->flags |= B44_FLAG_FULL_DUPLEX;
550 else
551 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
552
553 if (!netif_carrier_ok(bp->dev) &&
554 (bmsr & BMSR_LSTATUS)) {
555 u32 val = br32(bp, B44_TX_CTRL);
556 u32 local_adv, remote_adv;
557
558 if (bp->flags & B44_FLAG_FULL_DUPLEX)
559 val |= TX_CTRL_DUPLEX;
560 else
561 val &= ~TX_CTRL_DUPLEX;
562 bw32(bp, B44_TX_CTRL, val);
563
564 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
565 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
566 !b44_readphy(bp, MII_LPA, &remote_adv))
567 b44_set_flow_ctrl(bp, local_adv, remote_adv);
568
569
570 netif_carrier_on(bp->dev);
571 b44_link_report(bp);
572 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
573
574 netif_carrier_off(bp->dev);
575 b44_link_report(bp);
576 }
577
578 if (bmsr & BMSR_RFAULT)
579 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
580 bp->dev->name);
581 if (bmsr & BMSR_JCD)
582 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
583 bp->dev->name);
584 }
585}
586
587static void b44_timer(unsigned long __opaque)
588{
589 struct b44 *bp = (struct b44 *) __opaque;
590
591 spin_lock_irq(&bp->lock);
592
593 b44_check_phy(bp);
594
595 b44_stats_update(bp);
596
597 spin_unlock_irq(&bp->lock);
598
599 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
600}
601
602static void b44_tx(struct b44 *bp)
603{
604 u32 cur, cons;
605
606 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
607 cur /= sizeof(struct dma_desc);
608
609
610 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
611 struct ring_info *rp = &bp->tx_buffers[cons];
612 struct sk_buff *skb = rp->skb;
613
614 BUG_ON(skb == NULL);
615
616 ssb_dma_unmap_single(bp->sdev,
617 rp->mapping,
618 skb->len,
619 DMA_TO_DEVICE);
620 rp->skb = NULL;
621 dev_kfree_skb_irq(skb);
622 }
623
624 bp->tx_cons = cons;
625 if (netif_queue_stopped(bp->dev) &&
626 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
627 netif_wake_queue(bp->dev);
628
629 bw32(bp, B44_GPTIMER, 0);
630}
631
632
633
634
635
636
637static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
638{
639 struct dma_desc *dp;
640 struct ring_info *src_map, *map;
641 struct rx_header *rh;
642 struct sk_buff *skb;
643 dma_addr_t mapping;
644 int dest_idx;
645 u32 ctrl;
646
647 src_map = NULL;
648 if (src_idx >= 0)
649 src_map = &bp->rx_buffers[src_idx];
650 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
651 map = &bp->rx_buffers[dest_idx];
652 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
653 if (skb == NULL)
654 return -ENOMEM;
655
656 mapping = ssb_dma_map_single(bp->sdev, skb->data,
657 RX_PKT_BUF_SZ,
658 DMA_FROM_DEVICE);
659
660
661
662 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
663 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
664
665 if (!ssb_dma_mapping_error(bp->sdev, mapping))
666 ssb_dma_unmap_single(bp->sdev, mapping,
667 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
668 dev_kfree_skb_any(skb);
669 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
670 if (skb == NULL)
671 return -ENOMEM;
672 mapping = ssb_dma_map_single(bp->sdev, skb->data,
673 RX_PKT_BUF_SZ,
674 DMA_FROM_DEVICE);
675 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
676 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
677 if (!ssb_dma_mapping_error(bp->sdev, mapping))
678 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
679 dev_kfree_skb_any(skb);
680 return -ENOMEM;
681 }
682 }
683
684 rh = (struct rx_header *) skb->data;
685 skb_reserve(skb, RX_PKT_OFFSET);
686
687 rh->len = 0;
688 rh->flags = 0;
689
690 map->skb = skb;
691 map->mapping = mapping;
692
693 if (src_map != NULL)
694 src_map->skb = NULL;
695
696 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
697 if (dest_idx == (B44_RX_RING_SIZE - 1))
698 ctrl |= DESC_CTRL_EOT;
699
700 dp = &bp->rx_ring[dest_idx];
701 dp->ctrl = cpu_to_le32(ctrl);
702 dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
703
704 if (bp->flags & B44_FLAG_RX_RING_HACK)
705 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
706 dest_idx * sizeof(dp),
707 DMA_BIDIRECTIONAL);
708
709 return RX_PKT_BUF_SZ;
710}
711
712static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
713{
714 struct dma_desc *src_desc, *dest_desc;
715 struct ring_info *src_map, *dest_map;
716 struct rx_header *rh;
717 int dest_idx;
718 __le32 ctrl;
719
720 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
721 dest_desc = &bp->rx_ring[dest_idx];
722 dest_map = &bp->rx_buffers[dest_idx];
723 src_desc = &bp->rx_ring[src_idx];
724 src_map = &bp->rx_buffers[src_idx];
725
726 dest_map->skb = src_map->skb;
727 rh = (struct rx_header *) src_map->skb->data;
728 rh->len = 0;
729 rh->flags = 0;
730 dest_map->mapping = src_map->mapping;
731
732 if (bp->flags & B44_FLAG_RX_RING_HACK)
733 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
734 src_idx * sizeof(src_desc),
735 DMA_BIDIRECTIONAL);
736
737 ctrl = src_desc->ctrl;
738 if (dest_idx == (B44_RX_RING_SIZE - 1))
739 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
740 else
741 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
742
743 dest_desc->ctrl = ctrl;
744 dest_desc->addr = src_desc->addr;
745
746 src_map->skb = NULL;
747
748 if (bp->flags & B44_FLAG_RX_RING_HACK)
749 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
750 dest_idx * sizeof(dest_desc),
751 DMA_BIDIRECTIONAL);
752
753 ssb_dma_sync_single_for_device(bp->sdev, le32_to_cpu(src_desc->addr),
754 RX_PKT_BUF_SZ,
755 DMA_FROM_DEVICE);
756}
757
758static int b44_rx(struct b44 *bp, int budget)
759{
760 int received;
761 u32 cons, prod;
762
763 received = 0;
764 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
765 prod /= sizeof(struct dma_desc);
766 cons = bp->rx_cons;
767
768 while (cons != prod && budget > 0) {
769 struct ring_info *rp = &bp->rx_buffers[cons];
770 struct sk_buff *skb = rp->skb;
771 dma_addr_t map = rp->mapping;
772 struct rx_header *rh;
773 u16 len;
774
775 ssb_dma_sync_single_for_cpu(bp->sdev, map,
776 RX_PKT_BUF_SZ,
777 DMA_FROM_DEVICE);
778 rh = (struct rx_header *) skb->data;
779 len = le16_to_cpu(rh->len);
780 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
781 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
782 drop_it:
783 b44_recycle_rx(bp, cons, bp->rx_prod);
784 drop_it_no_recycle:
785 bp->stats.rx_dropped++;
786 goto next_pkt;
787 }
788
789 if (len == 0) {
790 int i = 0;
791
792 do {
793 udelay(2);
794 barrier();
795 len = le16_to_cpu(rh->len);
796 } while (len == 0 && i++ < 5);
797 if (len == 0)
798 goto drop_it;
799 }
800
801
802 len -= 4;
803
804 if (len > RX_COPY_THRESHOLD) {
805 int skb_size;
806 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
807 if (skb_size < 0)
808 goto drop_it;
809 ssb_dma_unmap_single(bp->sdev, map,
810 skb_size, DMA_FROM_DEVICE);
811
812 skb_put(skb, len + RX_PKT_OFFSET);
813 skb_pull(skb, RX_PKT_OFFSET);
814 } else {
815 struct sk_buff *copy_skb;
816
817 b44_recycle_rx(bp, cons, bp->rx_prod);
818 copy_skb = dev_alloc_skb(len + 2);
819 if (copy_skb == NULL)
820 goto drop_it_no_recycle;
821
822 skb_reserve(copy_skb, 2);
823 skb_put(copy_skb, len);
824
825 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
826 copy_skb->data, len);
827 skb = copy_skb;
828 }
829 skb->ip_summed = CHECKSUM_NONE;
830 skb->protocol = eth_type_trans(skb, bp->dev);
831 netif_receive_skb(skb);
832 bp->dev->last_rx = jiffies;
833 received++;
834 budget--;
835 next_pkt:
836 bp->rx_prod = (bp->rx_prod + 1) &
837 (B44_RX_RING_SIZE - 1);
838 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
839 }
840
841 bp->rx_cons = cons;
842 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
843
844 return received;
845}
846
847static int b44_poll(struct napi_struct *napi, int budget)
848{
849 struct b44 *bp = container_of(napi, struct b44, napi);
850 struct net_device *netdev = bp->dev;
851 int work_done;
852
853 spin_lock_irq(&bp->lock);
854
855 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
856
857 b44_tx(bp);
858
859 }
860 spin_unlock_irq(&bp->lock);
861
862 work_done = 0;
863 if (bp->istat & ISTAT_RX)
864 work_done += b44_rx(bp, budget);
865
866 if (bp->istat & ISTAT_ERRORS) {
867 unsigned long flags;
868
869 spin_lock_irqsave(&bp->lock, flags);
870 b44_halt(bp);
871 b44_init_rings(bp);
872 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
873 netif_wake_queue(bp->dev);
874 spin_unlock_irqrestore(&bp->lock, flags);
875 work_done = 0;
876 }
877
878 if (work_done < budget) {
879 netif_rx_complete(netdev, napi);
880 b44_enable_ints(bp);
881 }
882
883 return work_done;
884}
885
886static irqreturn_t b44_interrupt(int irq, void *dev_id)
887{
888 struct net_device *dev = dev_id;
889 struct b44 *bp = netdev_priv(dev);
890 u32 istat, imask;
891 int handled = 0;
892
893 spin_lock(&bp->lock);
894
895 istat = br32(bp, B44_ISTAT);
896 imask = br32(bp, B44_IMASK);
897
898
899
900
901
902 istat &= imask;
903 if (istat) {
904 handled = 1;
905
906 if (unlikely(!netif_running(dev))) {
907 printk(KERN_INFO "%s: late interrupt.\n", dev->name);
908 goto irq_ack;
909 }
910
911 if (netif_rx_schedule_prep(dev, &bp->napi)) {
912
913
914
915 bp->istat = istat;
916 __b44_disable_ints(bp);
917 __netif_rx_schedule(dev, &bp->napi);
918 } else {
919 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
920 dev->name);
921 }
922
923irq_ack:
924 bw32(bp, B44_ISTAT, istat);
925 br32(bp, B44_ISTAT);
926 }
927 spin_unlock(&bp->lock);
928 return IRQ_RETVAL(handled);
929}
930
931static void b44_tx_timeout(struct net_device *dev)
932{
933 struct b44 *bp = netdev_priv(dev);
934
935 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
936 dev->name);
937
938 spin_lock_irq(&bp->lock);
939
940 b44_halt(bp);
941 b44_init_rings(bp);
942 b44_init_hw(bp, B44_FULL_RESET);
943
944 spin_unlock_irq(&bp->lock);
945
946 b44_enable_ints(bp);
947
948 netif_wake_queue(dev);
949}
950
951static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
952{
953 struct b44 *bp = netdev_priv(dev);
954 int rc = NETDEV_TX_OK;
955 dma_addr_t mapping;
956 u32 len, entry, ctrl;
957
958 len = skb->len;
959 spin_lock_irq(&bp->lock);
960
961
962 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
963 netif_stop_queue(dev);
964 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
965 dev->name);
966 goto err_out;
967 }
968
969 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
970 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
971 struct sk_buff *bounce_skb;
972
973
974 if (!ssb_dma_mapping_error(bp->sdev, mapping))
975 ssb_dma_unmap_single(bp->sdev, mapping, len,
976 DMA_TO_DEVICE);
977
978 bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA);
979 if (!bounce_skb)
980 goto err_out;
981
982 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
983 len, DMA_TO_DEVICE);
984 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
985 if (!ssb_dma_mapping_error(bp->sdev, mapping))
986 ssb_dma_unmap_single(bp->sdev, mapping,
987 len, DMA_TO_DEVICE);
988 dev_kfree_skb_any(bounce_skb);
989 goto err_out;
990 }
991
992 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
993 dev_kfree_skb_any(skb);
994 skb = bounce_skb;
995 }
996
997 entry = bp->tx_prod;
998 bp->tx_buffers[entry].skb = skb;
999 bp->tx_buffers[entry].mapping = mapping;
1000
1001 ctrl = (len & DESC_CTRL_LEN);
1002 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1003 if (entry == (B44_TX_RING_SIZE - 1))
1004 ctrl |= DESC_CTRL_EOT;
1005
1006 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1007 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1008
1009 if (bp->flags & B44_FLAG_TX_RING_HACK)
1010 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1011 entry * sizeof(bp->tx_ring[0]),
1012 DMA_TO_DEVICE);
1013
1014 entry = NEXT_TX(entry);
1015
1016 bp->tx_prod = entry;
1017
1018 wmb();
1019
1020 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1021 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1022 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1023 if (bp->flags & B44_FLAG_REORDER_BUG)
1024 br32(bp, B44_DMATX_PTR);
1025
1026 if (TX_BUFFS_AVAIL(bp) < 1)
1027 netif_stop_queue(dev);
1028
1029 dev->trans_start = jiffies;
1030
1031out_unlock:
1032 spin_unlock_irq(&bp->lock);
1033
1034 return rc;
1035
1036err_out:
1037 rc = NETDEV_TX_BUSY;
1038 goto out_unlock;
1039}
1040
1041static int b44_change_mtu(struct net_device *dev, int new_mtu)
1042{
1043 struct b44 *bp = netdev_priv(dev);
1044
1045 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1046 return -EINVAL;
1047
1048 if (!netif_running(dev)) {
1049
1050
1051
1052 dev->mtu = new_mtu;
1053 return 0;
1054 }
1055
1056 spin_lock_irq(&bp->lock);
1057 b44_halt(bp);
1058 dev->mtu = new_mtu;
1059 b44_init_rings(bp);
1060 b44_init_hw(bp, B44_FULL_RESET);
1061 spin_unlock_irq(&bp->lock);
1062
1063 b44_enable_ints(bp);
1064
1065 return 0;
1066}
1067
1068
1069
1070
1071
1072
1073
1074
1075static void b44_free_rings(struct b44 *bp)
1076{
1077 struct ring_info *rp;
1078 int i;
1079
1080 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1081 rp = &bp->rx_buffers[i];
1082
1083 if (rp->skb == NULL)
1084 continue;
1085 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1086 DMA_FROM_DEVICE);
1087 dev_kfree_skb_any(rp->skb);
1088 rp->skb = NULL;
1089 }
1090
1091
1092 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1093 rp = &bp->tx_buffers[i];
1094
1095 if (rp->skb == NULL)
1096 continue;
1097 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1098 DMA_TO_DEVICE);
1099 dev_kfree_skb_any(rp->skb);
1100 rp->skb = NULL;
1101 }
1102}
1103
1104
1105
1106
1107
1108
1109
1110static void b44_init_rings(struct b44 *bp)
1111{
1112 int i;
1113
1114 b44_free_rings(bp);
1115
1116 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1117 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1118
1119 if (bp->flags & B44_FLAG_RX_RING_HACK)
1120 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1121 DMA_TABLE_BYTES,
1122 DMA_BIDIRECTIONAL);
1123
1124 if (bp->flags & B44_FLAG_TX_RING_HACK)
1125 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1126 DMA_TABLE_BYTES,
1127 DMA_TO_DEVICE);
1128
1129 for (i = 0; i < bp->rx_pending; i++) {
1130 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1131 break;
1132 }
1133}
1134
1135
1136
1137
1138
1139static void b44_free_consistent(struct b44 *bp)
1140{
1141 kfree(bp->rx_buffers);
1142 bp->rx_buffers = NULL;
1143 kfree(bp->tx_buffers);
1144 bp->tx_buffers = NULL;
1145 if (bp->rx_ring) {
1146 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1147 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1148 DMA_TABLE_BYTES,
1149 DMA_BIDIRECTIONAL);
1150 kfree(bp->rx_ring);
1151 } else
1152 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1153 bp->rx_ring, bp->rx_ring_dma,
1154 GFP_KERNEL);
1155 bp->rx_ring = NULL;
1156 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1157 }
1158 if (bp->tx_ring) {
1159 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1160 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1161 DMA_TABLE_BYTES,
1162 DMA_TO_DEVICE);
1163 kfree(bp->tx_ring);
1164 } else
1165 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1166 bp->tx_ring, bp->tx_ring_dma,
1167 GFP_KERNEL);
1168 bp->tx_ring = NULL;
1169 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1170 }
1171}
1172
1173
1174
1175
1176
1177static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1178{
1179 int size;
1180
1181 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1182 bp->rx_buffers = kzalloc(size, gfp);
1183 if (!bp->rx_buffers)
1184 goto out_err;
1185
1186 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1187 bp->tx_buffers = kzalloc(size, gfp);
1188 if (!bp->tx_buffers)
1189 goto out_err;
1190
1191 size = DMA_TABLE_BYTES;
1192 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
1193 if (!bp->rx_ring) {
1194
1195
1196
1197 struct dma_desc *rx_ring;
1198 dma_addr_t rx_ring_dma;
1199
1200 rx_ring = kzalloc(size, gfp);
1201 if (!rx_ring)
1202 goto out_err;
1203
1204 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1205 DMA_TABLE_BYTES,
1206 DMA_BIDIRECTIONAL);
1207
1208 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
1209 rx_ring_dma + size > DMA_30BIT_MASK) {
1210 kfree(rx_ring);
1211 goto out_err;
1212 }
1213
1214 bp->rx_ring = rx_ring;
1215 bp->rx_ring_dma = rx_ring_dma;
1216 bp->flags |= B44_FLAG_RX_RING_HACK;
1217 }
1218
1219 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
1220 if (!bp->tx_ring) {
1221
1222
1223
1224 struct dma_desc *tx_ring;
1225 dma_addr_t tx_ring_dma;
1226
1227 tx_ring = kzalloc(size, gfp);
1228 if (!tx_ring)
1229 goto out_err;
1230
1231 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
1232 DMA_TABLE_BYTES,
1233 DMA_TO_DEVICE);
1234
1235 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
1236 tx_ring_dma + size > DMA_30BIT_MASK) {
1237 kfree(tx_ring);
1238 goto out_err;
1239 }
1240
1241 bp->tx_ring = tx_ring;
1242 bp->tx_ring_dma = tx_ring_dma;
1243 bp->flags |= B44_FLAG_TX_RING_HACK;
1244 }
1245
1246 return 0;
1247
1248out_err:
1249 b44_free_consistent(bp);
1250 return -ENOMEM;
1251}
1252
1253
1254static void b44_clear_stats(struct b44 *bp)
1255{
1256 unsigned long reg;
1257
1258 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1259 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1260 br32(bp, reg);
1261 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1262 br32(bp, reg);
1263}
1264
1265
1266static void b44_chip_reset(struct b44 *bp, int reset_kind)
1267{
1268 struct ssb_device *sdev = bp->sdev;
1269
1270 if (ssb_device_is_enabled(bp->sdev)) {
1271 bw32(bp, B44_RCV_LAZY, 0);
1272 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1273 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1274 bw32(bp, B44_DMATX_CTRL, 0);
1275 bp->tx_prod = bp->tx_cons = 0;
1276 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1277 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1278 100, 0);
1279 }
1280 bw32(bp, B44_DMARX_CTRL, 0);
1281 bp->rx_prod = bp->rx_cons = 0;
1282 } else
1283 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1284
1285 ssb_device_enable(bp->sdev, 0);
1286 b44_clear_stats(bp);
1287
1288
1289
1290
1291
1292 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1293 return;
1294
1295 switch (sdev->bus->bustype) {
1296 case SSB_BUSTYPE_SSB:
1297 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1298 (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
1299 & MDIO_CTRL_MAXF_MASK)));
1300 break;
1301 case SSB_BUSTYPE_PCI:
1302 case SSB_BUSTYPE_PCMCIA:
1303 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1304 (0x0d & MDIO_CTRL_MAXF_MASK)));
1305 break;
1306 }
1307
1308 br32(bp, B44_MDIO_CTRL);
1309
1310 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1311 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1312 br32(bp, B44_ENET_CTRL);
1313 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1314 } else {
1315 u32 val = br32(bp, B44_DEVCTRL);
1316
1317 if (val & DEVCTRL_EPR) {
1318 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1319 br32(bp, B44_DEVCTRL);
1320 udelay(100);
1321 }
1322 bp->flags |= B44_FLAG_INTERNAL_PHY;
1323 }
1324}
1325
1326
1327static void b44_halt(struct b44 *bp)
1328{
1329 b44_disable_ints(bp);
1330
1331 b44_phy_reset(bp);
1332
1333 printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1334 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1335
1336
1337 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1338}
1339
1340
1341static void __b44_set_mac_addr(struct b44 *bp)
1342{
1343 bw32(bp, B44_CAM_CTRL, 0);
1344 if (!(bp->dev->flags & IFF_PROMISC)) {
1345 u32 val;
1346
1347 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1348 val = br32(bp, B44_CAM_CTRL);
1349 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1350 }
1351}
1352
1353static int b44_set_mac_addr(struct net_device *dev, void *p)
1354{
1355 struct b44 *bp = netdev_priv(dev);
1356 struct sockaddr *addr = p;
1357 u32 val;
1358
1359 if (netif_running(dev))
1360 return -EBUSY;
1361
1362 if (!is_valid_ether_addr(addr->sa_data))
1363 return -EINVAL;
1364
1365 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1366
1367 spin_lock_irq(&bp->lock);
1368
1369 val = br32(bp, B44_RXCONFIG);
1370 if (!(val & RXCONFIG_CAM_ABSENT))
1371 __b44_set_mac_addr(bp);
1372
1373 spin_unlock_irq(&bp->lock);
1374
1375 return 0;
1376}
1377
1378
1379
1380
1381static void __b44_set_rx_mode(struct net_device *);
1382static void b44_init_hw(struct b44 *bp, int reset_kind)
1383{
1384 u32 val;
1385
1386 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1387 if (reset_kind == B44_FULL_RESET) {
1388 b44_phy_reset(bp);
1389 b44_setup_phy(bp);
1390 }
1391
1392
1393 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1394 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1395
1396
1397 __b44_set_rx_mode(bp->dev);
1398
1399
1400 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1401 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1402
1403 bw32(bp, B44_TX_WMARK, 56);
1404 if (reset_kind == B44_PARTIAL_RESET) {
1405 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1406 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1407 } else {
1408 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1409 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1410 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1411 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1412 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1413
1414 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1415 bp->rx_prod = bp->rx_pending;
1416
1417 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1418 }
1419
1420 val = br32(bp, B44_ENET_CTRL);
1421 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1422}
1423
1424static int b44_open(struct net_device *dev)
1425{
1426 struct b44 *bp = netdev_priv(dev);
1427 int err;
1428
1429 err = b44_alloc_consistent(bp, GFP_KERNEL);
1430 if (err)
1431 goto out;
1432
1433 napi_enable(&bp->napi);
1434
1435 b44_init_rings(bp);
1436 b44_init_hw(bp, B44_FULL_RESET);
1437
1438 b44_check_phy(bp);
1439
1440 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1441 if (unlikely(err < 0)) {
1442 napi_disable(&bp->napi);
1443 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1444 b44_free_rings(bp);
1445 b44_free_consistent(bp);
1446 goto out;
1447 }
1448
1449 init_timer(&bp->timer);
1450 bp->timer.expires = jiffies + HZ;
1451 bp->timer.data = (unsigned long) bp;
1452 bp->timer.function = b44_timer;
1453 add_timer(&bp->timer);
1454
1455 b44_enable_ints(bp);
1456 netif_start_queue(dev);
1457out:
1458 return err;
1459}
1460
1461#ifdef CONFIG_NET_POLL_CONTROLLER
1462
1463
1464
1465
1466static void b44_poll_controller(struct net_device *dev)
1467{
1468 disable_irq(dev->irq);
1469 b44_interrupt(dev->irq, dev);
1470 enable_irq(dev->irq);
1471}
1472#endif
1473
1474static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1475{
1476 u32 i;
1477 u32 *pattern = (u32 *) pp;
1478
1479 for (i = 0; i < bytes; i += sizeof(u32)) {
1480 bw32(bp, B44_FILT_ADDR, table_offset + i);
1481 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1482 }
1483}
1484
1485static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1486{
1487 int magicsync = 6;
1488 int k, j, len = offset;
1489 int ethaddr_bytes = ETH_ALEN;
1490
1491 memset(ppattern + offset, 0xff, magicsync);
1492 for (j = 0; j < magicsync; j++)
1493 set_bit(len++, (unsigned long *) pmask);
1494
1495 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1496 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1497 ethaddr_bytes = ETH_ALEN;
1498 else
1499 ethaddr_bytes = B44_PATTERN_SIZE - len;
1500 if (ethaddr_bytes <=0)
1501 break;
1502 for (k = 0; k< ethaddr_bytes; k++) {
1503 ppattern[offset + magicsync +
1504 (j * ETH_ALEN) + k] = macaddr[k];
1505 len++;
1506 set_bit(len, (unsigned long *) pmask);
1507 }
1508 }
1509 return len - 1;
1510}
1511
1512
1513
1514
1515static void b44_setup_pseudo_magicp(struct b44 *bp)
1516{
1517
1518 u32 val;
1519 int plen0, plen1, plen2;
1520 u8 *pwol_pattern;
1521 u8 pwol_mask[B44_PMASK_SIZE];
1522
1523 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1524 if (!pwol_pattern) {
1525 printk(KERN_ERR PFX "Memory not available for WOL\n");
1526 return;
1527 }
1528
1529
1530 memset(pwol_mask, 0, B44_PMASK_SIZE);
1531 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1532 B44_ETHIPV4UDP_HLEN);
1533
1534 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1535 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1536
1537
1538 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1539 memset(pwol_mask, 0, B44_PMASK_SIZE);
1540 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1541 ETH_HLEN);
1542
1543 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1544 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1545 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1546 B44_PMASK_BASE + B44_PMASK_SIZE);
1547
1548
1549 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1550 memset(pwol_mask, 0, B44_PMASK_SIZE);
1551 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1552 B44_ETHIPV6UDP_HLEN);
1553
1554 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1555 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1556 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1557 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1558
1559 kfree(pwol_pattern);
1560
1561
1562 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1563 bw32(bp, B44_WKUP_LEN, val);
1564
1565
1566 val = br32(bp, B44_DEVCTRL);
1567 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1568
1569}
1570
1571#ifdef CONFIG_B44_PCI
1572static void b44_setup_wol_pci(struct b44 *bp)
1573{
1574 u16 val;
1575
1576 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1577 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1578 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1579 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1580 }
1581}
1582#else
1583static inline void b44_setup_wol_pci(struct b44 *bp) { }
1584#endif
1585
1586static void b44_setup_wol(struct b44 *bp)
1587{
1588 u32 val;
1589
1590 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1591
1592 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1593
1594 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1595
1596 val = bp->dev->dev_addr[2] << 24 |
1597 bp->dev->dev_addr[3] << 16 |
1598 bp->dev->dev_addr[4] << 8 |
1599 bp->dev->dev_addr[5];
1600 bw32(bp, B44_ADDR_LO, val);
1601
1602 val = bp->dev->dev_addr[0] << 8 |
1603 bp->dev->dev_addr[1];
1604 bw32(bp, B44_ADDR_HI, val);
1605
1606 val = br32(bp, B44_DEVCTRL);
1607 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1608
1609 } else {
1610 b44_setup_pseudo_magicp(bp);
1611 }
1612 b44_setup_wol_pci(bp);
1613}
1614
1615static int b44_close(struct net_device *dev)
1616{
1617 struct b44 *bp = netdev_priv(dev);
1618
1619 netif_stop_queue(dev);
1620
1621 napi_disable(&bp->napi);
1622
1623 del_timer_sync(&bp->timer);
1624
1625 spin_lock_irq(&bp->lock);
1626
1627 b44_halt(bp);
1628 b44_free_rings(bp);
1629 netif_carrier_off(dev);
1630
1631 spin_unlock_irq(&bp->lock);
1632
1633 free_irq(dev->irq, dev);
1634
1635 if (bp->flags & B44_FLAG_WOL_ENABLE) {
1636 b44_init_hw(bp, B44_PARTIAL_RESET);
1637 b44_setup_wol(bp);
1638 }
1639
1640 b44_free_consistent(bp);
1641
1642 return 0;
1643}
1644
1645static struct net_device_stats *b44_get_stats(struct net_device *dev)
1646{
1647 struct b44 *bp = netdev_priv(dev);
1648 struct net_device_stats *nstat = &bp->stats;
1649 struct b44_hw_stats *hwstat = &bp->hw_stats;
1650
1651
1652 nstat->rx_packets = hwstat->rx_pkts;
1653 nstat->tx_packets = hwstat->tx_pkts;
1654 nstat->rx_bytes = hwstat->rx_octets;
1655 nstat->tx_bytes = hwstat->tx_octets;
1656 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1657 hwstat->tx_oversize_pkts +
1658 hwstat->tx_underruns +
1659 hwstat->tx_excessive_cols +
1660 hwstat->tx_late_cols);
1661 nstat->multicast = hwstat->tx_multicast_pkts;
1662 nstat->collisions = hwstat->tx_total_cols;
1663
1664 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1665 hwstat->rx_undersize);
1666 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1667 nstat->rx_frame_errors = hwstat->rx_align_errs;
1668 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1669 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1670 hwstat->rx_oversize_pkts +
1671 hwstat->rx_missed_pkts +
1672 hwstat->rx_crc_align_errs +
1673 hwstat->rx_undersize +
1674 hwstat->rx_crc_errs +
1675 hwstat->rx_align_errs +
1676 hwstat->rx_symbol_errs);
1677
1678 nstat->tx_aborted_errors = hwstat->tx_underruns;
1679#if 0
1680
1681 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1682#endif
1683
1684 return nstat;
1685}
1686
1687static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1688{
1689 struct dev_mc_list *mclist;
1690 int i, num_ents;
1691
1692 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1693 mclist = dev->mc_list;
1694 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1695 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1696 }
1697 return i+1;
1698}
1699
1700static void __b44_set_rx_mode(struct net_device *dev)
1701{
1702 struct b44 *bp = netdev_priv(dev);
1703 u32 val;
1704
1705 val = br32(bp, B44_RXCONFIG);
1706 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1707 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1708 val |= RXCONFIG_PROMISC;
1709 bw32(bp, B44_RXCONFIG, val);
1710 } else {
1711 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1712 int i = 1;
1713
1714 __b44_set_mac_addr(bp);
1715
1716 if ((dev->flags & IFF_ALLMULTI) ||
1717 (dev->mc_count > B44_MCAST_TABLE_SIZE))
1718 val |= RXCONFIG_ALLMULTI;
1719 else
1720 i = __b44_load_mcast(bp, dev);
1721
1722 for (; i < 64; i++)
1723 __b44_cam_write(bp, zero, i);
1724
1725 bw32(bp, B44_RXCONFIG, val);
1726 val = br32(bp, B44_CAM_CTRL);
1727 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1728 }
1729}
1730
1731static void b44_set_rx_mode(struct net_device *dev)
1732{
1733 struct b44 *bp = netdev_priv(dev);
1734
1735 spin_lock_irq(&bp->lock);
1736 __b44_set_rx_mode(dev);
1737 spin_unlock_irq(&bp->lock);
1738}
1739
1740static u32 b44_get_msglevel(struct net_device *dev)
1741{
1742 struct b44 *bp = netdev_priv(dev);
1743 return bp->msg_enable;
1744}
1745
1746static void b44_set_msglevel(struct net_device *dev, u32 value)
1747{
1748 struct b44 *bp = netdev_priv(dev);
1749 bp->msg_enable = value;
1750}
1751
1752static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1753{
1754 struct b44 *bp = netdev_priv(dev);
1755 struct ssb_bus *bus = bp->sdev->bus;
1756
1757 strncpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1758 strncpy(info->version, DRV_MODULE_VERSION, sizeof(info->driver));
1759 switch (bus->bustype) {
1760 case SSB_BUSTYPE_PCI:
1761 strncpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1762 break;
1763 case SSB_BUSTYPE_PCMCIA:
1764 case SSB_BUSTYPE_SSB:
1765 strncpy(info->bus_info, "SSB", sizeof(info->bus_info));
1766 break;
1767 }
1768}
1769
1770static int b44_nway_reset(struct net_device *dev)
1771{
1772 struct b44 *bp = netdev_priv(dev);
1773 u32 bmcr;
1774 int r;
1775
1776 spin_lock_irq(&bp->lock);
1777 b44_readphy(bp, MII_BMCR, &bmcr);
1778 b44_readphy(bp, MII_BMCR, &bmcr);
1779 r = -EINVAL;
1780 if (bmcr & BMCR_ANENABLE) {
1781 b44_writephy(bp, MII_BMCR,
1782 bmcr | BMCR_ANRESTART);
1783 r = 0;
1784 }
1785 spin_unlock_irq(&bp->lock);
1786
1787 return r;
1788}
1789
1790static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1791{
1792 struct b44 *bp = netdev_priv(dev);
1793
1794 cmd->supported = (SUPPORTED_Autoneg);
1795 cmd->supported |= (SUPPORTED_100baseT_Half |
1796 SUPPORTED_100baseT_Full |
1797 SUPPORTED_10baseT_Half |
1798 SUPPORTED_10baseT_Full |
1799 SUPPORTED_MII);
1800
1801 cmd->advertising = 0;
1802 if (bp->flags & B44_FLAG_ADV_10HALF)
1803 cmd->advertising |= ADVERTISED_10baseT_Half;
1804 if (bp->flags & B44_FLAG_ADV_10FULL)
1805 cmd->advertising |= ADVERTISED_10baseT_Full;
1806 if (bp->flags & B44_FLAG_ADV_100HALF)
1807 cmd->advertising |= ADVERTISED_100baseT_Half;
1808 if (bp->flags & B44_FLAG_ADV_100FULL)
1809 cmd->advertising |= ADVERTISED_100baseT_Full;
1810 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1811 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1812 SPEED_100 : SPEED_10;
1813 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1814 DUPLEX_FULL : DUPLEX_HALF;
1815 cmd->port = 0;
1816 cmd->phy_address = bp->phy_addr;
1817 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1818 XCVR_INTERNAL : XCVR_EXTERNAL;
1819 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1820 AUTONEG_DISABLE : AUTONEG_ENABLE;
1821 if (cmd->autoneg == AUTONEG_ENABLE)
1822 cmd->advertising |= ADVERTISED_Autoneg;
1823 if (!netif_running(dev)){
1824 cmd->speed = 0;
1825 cmd->duplex = 0xff;
1826 }
1827 cmd->maxtxpkt = 0;
1828 cmd->maxrxpkt = 0;
1829 return 0;
1830}
1831
1832static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1833{
1834 struct b44 *bp = netdev_priv(dev);
1835
1836
1837 if (cmd->autoneg == AUTONEG_ENABLE) {
1838 if (cmd->advertising &
1839 (ADVERTISED_1000baseT_Half |
1840 ADVERTISED_1000baseT_Full))
1841 return -EINVAL;
1842 } else if ((cmd->speed != SPEED_100 &&
1843 cmd->speed != SPEED_10) ||
1844 (cmd->duplex != DUPLEX_HALF &&
1845 cmd->duplex != DUPLEX_FULL)) {
1846 return -EINVAL;
1847 }
1848
1849 spin_lock_irq(&bp->lock);
1850
1851 if (cmd->autoneg == AUTONEG_ENABLE) {
1852 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1853 B44_FLAG_100_BASE_T |
1854 B44_FLAG_FULL_DUPLEX |
1855 B44_FLAG_ADV_10HALF |
1856 B44_FLAG_ADV_10FULL |
1857 B44_FLAG_ADV_100HALF |
1858 B44_FLAG_ADV_100FULL);
1859 if (cmd->advertising == 0) {
1860 bp->flags |= (B44_FLAG_ADV_10HALF |
1861 B44_FLAG_ADV_10FULL |
1862 B44_FLAG_ADV_100HALF |
1863 B44_FLAG_ADV_100FULL);
1864 } else {
1865 if (cmd->advertising & ADVERTISED_10baseT_Half)
1866 bp->flags |= B44_FLAG_ADV_10HALF;
1867 if (cmd->advertising & ADVERTISED_10baseT_Full)
1868 bp->flags |= B44_FLAG_ADV_10FULL;
1869 if (cmd->advertising & ADVERTISED_100baseT_Half)
1870 bp->flags |= B44_FLAG_ADV_100HALF;
1871 if (cmd->advertising & ADVERTISED_100baseT_Full)
1872 bp->flags |= B44_FLAG_ADV_100FULL;
1873 }
1874 } else {
1875 bp->flags |= B44_FLAG_FORCE_LINK;
1876 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1877 if (cmd->speed == SPEED_100)
1878 bp->flags |= B44_FLAG_100_BASE_T;
1879 if (cmd->duplex == DUPLEX_FULL)
1880 bp->flags |= B44_FLAG_FULL_DUPLEX;
1881 }
1882
1883 if (netif_running(dev))
1884 b44_setup_phy(bp);
1885
1886 spin_unlock_irq(&bp->lock);
1887
1888 return 0;
1889}
1890
1891static void b44_get_ringparam(struct net_device *dev,
1892 struct ethtool_ringparam *ering)
1893{
1894 struct b44 *bp = netdev_priv(dev);
1895
1896 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1897 ering->rx_pending = bp->rx_pending;
1898
1899
1900}
1901
1902static int b44_set_ringparam(struct net_device *dev,
1903 struct ethtool_ringparam *ering)
1904{
1905 struct b44 *bp = netdev_priv(dev);
1906
1907 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1908 (ering->rx_mini_pending != 0) ||
1909 (ering->rx_jumbo_pending != 0) ||
1910 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1911 return -EINVAL;
1912
1913 spin_lock_irq(&bp->lock);
1914
1915 bp->rx_pending = ering->rx_pending;
1916 bp->tx_pending = ering->tx_pending;
1917
1918 b44_halt(bp);
1919 b44_init_rings(bp);
1920 b44_init_hw(bp, B44_FULL_RESET);
1921 netif_wake_queue(bp->dev);
1922 spin_unlock_irq(&bp->lock);
1923
1924 b44_enable_ints(bp);
1925
1926 return 0;
1927}
1928
1929static void b44_get_pauseparam(struct net_device *dev,
1930 struct ethtool_pauseparam *epause)
1931{
1932 struct b44 *bp = netdev_priv(dev);
1933
1934 epause->autoneg =
1935 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1936 epause->rx_pause =
1937 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1938 epause->tx_pause =
1939 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1940}
1941
1942static int b44_set_pauseparam(struct net_device *dev,
1943 struct ethtool_pauseparam *epause)
1944{
1945 struct b44 *bp = netdev_priv(dev);
1946
1947 spin_lock_irq(&bp->lock);
1948 if (epause->autoneg)
1949 bp->flags |= B44_FLAG_PAUSE_AUTO;
1950 else
1951 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1952 if (epause->rx_pause)
1953 bp->flags |= B44_FLAG_RX_PAUSE;
1954 else
1955 bp->flags &= ~B44_FLAG_RX_PAUSE;
1956 if (epause->tx_pause)
1957 bp->flags |= B44_FLAG_TX_PAUSE;
1958 else
1959 bp->flags &= ~B44_FLAG_TX_PAUSE;
1960 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1961 b44_halt(bp);
1962 b44_init_rings(bp);
1963 b44_init_hw(bp, B44_FULL_RESET);
1964 } else {
1965 __b44_set_flow_ctrl(bp, bp->flags);
1966 }
1967 spin_unlock_irq(&bp->lock);
1968
1969 b44_enable_ints(bp);
1970
1971 return 0;
1972}
1973
1974static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1975{
1976 switch(stringset) {
1977 case ETH_SS_STATS:
1978 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1979 break;
1980 }
1981}
1982
1983static int b44_get_sset_count(struct net_device *dev, int sset)
1984{
1985 switch (sset) {
1986 case ETH_SS_STATS:
1987 return ARRAY_SIZE(b44_gstrings);
1988 default:
1989 return -EOPNOTSUPP;
1990 }
1991}
1992
1993static void b44_get_ethtool_stats(struct net_device *dev,
1994 struct ethtool_stats *stats, u64 *data)
1995{
1996 struct b44 *bp = netdev_priv(dev);
1997 u32 *val = &bp->hw_stats.tx_good_octets;
1998 u32 i;
1999
2000 spin_lock_irq(&bp->lock);
2001
2002 b44_stats_update(bp);
2003
2004 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2005 *data++ = *val++;
2006
2007 spin_unlock_irq(&bp->lock);
2008}
2009
2010static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2011{
2012 struct b44 *bp = netdev_priv(dev);
2013
2014 wol->supported = WAKE_MAGIC;
2015 if (bp->flags & B44_FLAG_WOL_ENABLE)
2016 wol->wolopts = WAKE_MAGIC;
2017 else
2018 wol->wolopts = 0;
2019 memset(&wol->sopass, 0, sizeof(wol->sopass));
2020}
2021
2022static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2023{
2024 struct b44 *bp = netdev_priv(dev);
2025
2026 spin_lock_irq(&bp->lock);
2027 if (wol->wolopts & WAKE_MAGIC)
2028 bp->flags |= B44_FLAG_WOL_ENABLE;
2029 else
2030 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2031 spin_unlock_irq(&bp->lock);
2032
2033 return 0;
2034}
2035
2036static const struct ethtool_ops b44_ethtool_ops = {
2037 .get_drvinfo = b44_get_drvinfo,
2038 .get_settings = b44_get_settings,
2039 .set_settings = b44_set_settings,
2040 .nway_reset = b44_nway_reset,
2041 .get_link = ethtool_op_get_link,
2042 .get_wol = b44_get_wol,
2043 .set_wol = b44_set_wol,
2044 .get_ringparam = b44_get_ringparam,
2045 .set_ringparam = b44_set_ringparam,
2046 .get_pauseparam = b44_get_pauseparam,
2047 .set_pauseparam = b44_set_pauseparam,
2048 .get_msglevel = b44_get_msglevel,
2049 .set_msglevel = b44_set_msglevel,
2050 .get_strings = b44_get_strings,
2051 .get_sset_count = b44_get_sset_count,
2052 .get_ethtool_stats = b44_get_ethtool_stats,
2053};
2054
2055static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2056{
2057 struct mii_ioctl_data *data = if_mii(ifr);
2058 struct b44 *bp = netdev_priv(dev);
2059 int err = -EINVAL;
2060
2061 if (!netif_running(dev))
2062 goto out;
2063
2064 spin_lock_irq(&bp->lock);
2065 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2066 spin_unlock_irq(&bp->lock);
2067out:
2068 return err;
2069}
2070
2071static int __devinit b44_get_invariants(struct b44 *bp)
2072{
2073 struct ssb_device *sdev = bp->sdev;
2074 int err = 0;
2075 u8 *addr;
2076
2077 bp->dma_offset = ssb_dma_translation(sdev);
2078
2079 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2080 instance > 1) {
2081 addr = sdev->bus->sprom.et1mac;
2082 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2083 } else {
2084 addr = sdev->bus->sprom.et0mac;
2085 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2086 }
2087
2088
2089
2090 bp->phy_addr &= 0x1F;
2091
2092 memcpy(bp->dev->dev_addr, addr, 6);
2093
2094 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2095 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2096 return -EINVAL;
2097 }
2098
2099 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
2100
2101 bp->imask = IMASK_DEF;
2102
2103
2104
2105
2106
2107 if (bp->sdev->id.revision >= 7)
2108 bp->flags |= B44_FLAG_B0_ANDLATER;
2109
2110 return err;
2111}
2112
2113static int __devinit b44_init_one(struct ssb_device *sdev,
2114 const struct ssb_device_id *ent)
2115{
2116 static int b44_version_printed = 0;
2117 struct net_device *dev;
2118 struct b44 *bp;
2119 int err;
2120 DECLARE_MAC_BUF(mac);
2121
2122 instance++;
2123
2124 if (b44_version_printed++ == 0)
2125 printk(KERN_INFO "%s", version);
2126
2127
2128 dev = alloc_etherdev(sizeof(*bp));
2129 if (!dev) {
2130 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
2131 err = -ENOMEM;
2132 goto out;
2133 }
2134
2135 SET_NETDEV_DEV(dev, sdev->dev);
2136
2137
2138 dev->features |= 0;
2139
2140 bp = netdev_priv(dev);
2141 bp->sdev = sdev;
2142 bp->dev = dev;
2143
2144 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2145
2146 spin_lock_init(&bp->lock);
2147
2148 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2149 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2150
2151 dev->open = b44_open;
2152 dev->stop = b44_close;
2153 dev->hard_start_xmit = b44_start_xmit;
2154 dev->get_stats = b44_get_stats;
2155 dev->set_multicast_list = b44_set_rx_mode;
2156 dev->set_mac_address = b44_set_mac_addr;
2157 dev->do_ioctl = b44_ioctl;
2158 dev->tx_timeout = b44_tx_timeout;
2159 netif_napi_add(dev, &bp->napi, b44_poll, 64);
2160 dev->watchdog_timeo = B44_TX_TIMEOUT;
2161#ifdef CONFIG_NET_POLL_CONTROLLER
2162 dev->poll_controller = b44_poll_controller;
2163#endif
2164 dev->change_mtu = b44_change_mtu;
2165 dev->irq = sdev->irq;
2166 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2167
2168 netif_carrier_off(dev);
2169
2170 err = ssb_bus_powerup(sdev->bus, 0);
2171 if (err) {
2172 dev_err(sdev->dev,
2173 "Failed to powerup the bus\n");
2174 goto err_out_free_dev;
2175 }
2176 err = ssb_dma_set_mask(sdev, DMA_30BIT_MASK);
2177 if (err) {
2178 dev_err(sdev->dev,
2179 "Required 30BIT DMA mask unsupported by the system.\n");
2180 goto err_out_powerdown;
2181 }
2182 err = b44_get_invariants(bp);
2183 if (err) {
2184 dev_err(sdev->dev,
2185 "Problem fetching invariants of chip, aborting.\n");
2186 goto err_out_powerdown;
2187 }
2188
2189 bp->mii_if.dev = dev;
2190 bp->mii_if.mdio_read = b44_mii_read;
2191 bp->mii_if.mdio_write = b44_mii_write;
2192 bp->mii_if.phy_id = bp->phy_addr;
2193 bp->mii_if.phy_id_mask = 0x1f;
2194 bp->mii_if.reg_num_mask = 0x1f;
2195
2196
2197 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2198 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2199
2200
2201 bp->flags |= B44_FLAG_PAUSE_AUTO;
2202
2203 err = register_netdev(dev);
2204 if (err) {
2205 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2206 goto err_out_powerdown;
2207 }
2208
2209 ssb_set_drvdata(sdev, dev);
2210
2211
2212
2213
2214 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2215
2216 printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
2217 dev->name, print_mac(mac, dev->dev_addr));
2218
2219 return 0;
2220
2221err_out_powerdown:
2222 ssb_bus_may_powerdown(sdev->bus);
2223
2224err_out_free_dev:
2225 free_netdev(dev);
2226
2227out:
2228 return err;
2229}
2230
2231static void __devexit b44_remove_one(struct ssb_device *sdev)
2232{
2233 struct net_device *dev = ssb_get_drvdata(sdev);
2234
2235 unregister_netdev(dev);
2236 ssb_bus_may_powerdown(sdev->bus);
2237 free_netdev(dev);
2238 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2239 ssb_set_drvdata(sdev, NULL);
2240}
2241
2242static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2243{
2244 struct net_device *dev = ssb_get_drvdata(sdev);
2245 struct b44 *bp = netdev_priv(dev);
2246
2247 if (!netif_running(dev))
2248 return 0;
2249
2250 del_timer_sync(&bp->timer);
2251
2252 spin_lock_irq(&bp->lock);
2253
2254 b44_halt(bp);
2255 netif_carrier_off(bp->dev);
2256 netif_device_detach(bp->dev);
2257 b44_free_rings(bp);
2258
2259 spin_unlock_irq(&bp->lock);
2260
2261 free_irq(dev->irq, dev);
2262 if (bp->flags & B44_FLAG_WOL_ENABLE) {
2263 b44_init_hw(bp, B44_PARTIAL_RESET);
2264 b44_setup_wol(bp);
2265 }
2266
2267 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2268 return 0;
2269}
2270
2271static int b44_resume(struct ssb_device *sdev)
2272{
2273 struct net_device *dev = ssb_get_drvdata(sdev);
2274 struct b44 *bp = netdev_priv(dev);
2275 int rc = 0;
2276
2277 rc = ssb_bus_powerup(sdev->bus, 0);
2278 if (rc) {
2279 dev_err(sdev->dev,
2280 "Failed to powerup the bus\n");
2281 return rc;
2282 }
2283
2284 if (!netif_running(dev))
2285 return 0;
2286
2287 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2288 if (rc) {
2289 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2290 return rc;
2291 }
2292
2293 spin_lock_irq(&bp->lock);
2294
2295 b44_init_rings(bp);
2296 b44_init_hw(bp, B44_FULL_RESET);
2297 netif_device_attach(bp->dev);
2298 spin_unlock_irq(&bp->lock);
2299
2300 b44_enable_ints(bp);
2301 netif_wake_queue(dev);
2302
2303 mod_timer(&bp->timer, jiffies + 1);
2304
2305 return 0;
2306}
2307
2308static struct ssb_driver b44_ssb_driver = {
2309 .name = DRV_MODULE_NAME,
2310 .id_table = b44_ssb_tbl,
2311 .probe = b44_init_one,
2312 .remove = __devexit_p(b44_remove_one),
2313 .suspend = b44_suspend,
2314 .resume = b44_resume,
2315};
2316
2317static inline int b44_pci_init(void)
2318{
2319 int err = 0;
2320#ifdef CONFIG_B44_PCI
2321 err = ssb_pcihost_register(&b44_pci_driver);
2322#endif
2323 return err;
2324}
2325
2326static inline void b44_pci_exit(void)
2327{
2328#ifdef CONFIG_B44_PCI
2329 ssb_pcihost_unregister(&b44_pci_driver);
2330#endif
2331}
2332
2333static int __init b44_init(void)
2334{
2335 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2336 int err;
2337
2338
2339 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2340 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2341
2342 err = b44_pci_init();
2343 if (err)
2344 return err;
2345 err = ssb_driver_register(&b44_ssb_driver);
2346 if (err)
2347 b44_pci_exit();
2348 return err;
2349}
2350
2351static void __exit b44_cleanup(void)
2352{
2353 ssb_driver_unregister(&b44_ssb_driver);
2354 b44_pci_exit();
2355}
2356
2357module_init(b44_init);
2358module_exit(b44_cleanup);
2359
2360
