linux/drivers/ieee1394/ohci1394.h
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   1/*
   2 * ohci1394.h - driver for OHCI 1394 boards
   3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
   4 *                        Gord Peters <GordPeters@smarttech.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software Foundation,
  18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19 */
  20
  21#ifndef _OHCI1394_H
  22#define _OHCI1394_H
  23
  24#include "ieee1394_types.h"
  25#include <asm/io.h>
  26
  27#define OHCI1394_DRIVER_NAME      "ohci1394"
  28
  29#define OHCI1394_MAX_AT_REQ_RETRIES     0x2
  30#define OHCI1394_MAX_AT_RESP_RETRIES    0x2
  31#define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
  32#define OHCI1394_MAX_SELF_ID_ERRORS     16
  33
  34#define AR_REQ_NUM_DESC         4               /* number of AR req descriptors */
  35#define AR_REQ_BUF_SIZE         PAGE_SIZE       /* size of AR req buffers */
  36#define AR_REQ_SPLIT_BUF_SIZE   PAGE_SIZE       /* split packet buffer */
  37
  38#define AR_RESP_NUM_DESC        4               /* number of AR resp descriptors */
  39#define AR_RESP_BUF_SIZE        PAGE_SIZE       /* size of AR resp buffers */
  40#define AR_RESP_SPLIT_BUF_SIZE  PAGE_SIZE       /* split packet buffer */
  41
  42#define IR_NUM_DESC             16              /* number of IR descriptors */
  43#define IR_BUF_SIZE             PAGE_SIZE       /* 4096 bytes/buffer */
  44#define IR_SPLIT_BUF_SIZE       PAGE_SIZE       /* split packet buffer */
  45
  46#define IT_NUM_DESC             16      /* number of IT descriptors */
  47
  48#define AT_REQ_NUM_DESC         32      /* number of AT req descriptors */
  49#define AT_RESP_NUM_DESC        32      /* number of AT resp descriptors */
  50
  51#define OHCI_LOOP_COUNT         100     /* Number of loops for reg read waits */
  52
  53#define OHCI_CONFIG_ROM_LEN     1024    /* Length of the mapped configrom space */
  54
  55#define OHCI1394_SI_DMA_BUF_SIZE        8192 /* length of the selfid buffer */
  56
  57/* PCI configuration space addresses */
  58#define OHCI1394_PCI_HCI_Control 0x40
  59
  60struct dma_cmd {
  61        u32 control;
  62        u32 address;
  63        u32 branchAddress;
  64        u32 status;
  65};
  66
  67/*
  68 * FIXME:
  69 * It is important that a single at_dma_prg does not cross a page boundary
  70 * The proper way to do it would be to do the check dynamically as the
  71 * programs are inserted into the AT fifo.
  72 */
  73struct at_dma_prg {
  74        struct dma_cmd begin;
  75        quadlet_t data[4];
  76        struct dma_cmd end;
  77        quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  78};
  79
  80/* identify whether a DMA context is asynchronous or isochronous */
  81enum context_type { DMA_CTX_ASYNC_REQ, DMA_CTX_ASYNC_RESP, DMA_CTX_ISO };
  82
  83/* DMA receive context */
  84struct dma_rcv_ctx {
  85        struct ti_ohci *ohci;
  86        enum context_type type;
  87        int ctx;
  88        unsigned int num_desc;
  89
  90        unsigned int buf_size;
  91        unsigned int split_buf_size;
  92
  93        /* dma block descriptors */
  94        struct dma_cmd **prg_cpu;
  95        dma_addr_t *prg_bus;
  96        struct pci_pool *prg_pool;
  97
  98        /* dma buffers */
  99        quadlet_t **buf_cpu;
 100        dma_addr_t *buf_bus;
 101
 102        unsigned int buf_ind;
 103        unsigned int buf_offset;
 104        quadlet_t *spb;
 105        spinlock_t lock;
 106        struct tasklet_struct task;
 107        int ctrlClear;
 108        int ctrlSet;
 109        int cmdPtr;
 110        int ctxtMatch;
 111};
 112
 113/* DMA transmit context */
 114struct dma_trm_ctx {
 115        struct ti_ohci *ohci;
 116        enum context_type type;
 117        int ctx;
 118        unsigned int num_desc;
 119
 120        /* dma block descriptors */
 121        struct at_dma_prg **prg_cpu;
 122        dma_addr_t *prg_bus;
 123        struct pci_pool *prg_pool;
 124
 125        unsigned int prg_ind;
 126        unsigned int sent_ind;
 127        int free_prgs;
 128        quadlet_t *branchAddrPtr;
 129
 130        /* list of packets inserted in the AT FIFO */
 131        struct list_head fifo_list;
 132
 133        /* list of pending packets to be inserted in the AT FIFO */
 134        struct list_head pending_list;
 135
 136        spinlock_t lock;
 137        struct tasklet_struct task;
 138        int ctrlClear;
 139        int ctrlSet;
 140        int cmdPtr;
 141};
 142
 143struct ohci1394_iso_tasklet {
 144        struct tasklet_struct tasklet;
 145        struct list_head link;
 146        int context;
 147        enum { OHCI_ISO_TRANSMIT, OHCI_ISO_RECEIVE,
 148               OHCI_ISO_MULTICHANNEL_RECEIVE } type;
 149};
 150
 151struct ti_ohci {
 152        struct pci_dev *dev;
 153
 154        enum {
 155                OHCI_INIT_ALLOC_HOST,
 156                OHCI_INIT_HAVE_MEM_REGION,
 157                OHCI_INIT_HAVE_IOMAPPING,
 158                OHCI_INIT_HAVE_CONFIG_ROM_BUFFER,
 159                OHCI_INIT_HAVE_SELFID_BUFFER,
 160                OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE,
 161                OHCI_INIT_HAVE_IRQ,
 162                OHCI_INIT_DONE,
 163        } init_state;
 164
 165        /* remapped memory spaces */
 166        void __iomem *registers;
 167
 168        /* dma buffer for self-id packets */
 169        quadlet_t *selfid_buf_cpu;
 170        dma_addr_t selfid_buf_bus;
 171
 172        /* buffer for csr config rom */
 173        quadlet_t *csr_config_rom_cpu;
 174        dma_addr_t csr_config_rom_bus;
 175        int csr_config_rom_length;
 176
 177        unsigned int max_packet_size;
 178
 179        /* async receive */
 180        struct dma_rcv_ctx ar_resp_context;
 181        struct dma_rcv_ctx ar_req_context;
 182
 183        /* async transmit */
 184        struct dma_trm_ctx at_resp_context;
 185        struct dma_trm_ctx at_req_context;
 186
 187        /* iso receive */
 188        int nb_iso_rcv_ctx;
 189        unsigned long ir_ctx_usage; /* use test_and_set_bit() for atomicity */
 190        unsigned long ir_multichannel_used; /* ditto */
 191        spinlock_t IR_channel_lock;
 192
 193        /* iso transmit */
 194        int nb_iso_xmit_ctx;
 195        unsigned long it_ctx_usage; /* use test_and_set_bit() for atomicity */
 196
 197        u64 ISO_channel_usage;
 198
 199        /* IEEE-1394 part follows */
 200        struct hpsb_host *host;
 201
 202        int phyid, isroot;
 203
 204        spinlock_t phy_reg_lock;
 205        spinlock_t event_lock;
 206
 207        int self_id_errors;
 208
 209        /* Tasklets for iso receive and transmit, used by video1394
 210         * and dv1394 */
 211        struct list_head iso_tasklet_list;
 212        spinlock_t iso_tasklet_list_lock;
 213
 214        /* Swap the selfid buffer? */
 215        unsigned int selfid_swap:1;
 216        /* Some Apple chipset seem to swap incoming headers for us */
 217        unsigned int no_swap_incoming:1;
 218
 219        /* Force extra paranoia checking on bus-reset handling */
 220        unsigned int check_busreset:1;
 221};
 222
 223static inline int cross_bound(unsigned long addr, unsigned int size)
 224{
 225        if (size == 0)
 226                return 0;
 227
 228        if (size > PAGE_SIZE)
 229                return 1;
 230
 231        if (addr >> PAGE_SHIFT != (addr + size - 1) >> PAGE_SHIFT)
 232                return 1;
 233
 234        return 0;
 235}
 236
 237/*
 238 * Register read and write helper functions.
 239 */
 240static inline void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
 241{
 242        writel(data, ohci->registers + offset);
 243}
 244
 245static inline u32 reg_read(const struct ti_ohci *ohci, int offset)
 246{
 247        return readl(ohci->registers + offset);
 248}
 249
 250
 251/* 2 KiloBytes of register space */
 252#define OHCI1394_REGISTER_SIZE                0x800
 253
 254/* Offsets relative to context bases defined below */
 255
 256#define OHCI1394_ContextControlSet            0x000
 257#define OHCI1394_ContextControlClear          0x004
 258#define OHCI1394_ContextCommandPtr            0x00C
 259
 260/* register map */
 261#define OHCI1394_Version                      0x000
 262#define OHCI1394_GUID_ROM                     0x004
 263#define OHCI1394_ATRetries                    0x008
 264#define OHCI1394_CSRData                      0x00C
 265#define OHCI1394_CSRCompareData               0x010
 266#define OHCI1394_CSRControl                   0x014
 267#define OHCI1394_ConfigROMhdr                 0x018
 268#define OHCI1394_BusID                        0x01C
 269#define OHCI1394_BusOptions                   0x020
 270#define OHCI1394_GUIDHi                       0x024
 271#define OHCI1394_GUIDLo                       0x028
 272#define OHCI1394_ConfigROMmap                 0x034
 273#define OHCI1394_PostedWriteAddressLo         0x038
 274#define OHCI1394_PostedWriteAddressHi         0x03C
 275#define OHCI1394_VendorID                     0x040
 276#define OHCI1394_HCControlSet                 0x050
 277#define OHCI1394_HCControlClear               0x054
 278#define  OHCI1394_HCControl_noByteSwap          0x40000000
 279#define  OHCI1394_HCControl_programPhyEnable    0x00800000
 280#define  OHCI1394_HCControl_aPhyEnhanceEnable   0x00400000
 281#define  OHCI1394_HCControl_LPS                 0x00080000
 282#define  OHCI1394_HCControl_postedWriteEnable   0x00040000
 283#define  OHCI1394_HCControl_linkEnable          0x00020000
 284#define  OHCI1394_HCControl_softReset           0x00010000
 285#define OHCI1394_SelfIDBuffer                 0x064
 286#define OHCI1394_SelfIDCount                  0x068
 287#define OHCI1394_IRMultiChanMaskHiSet         0x070
 288#define OHCI1394_IRMultiChanMaskHiClear       0x074
 289#define OHCI1394_IRMultiChanMaskLoSet         0x078
 290#define OHCI1394_IRMultiChanMaskLoClear       0x07C
 291#define OHCI1394_IntEventSet                  0x080
 292#define OHCI1394_IntEventClear                0x084
 293#define OHCI1394_IntMaskSet                   0x088
 294#define OHCI1394_IntMaskClear                 0x08C
 295#define OHCI1394_IsoXmitIntEventSet           0x090
 296#define OHCI1394_IsoXmitIntEventClear         0x094
 297#define OHCI1394_IsoXmitIntMaskSet            0x098
 298#define OHCI1394_IsoXmitIntMaskClear          0x09C
 299#define OHCI1394_IsoRecvIntEventSet           0x0A0
 300#define OHCI1394_IsoRecvIntEventClear         0x0A4
 301#define OHCI1394_IsoRecvIntMaskSet            0x0A8
 302#define OHCI1394_IsoRecvIntMaskClear          0x0AC
 303#define OHCI1394_InitialBandwidthAvailable    0x0B0
 304#define OHCI1394_InitialChannelsAvailableHi   0x0B4
 305#define OHCI1394_InitialChannelsAvailableLo   0x0B8
 306#define OHCI1394_FairnessControl              0x0DC
 307#define OHCI1394_LinkControlSet               0x0E0
 308#define OHCI1394_LinkControlClear             0x0E4
 309#define  OHCI1394_LinkControl_RcvSelfID         0x00000200
 310#define  OHCI1394_LinkControl_RcvPhyPkt         0x00000400
 311#define  OHCI1394_LinkControl_CycleTimerEnable  0x00100000
 312#define  OHCI1394_LinkControl_CycleMaster       0x00200000
 313#define  OHCI1394_LinkControl_CycleSource       0x00400000
 314#define OHCI1394_NodeID                       0x0E8
 315#define OHCI1394_PhyControl                   0x0EC
 316#define OHCI1394_IsochronousCycleTimer        0x0F0
 317#define OHCI1394_AsReqFilterHiSet             0x100
 318#define OHCI1394_AsReqFilterHiClear           0x104
 319#define OHCI1394_AsReqFilterLoSet             0x108
 320#define OHCI1394_AsReqFilterLoClear           0x10C
 321#define OHCI1394_PhyReqFilterHiSet            0x110
 322#define OHCI1394_PhyReqFilterHiClear          0x114
 323#define OHCI1394_PhyReqFilterLoSet            0x118
 324#define OHCI1394_PhyReqFilterLoClear          0x11C
 325#define OHCI1394_PhyUpperBound                0x120
 326
 327#define OHCI1394_AsReqTrContextBase           0x180
 328#define OHCI1394_AsReqTrContextControlSet     0x180
 329#define OHCI1394_AsReqTrContextControlClear   0x184
 330#define OHCI1394_AsReqTrCommandPtr            0x18C
 331
 332#define OHCI1394_AsRspTrContextBase           0x1A0
 333#define OHCI1394_AsRspTrContextControlSet     0x1A0
 334#define OHCI1394_AsRspTrContextControlClear   0x1A4
 335#define OHCI1394_AsRspTrCommandPtr            0x1AC
 336
 337#define OHCI1394_AsReqRcvContextBase          0x1C0
 338#define OHCI1394_AsReqRcvContextControlSet    0x1C0
 339#define OHCI1394_AsReqRcvContextControlClear  0x1C4
 340#define OHCI1394_AsReqRcvCommandPtr           0x1CC
 341
 342#define OHCI1394_AsRspRcvContextBase          0x1E0
 343#define OHCI1394_AsRspRcvContextControlSet    0x1E0
 344#define OHCI1394_AsRspRcvContextControlClear  0x1E4
 345#define OHCI1394_AsRspRcvCommandPtr           0x1EC
 346
 347/* Isochronous transmit registers */
 348/* Add (16 * n) for context n */
 349#define OHCI1394_IsoXmitContextBase           0x200
 350#define OHCI1394_IsoXmitContextControlSet     0x200
 351#define OHCI1394_IsoXmitContextControlClear   0x204
 352#define OHCI1394_IsoXmitCommandPtr            0x20C
 353
 354/* Isochronous receive registers */
 355/* Add (32 * n) for context n */
 356#define OHCI1394_IsoRcvContextBase            0x400
 357#define OHCI1394_IsoRcvContextControlSet      0x400
 358#define OHCI1394_IsoRcvContextControlClear    0x404
 359#define OHCI1394_IsoRcvCommandPtr             0x40C
 360#define OHCI1394_IsoRcvContextMatch           0x410
 361
 362/* Interrupts Mask/Events */
 363
 364#define OHCI1394_reqTxComplete           0x00000001
 365#define OHCI1394_respTxComplete          0x00000002
 366#define OHCI1394_ARRQ                    0x00000004
 367#define OHCI1394_ARRS                    0x00000008
 368#define OHCI1394_RQPkt                   0x00000010
 369#define OHCI1394_RSPkt                   0x00000020
 370#define OHCI1394_isochTx                 0x00000040
 371#define OHCI1394_isochRx                 0x00000080
 372#define OHCI1394_postedWriteErr          0x00000100
 373#define OHCI1394_lockRespErr             0x00000200
 374#define OHCI1394_selfIDComplete          0x00010000
 375#define OHCI1394_busReset                0x00020000
 376#define OHCI1394_phy                     0x00080000
 377#define OHCI1394_cycleSynch              0x00100000
 378#define OHCI1394_cycle64Seconds          0x00200000
 379#define OHCI1394_cycleLost               0x00400000
 380#define OHCI1394_cycleInconsistent       0x00800000
 381#define OHCI1394_unrecoverableError      0x01000000
 382#define OHCI1394_cycleTooLong            0x02000000
 383#define OHCI1394_phyRegRcvd              0x04000000
 384#define OHCI1394_masterIntEnable         0x80000000
 385
 386/* DMA Control flags */
 387#define DMA_CTL_OUTPUT_MORE              0x00000000
 388#define DMA_CTL_OUTPUT_LAST              0x10000000
 389#define DMA_CTL_INPUT_MORE               0x20000000
 390#define DMA_CTL_INPUT_LAST               0x30000000
 391#define DMA_CTL_UPDATE                   0x08000000
 392#define DMA_CTL_IMMEDIATE                0x02000000
 393#define DMA_CTL_IRQ                      0x00300000
 394#define DMA_CTL_BRANCH                   0x000c0000
 395#define DMA_CTL_WAIT                     0x00030000
 396
 397/* OHCI evt_* error types, table 3-2 of the OHCI 1.1 spec. */
 398#define EVT_NO_STATUS           0x0     /* No event status */
 399#define EVT_RESERVED_A          0x1     /* Reserved, not used !!! */
 400#define EVT_LONG_PACKET         0x2     /* The revc data was longer than the buf */
 401#define EVT_MISSING_ACK         0x3     /* A subaction gap was detected before an ack
 402                                           arrived, or recv'd ack had a parity error */
 403#define EVT_UNDERRUN            0x4     /* Underrun on corresponding FIFO, packet
 404                                           truncated */
 405#define EVT_OVERRUN             0x5     /* A recv FIFO overflowed on reception of ISO
 406                                           packet */
 407#define EVT_DESCRIPTOR_READ     0x6     /* An unrecoverable error occurred while host was
 408                                           reading a descriptor block */
 409#define EVT_DATA_READ           0x7     /* An error occurred while host controller was
 410                                           attempting to read from host memory in the data
 411                                           stage of descriptor processing */
 412#define EVT_DATA_WRITE          0x8     /* An error occurred while host controller was
 413                                           attempting to write either during the data stage
 414                                           of descriptor processing, or when processing a single
 415                                           16-bit host memory write */
 416#define EVT_BUS_RESET           0x9     /* Identifies a PHY packet in the recv buffer as
 417                                           being a synthesized bus reset packet */
 418#define EVT_TIMEOUT             0xa     /* Indicates that the asynchronous transmit response
 419                                           packet expired and was not transmitted, or that an
 420                                           IT DMA context experienced a skip processing overflow */
 421#define EVT_TCODE_ERR           0xb     /* A bad tCode is associated with this packet.
 422                                           The packet was flushed */
 423#define EVT_RESERVED_B          0xc     /* Reserved, not used !!! */
 424#define EVT_RESERVED_C          0xd     /* Reserved, not used !!! */
 425#define EVT_UNKNOWN             0xe     /* An error condition has occurred that cannot be
 426                                           represented by any other event codes defined herein. */
 427#define EVT_FLUSHED             0xf     /* Send by the link side of output FIFO when asynchronous
 428                                           packets are being flushed due to a bus reset. */
 429
 430#define OHCI1394_TCODE_PHY               0xE
 431
 432/* Node offset map (phys DMA area, posted write area).
 433 * The value of OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED may be modified but must
 434 * be lower than OHCI1394_MIDDLE_ADDRESS_SPACE.
 435 * OHCI1394_PHYS_UPPER_BOUND_FIXED and OHCI1394_MIDDLE_ADDRESS_SPACE are
 436 * constants given by the OHCI spec.
 437 */
 438#define OHCI1394_PHYS_UPPER_BOUND_FIXED         0x000100000000ULL /* 4 GB */
 439#define OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED    0x010000000000ULL /* 1 TB */
 440#define OHCI1394_MIDDLE_ADDRESS_SPACE           0xffff00000000ULL
 441
 442void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet,
 443                               int type,
 444                               void (*func)(unsigned long),
 445                               unsigned long data);
 446int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
 447                                  struct ohci1394_iso_tasklet *tasklet);
 448void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
 449                                     struct ohci1394_iso_tasklet *tasklet);
 450int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg);
 451struct ti_ohci *ohci1394_get_struct(int card_num);
 452
 453#endif
 454