LXR linux/arch/x86/kernel/irqinit

   1#include <linux/linkage.h>
   2#include <linux/errno.h>
   3#include <linux/signal.h>
   4#include <linux/sched.h>
   5#include <linux/ioport.h>
   6#include <linux/interrupt.h>
   7#include <linux/timex.h>
   8#include <linux/slab.h>
   9#include <linux/random.h>
  10#include <linux/init.h>
  11#include <linux/kernel_stat.h>
  12#include <linux/sysdev.h>
  13#include <linux/bitops.h>
  14
  15#include <asm/acpi.h>
  16#include <asm/atomic.h>
  17#include <asm/system.h>
  18#include <asm/io.h>
  19#include <asm/hw_irq.h>
  20#include <asm/pgtable.h>
  21#include <asm/delay.h>
  22#include <asm/desc.h>
  23#include <asm/apic.h>
  24#include <asm/i8259.h>
  25
  26/*
  27 * Common place to define all x86 IRQ vectors
  28 *
  29 * This builds up the IRQ handler stubs using some ugly macros in irq.h
  30 *
  31 * These macros create the low-level assembly IRQ routines that save
  32 * register context and call do_IRQ(). do_IRQ() then does all the
  33 * operations that are needed to keep the AT (or SMP IOAPIC)
  34 * interrupt-controller happy.
  35 */
  36
  37#define IRQ_NAME2(nr) nr##_interrupt(void)
  38#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
  39
  40/*
  41 *      SMP has a few special interrupts for IPI messages
  42 */
  43
  44#define BUILD_IRQ(nr)                           \
  45        asmlinkage void IRQ_NAME(nr);           \
  46        asm("\n.text\n.p2align\n"               \
  47            "IRQ" #nr "_interrupt:\n\t"         \
  48            "push $~(" #nr ") ; "               \
  49            "jmp common_interrupt\n"            \
  50            ".previous");
  51
  52#define BI(x,y) \
  53        BUILD_IRQ(x##y)
  54
  55#define BUILD_16_IRQS(x) \
  56        BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  57        BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  58        BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  59        BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  60
  61/*
  62 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  63 * (these are usually mapped to vectors 0x30-0x3f)
  64 */
  65
  66/*
  67 * The IO-APIC gives us many more interrupt sources. Most of these
  68 * are unused but an SMP system is supposed to have enough memory ...
  69 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  70 * across the spectrum, so we really want to be prepared to get all
  71 * of these. Plus, more powerful systems might have more than 64
  72 * IO-APIC registers.
  73 *
  74 * (these are usually mapped into the 0x30-0xff vector range)
  75 */
  76                                      BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  77BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  78BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  79BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
  80
  81#undef BUILD_16_IRQS
  82#undef BI
  83
  84
  85#define IRQ(x,y) \
  86        IRQ##x##y##_interrupt
  87
  88#define IRQLIST_16(x) \
  89        IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  90        IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  91        IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  92        IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
  93
  94/* for the irq vectors */
  95static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
  96                                          IRQLIST_16(0x2), IRQLIST_16(0x3),
  97        IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
  98        IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
  99        IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
 100};
 101
 102#undef IRQ
 103#undef IRQLIST_16
 104
 105
 106
 107
 108/*
 109 * IRQ2 is cascade interrupt to second interrupt controller
 110 */
 111
 112static struct irqaction irq2 = {
 113        .handler = no_action,
 114        .mask = CPU_MASK_NONE,
 115        .name = "cascade",
 116};
 117DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
 118        [0 ... IRQ0_VECTOR - 1] = -1,
 119        [IRQ0_VECTOR] = 0,
 120        [IRQ1_VECTOR] = 1,
 121        [IRQ2_VECTOR] = 2,
 122        [IRQ3_VECTOR] = 3,
 123        [IRQ4_VECTOR] = 4,
 124        [IRQ5_VECTOR] = 5,
 125        [IRQ6_VECTOR] = 6,
 126        [IRQ7_VECTOR] = 7,
 127        [IRQ8_VECTOR] = 8,
 128        [IRQ9_VECTOR] = 9,
 129        [IRQ10_VECTOR] = 10,
 130        [IRQ11_VECTOR] = 11,
 131        [IRQ12_VECTOR] = 12,
 132        [IRQ13_VECTOR] = 13,
 133        [IRQ14_VECTOR] = 14,
 134        [IRQ15_VECTOR] = 15,
 135        [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 136};
 137
 138void __init init_ISA_irqs(void)
 139{
 140        int i;
 141
 142        init_bsp_APIC();
 143        init_8259A(0);
 144
 145        for (i = 0; i < 16; i++) {
 146                /* first time call this irq_desc */
 147                struct irq_desc *desc = irq_to_desc(i);
 148
 149                desc->status = IRQ_DISABLED;
 150                desc->action = NULL;
 151                desc->depth = 1;
 152
 153                /*
 154                 * 16 old-style INTA-cycle interrupts:
 155                 */
 156                set_irq_chip_and_handler_name(i, &i8259A_chip,
 157                                                      handle_level_irq, "XT");
 158        }
 159}
 160
 161void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 162
 163static void __init smp_intr_init(void)
 164{
 165#ifdef CONFIG_SMP
 166        /*
 167         * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 168         * IPI, driven by wakeup.
 169         */
 170        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 171
 172        /* IPIs for invalidation */
 173        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 174        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 175        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 176        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 177        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 178        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 179        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 180        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 181
 182        /* IPI for generic function call */
 183        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 184
 185        /* IPI for generic single function call */
 186        alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 187                        call_function_single_interrupt);
 188
 189        /* Low priority IPI to cleanup after moving an irq */
 190        set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 191#endif
 192}
 193
 194static void __init apic_intr_init(void)
 195{
 196        smp_intr_init();
 197
 198        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 199        alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 200
 201        /* self generated IPI for local APIC timer */
 202        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 203
 204        /* IPI vectors for APIC spurious and error interrupts */
 205        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 206        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 207}
 208
 209void __init native_init_IRQ(void)
 210{
 211        int i;
 212
 213        init_ISA_irqs();
 214        /*
 215         * Cover the whole vector space, no vector can escape
 216         * us. (some of these will be overridden and become
 217         * 'special' SMP interrupts)
 218         */
 219        for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
 220                int vector = FIRST_EXTERNAL_VECTOR + i;
 221                if (vector != IA32_SYSCALL_VECTOR)
 222                        set_intr_gate(vector, interrupt[i]);
 223        }
 224
 225        apic_intr_init();
 226
 227        if (!acpi_ioapic)
 228                setup_irq(2, &irq2);
 229}
 230