LXR linux/arch/x86/kernel/irqinit

   1#include <linux/errno.h>
   2#include <linux/signal.h>
   3#include <linux/sched.h>
   4#include <linux/ioport.h>
   5#include <linux/interrupt.h>
   6#include <linux/slab.h>
   7#include <linux/random.h>
   8#include <linux/init.h>
   9#include <linux/kernel_stat.h>
  10#include <linux/sysdev.h>
  11#include <linux/bitops.h>
  12
  13#include <asm/atomic.h>
  14#include <asm/system.h>
  15#include <asm/io.h>
  16#include <asm/timer.h>
  17#include <asm/pgtable.h>
  18#include <asm/delay.h>
  19#include <asm/desc.h>
  20#include <asm/apic.h>
  21#include <asm/arch_hooks.h>
  22#include <asm/i8259.h>
  23
  24
  25
  26/*
  27 * Note that on a 486, we don't want to do a SIGFPE on an irq13
  28 * as the irq is unreliable, and exception 16 works correctly
  29 * (ie as explained in the intel literature). On a 386, you
  30 * can't use exception 16 due to bad IBM design, so we have to
  31 * rely on the less exact irq13.
  32 *
  33 * Careful.. Not only is IRQ13 unreliable, but it is also
  34 * leads to races. IBM designers who came up with it should
  35 * be shot.
  36 */
  37 
  38
  39static irqreturn_t math_error_irq(int cpl, void *dev_id)
  40{
  41        extern void math_error(void __user *);
  42        outb(0,0xF0);
  43        if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  44                return IRQ_NONE;
  45        math_error((void __user *)get_irq_regs()->ip);
  46        return IRQ_HANDLED;
  47}
  48
  49/*
  50 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  51 * so allow interrupt sharing.
  52 */
  53static struct irqaction fpu_irq = {
  54        .handler = math_error_irq,
  55        .mask = CPU_MASK_NONE,
  56        .name = "fpu",
  57};
  58
  59void __init init_ISA_irqs (void)
  60{
  61        int i;
  62
  63#ifdef CONFIG_X86_LOCAL_APIC
  64        init_bsp_APIC();
  65#endif
  66        init_8259A(0);
  67
  68        /*
  69         * 16 old-style INTA-cycle interrupts:
  70         */
  71        for (i = 0; i < 16; i++) {
  72                /* first time call this irq_desc */
  73                struct irq_desc *desc = irq_to_desc(i);
  74
  75                desc->status = IRQ_DISABLED;
  76                desc->action = NULL;
  77                desc->depth = 1;
  78
  79                set_irq_chip_and_handler_name(i, &i8259A_chip,
  80                                              handle_level_irq, "XT");
  81        }
  82}
  83
  84/*
  85 * IRQ2 is cascade interrupt to second interrupt controller
  86 */
  87static struct irqaction irq2 = {
  88        .handler = no_action,
  89        .mask = CPU_MASK_NONE,
  90        .name = "cascade",
  91};
  92
  93DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  94        [0 ... IRQ0_VECTOR - 1] = -1,
  95        [IRQ0_VECTOR] = 0,
  96        [IRQ1_VECTOR] = 1,
  97        [IRQ2_VECTOR] = 2,
  98        [IRQ3_VECTOR] = 3,
  99        [IRQ4_VECTOR] = 4,
 100        [IRQ5_VECTOR] = 5,
 101        [IRQ6_VECTOR] = 6,
 102        [IRQ7_VECTOR] = 7,
 103        [IRQ8_VECTOR] = 8,
 104        [IRQ9_VECTOR] = 9,
 105        [IRQ10_VECTOR] = 10,
 106        [IRQ11_VECTOR] = 11,
 107        [IRQ12_VECTOR] = 12,
 108        [IRQ13_VECTOR] = 13,
 109        [IRQ14_VECTOR] = 14,
 110        [IRQ15_VECTOR] = 15,
 111        [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 112};
 113
 114/* Overridden in paravirt.c */
 115void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 116
 117void __init native_init_IRQ(void)
 118{
 119        int i;
 120
 121        /* all the set up before the call gates are initialised */
 122        pre_intr_init_hook();
 123
 124        /*
 125         * Cover the whole vector space, no vector can escape
 126         * us. (some of these will be overridden and become
 127         * 'special' SMP interrupts)
 128         */
 129        for (i =  FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
 130                /* SYSCALL_VECTOR was reserved in trap_init. */
 131                if (i != SYSCALL_VECTOR)
 132                        set_intr_gate(i, interrupt[i]);
 133        }
 134
 135
 136#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP)
 137        /*
 138         * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 139         * IPI, driven by wakeup.
 140         */
 141        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 142
 143        /* IPI for invalidation */
 144        alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
 145
 146        /* IPI for generic function call */
 147        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 148
 149        /* IPI for single call function */
 150        set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt);
 151
 152        /* Low priority IPI to cleanup after moving an irq */
 153        set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 154#endif
 155
 156#ifdef CONFIG_X86_LOCAL_APIC
 157        /* self generated IPI for local APIC timer */
 158        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 159
 160        /* IPI vectors for APIC spurious and error interrupts */
 161        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 162        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 163#endif
 164
 165#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_MCE_P4THERMAL)
 166        /* thermal monitor LVT interrupt */
 167        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 168#endif
 169
 170        if (!acpi_ioapic)
 171                setup_irq(2, &irq2);
 172
 173        /* setup after call gates are initialised (usually add in
 174         * the architecture specific gates)
 175         */
 176        intr_init_hook();
 177
 178        /*
 179         * External FPU? Set up irq13 if so, for
 180         * original braindamaged IBM FERR coupling.
 181         */
 182        if (boot_cpu_data.hard_math && !cpu_has_fpu)
 183                setup_irq(FPU_IRQ, &fpu_irq);
 184
 185        irq_ctx_init(smp_processor_id());
 186}
 187