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11#include <linux/kernel.h>
12#include <linux/threads.h>
13#include <linux/cpumask.h>
14#include <linux/string.h>
15#include <linux/ctype.h>
16#include <linux/init.h>
17#include <linux/sched.h>
18#include <linux/module.h>
19#include <linux/hardirq.h>
20#include <asm/smp.h>
21#include <asm/ipi.h>
22#include <asm/genapic.h>
23#include <asm/pgtable.h>
24#include <asm/uv/uv_mmrs.h>
25#include <asm/uv/uv_hub.h>
26#include <asm/uv/bios.h>
27
28DEFINE_PER_CPU(int, x2apic_extra_bits);
29
30static enum uv_system_type uv_system_type;
31
32static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
33{
34 if (!strcmp(oem_id, "SGI")) {
35 if (!strcmp(oem_table_id, "UVL"))
36 uv_system_type = UV_LEGACY_APIC;
37 else if (!strcmp(oem_table_id, "UVX"))
38 uv_system_type = UV_X2APIC;
39 else if (!strcmp(oem_table_id, "UVH")) {
40 uv_system_type = UV_NON_UNIQUE_APIC;
41 return 1;
42 }
43 }
44 return 0;
45}
46
47enum uv_system_type get_uv_system_type(void)
48{
49 return uv_system_type;
50}
51
52int is_uv_system(void)
53{
54 return uv_system_type != UV_NONE;
55}
56EXPORT_SYMBOL_GPL(is_uv_system);
57
58DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
59EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
60
61struct uv_blade_info *uv_blade_info;
62EXPORT_SYMBOL_GPL(uv_blade_info);
63
64short *uv_node_to_blade;
65EXPORT_SYMBOL_GPL(uv_node_to_blade);
66
67short *uv_cpu_to_blade;
68EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
69
70short uv_possible_blades;
71EXPORT_SYMBOL_GPL(uv_possible_blades);
72
73unsigned long sn_rtc_cycles_per_second;
74EXPORT_SYMBOL(sn_rtc_cycles_per_second);
75
76
77
78static cpumask_t uv_target_cpus(void)
79{
80 return cpumask_of_cpu(0);
81}
82
83static cpumask_t uv_vector_allocation_domain(int cpu)
84{
85 cpumask_t domain = CPU_MASK_NONE;
86 cpu_set(cpu, domain);
87 return domain;
88}
89
90int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
91{
92 unsigned long val;
93 int pnode;
94
95 pnode = uv_apicid_to_pnode(phys_apicid);
96 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
97 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
98 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
99 APIC_DM_INIT;
100 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
101 mdelay(10);
102
103 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
104 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
105 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
106 APIC_DM_STARTUP;
107 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
108 return 0;
109}
110
111static void uv_send_IPI_one(int cpu, int vector)
112{
113 unsigned long val, apicid, lapicid;
114 int pnode;
115
116 apicid = per_cpu(x86_cpu_to_apicid, cpu);
117 lapicid = apicid & 0x3f;
118 pnode = uv_apicid_to_pnode(apicid);
119 val =
120 (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
121 UVH_IPI_INT_APIC_ID_SHFT) |
122 (vector << UVH_IPI_INT_VECTOR_SHFT);
123 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
124}
125
126static void uv_send_IPI_mask(cpumask_t mask, int vector)
127{
128 unsigned int cpu;
129
130 for_each_possible_cpu(cpu)
131 if (cpu_isset(cpu, mask))
132 uv_send_IPI_one(cpu, vector);
133}
134
135static void uv_send_IPI_allbutself(int vector)
136{
137 cpumask_t mask = cpu_online_map;
138
139 cpu_clear(smp_processor_id(), mask);
140
141 if (!cpus_empty(mask))
142 uv_send_IPI_mask(mask, vector);
143}
144
145static void uv_send_IPI_all(int vector)
146{
147 uv_send_IPI_mask(cpu_online_map, vector);
148}
149
150static int uv_apic_id_registered(void)
151{
152 return 1;
153}
154
155static void uv_init_apic_ldr(void)
156{
157}
158
159static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
160{
161 int cpu;
162
163
164
165
166
167 cpu = first_cpu(cpumask);
168 if ((unsigned)cpu < nr_cpu_ids)
169 return per_cpu(x86_cpu_to_apicid, cpu);
170 else
171 return BAD_APICID;
172}
173
174static unsigned int get_apic_id(unsigned long x)
175{
176 unsigned int id;
177
178 WARN_ON(preemptible() && num_online_cpus() > 1);
179 id = x | __get_cpu_var(x2apic_extra_bits);
180
181 return id;
182}
183
184static unsigned long set_apic_id(unsigned int id)
185{
186 unsigned long x;
187
188
189 x = id;
190 return x;
191}
192
193static unsigned int uv_read_apic_id(void)
194{
195
196 return get_apic_id(apic_read(APIC_ID));
197}
198
199static unsigned int phys_pkg_id(int index_msb)
200{
201 return uv_read_apic_id() >> index_msb;
202}
203
204static void uv_send_IPI_self(int vector)
205{
206 apic_write(APIC_SELF_IPI, vector);
207}
208
209struct genapic apic_x2apic_uv_x = {
210 .name = "UV large system",
211 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
212 .int_delivery_mode = dest_Fixed,
213 .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
214 .target_cpus = uv_target_cpus,
215 .vector_allocation_domain = uv_vector_allocation_domain,
216 .apic_id_registered = uv_apic_id_registered,
217 .init_apic_ldr = uv_init_apic_ldr,
218 .send_IPI_all = uv_send_IPI_all,
219 .send_IPI_allbutself = uv_send_IPI_allbutself,
220 .send_IPI_mask = uv_send_IPI_mask,
221 .send_IPI_self = uv_send_IPI_self,
222 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
223 .phys_pkg_id = phys_pkg_id,
224 .get_apic_id = get_apic_id,
225 .set_apic_id = set_apic_id,
226 .apic_id_mask = (0xFFFFFFFFu),
227};
228
229static __cpuinit void set_x2apic_extra_bits(int pnode)
230{
231 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
232}
233
234
235
236
237static __init int boot_pnode_to_blade(int pnode)
238{
239 int blade;
240
241 for (blade = 0; blade < uv_num_possible_blades(); blade++)
242 if (pnode == uv_blade_info[blade].pnode)
243 return blade;
244 BUG();
245}
246
247struct redir_addr {
248 unsigned long redirect;
249 unsigned long alias;
250};
251
252#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
253
254static __initdata struct redir_addr redir_addrs[] = {
255 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
256 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
257 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
258};
259
260static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
261{
262 union uvh_si_alias0_overlay_config_u alias;
263 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
264 int i;
265
266 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
267 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
268 if (alias.s.base == 0) {
269 *size = (1UL << alias.s.m_alias);
270 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
271 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
272 return;
273 }
274 }
275 BUG();
276}
277
278static __init void map_low_mmrs(void)
279{
280 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
281 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
282}
283
284enum map_type {map_wb, map_uc};
285
286static __init void map_high(char *id, unsigned long base, int shift,
287 int max_pnode, enum map_type map_type)
288{
289 unsigned long bytes, paddr;
290
291 paddr = base << shift;
292 bytes = (1UL << shift) * (max_pnode + 1);
293 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
294 paddr + bytes);
295 if (map_type == map_uc)
296 init_extra_mapping_uc(paddr, bytes);
297 else
298 init_extra_mapping_wb(paddr, bytes);
299
300}
301static __init void map_gru_high(int max_pnode)
302{
303 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
304 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
305
306 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
307 if (gru.s.enable)
308 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
309}
310
311static __init void map_config_high(int max_pnode)
312{
313 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
314 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
315
316 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
317 if (cfg.s.enable)
318 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
319}
320
321static __init void map_mmr_high(int max_pnode)
322{
323 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
324 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
325
326 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
327 if (mmr.s.enable)
328 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
329}
330
331static __init void map_mmioh_high(int max_pnode)
332{
333 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
334 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
335
336 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
337 if (mmioh.s.enable)
338 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
339}
340
341static __init void uv_rtc_init(void)
342{
343 long status;
344 u64 ticks_per_sec;
345
346 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
347 &ticks_per_sec);
348 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
349 printk(KERN_WARNING
350 "unable to determine platform RTC clock frequency, "
351 "guessing.\n");
352
353 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
354 } else
355 sn_rtc_cycles_per_second = ticks_per_sec;
356}
357
358
359
360
361
362void __cpuinit uv_cpu_init(void)
363{
364
365 if (!uv_blade_info)
366 return;
367
368 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
369
370 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
371 set_x2apic_extra_bits(uv_hub_info->pnode);
372}
373
374
375void __init uv_system_init(void)
376{
377 union uvh_si_addr_map_config_u m_n_config;
378 union uvh_node_id_u node_id;
379 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
380 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
381 int max_pnode = 0;
382 unsigned long mmr_base, present;
383
384 map_low_mmrs();
385
386 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
387 m_val = m_n_config.s.m_skt;
388 n_val = m_n_config.s.n_skt;
389 mmr_base =
390 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
391 ~UV_MMR_ENABLE;
392 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
393
394 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
395 uv_possible_blades +=
396 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
397 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
398
399 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
400 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
401
402 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
403
404 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
405 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
406 memset(uv_node_to_blade, 255, bytes);
407
408 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
409 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
410 memset(uv_cpu_to_blade, 255, bytes);
411
412 blade = 0;
413 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
414 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
415 for (j = 0; j < 64; j++) {
416 if (!test_bit(j, &present))
417 continue;
418 uv_blade_info[blade].pnode = (i * 64 + j);
419 uv_blade_info[blade].nr_possible_cpus = 0;
420 uv_blade_info[blade].nr_online_cpus = 0;
421 blade++;
422 }
423 }
424
425 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
426 gnode_upper = (((unsigned long)node_id.s.node_id) &
427 ~((1 << n_val) - 1)) << m_val;
428
429 uv_bios_init();
430 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
431 &uv_coherency_id, &uv_region_size);
432 uv_rtc_init();
433
434 for_each_present_cpu(cpu) {
435 nid = cpu_to_node(cpu);
436 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
437 blade = boot_pnode_to_blade(pnode);
438 lcpu = uv_blade_info[blade].nr_possible_cpus;
439 uv_blade_info[blade].nr_possible_cpus++;
440
441 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
442 uv_cpu_hub_info(cpu)->lowmem_remap_top =
443 lowmem_redir_base + lowmem_redir_size;
444 uv_cpu_hub_info(cpu)->m_val = m_val;
445 uv_cpu_hub_info(cpu)->n_val = m_val;
446 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
447 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
448 uv_cpu_hub_info(cpu)->pnode = pnode;
449 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
450 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
451 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
452 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
453 uv_cpu_hub_info(cpu)->coherency_domain_number = uv_coherency_id;
454 uv_node_to_blade[nid] = blade;
455 uv_cpu_to_blade[cpu] = blade;
456 max_pnode = max(pnode, max_pnode);
457
458 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
459 "lcpu %d, blade %d\n",
460 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
461 lcpu, blade);
462 }
463
464 map_gru_high(max_pnode);
465 map_mmr_high(max_pnode);
466 map_config_high(max_pnode);
467 map_mmioh_high(max_pnode);
468
469 uv_cpu_init();
470}
471
