LXR linux/arch/x86/include/asm/apic.h

   1#ifndef _ASM_X86_APIC_H
   2#define _ASM_X86_APIC_H
   3
   4#include <linux/pm.h>
   5#include <linux/delay.h>
   6
   7#include <asm/alternative.h>
   8#include <asm/fixmap.h>
   9#include <asm/apicdef.h>
  10#include <asm/processor.h>
  11#include <asm/system.h>
  12#include <asm/cpufeature.h>
  13#include <asm/msr.h>
  14
  15#define ARCH_APICTIMER_STOPS_ON_C3      1
  16
  17/*
  18 * Debugging macros
  19 */
  20#define APIC_QUIET   0
  21#define APIC_VERBOSE 1
  22#define APIC_DEBUG   2
  23
  24/*
  25 * Define the default level of output to be very little
  26 * This can be turned up by using apic=verbose for more
  27 * information and apic=debug for _lots_ of information.
  28 * apic_verbosity is defined in apic.c
  29 */
  30#define apic_printk(v, s, a...) do {       \
  31                if ((v) <= apic_verbosity) \
  32                        printk(s, ##a);    \
  33        } while (0)
  34
  35
  36extern void generic_apic_probe(void);
  37
  38#ifdef CONFIG_X86_LOCAL_APIC
  39
  40extern unsigned int apic_verbosity;
  41extern int local_apic_timer_c2_ok;
  42
  43extern int disable_apic;
  44/*
  45 * Basic functions accessing APICs.
  46 */
  47#ifdef CONFIG_PARAVIRT
  48#include <asm/paravirt.h>
  49#else
  50#define setup_boot_clock setup_boot_APIC_clock
  51#define setup_secondary_clock setup_secondary_APIC_clock
  52#endif
  53
  54extern int is_vsmp_box(void);
  55extern void xapic_wait_icr_idle(void);
  56extern u32 safe_xapic_wait_icr_idle(void);
  57extern u64 xapic_icr_read(void);
  58extern void xapic_icr_write(u32, u32);
  59extern int setup_profiling_timer(unsigned int);
  60
  61static inline void native_apic_mem_write(u32 reg, u32 v)
  62{
  63        volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  64
  65        alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
  66                       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  67                       ASM_OUTPUT2("0" (v), "m" (*addr)));
  68}
  69
  70static inline u32 native_apic_mem_read(u32 reg)
  71{
  72        return *((volatile u32 *)(APIC_BASE + reg));
  73}
  74
  75static inline void native_apic_msr_write(u32 reg, u32 v)
  76{
  77        if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
  78            reg == APIC_LVR)
  79                return;
  80
  81        wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
  82}
  83
  84static inline u32 native_apic_msr_read(u32 reg)
  85{
  86        u32 low, high;
  87
  88        if (reg == APIC_DFR)
  89                return -1;
  90
  91        rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
  92        return low;
  93}
  94
  95#ifndef CONFIG_X86_32
  96extern int x2apic, x2apic_preenabled;
  97extern void check_x2apic(void);
  98extern void enable_x2apic(void);
  99extern void enable_IR_x2apic(void);
 100extern void x2apic_icr_write(u32 low, u32 id);
 101static inline int x2apic_enabled(void)
 102{
 103        int msr, msr2;
 104
 105        if (!cpu_has_x2apic)
 106                return 0;
 107
 108        rdmsr(MSR_IA32_APICBASE, msr, msr2);
 109        if (msr & X2APIC_ENABLE)
 110                return 1;
 111        return 0;
 112}
 113#else
 114#define x2apic_enabled()        0
 115#endif
 116
 117struct apic_ops {
 118        u32 (*read)(u32 reg);
 119        void (*write)(u32 reg, u32 v);
 120        u64 (*icr_read)(void);
 121        void (*icr_write)(u32 low, u32 high);
 122        void (*wait_icr_idle)(void);
 123        u32 (*safe_wait_icr_idle)(void);
 124};
 125
 126extern struct apic_ops *apic_ops;
 127
 128#define apic_read (apic_ops->read)
 129#define apic_write (apic_ops->write)
 130#define apic_icr_read (apic_ops->icr_read)
 131#define apic_icr_write (apic_ops->icr_write)
 132#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
 133#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
 134
 135extern int get_physical_broadcast(void);
 136
 137#ifdef CONFIG_X86_64
 138static inline void ack_x2APIC_irq(void)
 139{
 140        /* Docs say use 0 for future compatibility */
 141        native_apic_msr_write(APIC_EOI, 0);
 142}
 143#endif
 144
 145
 146static inline void ack_APIC_irq(void)
 147{
 148        /*
 149         * ack_APIC_irq() actually gets compiled as a single instruction
 150         * ... yummie.
 151         */
 152
 153        /* Docs say use 0 for future compatibility */
 154        apic_write(APIC_EOI, 0);
 155}
 156
 157extern int lapic_get_maxlvt(void);
 158extern void clear_local_APIC(void);
 159extern void connect_bsp_APIC(void);
 160extern void disconnect_bsp_APIC(int virt_wire_setup);
 161extern void disable_local_APIC(void);
 162extern void lapic_shutdown(void);
 163extern int verify_local_APIC(void);
 164extern void cache_APIC_registers(void);
 165extern void sync_Arb_IDs(void);
 166extern void init_bsp_APIC(void);
 167extern void setup_local_APIC(void);
 168extern void end_local_APIC_setup(void);
 169extern void init_apic_mappings(void);
 170extern void setup_boot_APIC_clock(void);
 171extern void setup_secondary_APIC_clock(void);
 172extern int APIC_init_uniprocessor(void);
 173extern void enable_NMI_through_LVT0(void);
 174
 175/*
 176 * On 32bit this is mach-xxx local
 177 */
 178#ifdef CONFIG_X86_64
 179extern void early_init_lapic_mapping(void);
 180extern int apic_is_clustered_box(void);
 181#else
 182static inline int apic_is_clustered_box(void)
 183{
 184        return 0;
 185}
 186#endif
 187
 188extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 189extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 190
 191
 192#else /* !CONFIG_X86_LOCAL_APIC */
 193static inline void lapic_shutdown(void) { }
 194#define local_apic_timer_c2_ok          1
 195static inline void init_apic_mappings(void) { }
 196
 197#endif /* !CONFIG_X86_LOCAL_APIC */
 198
 199#endif /* _ASM_X86_APIC_H */
 200