1/* 2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. 3 * Author: Joerg Roedel <joerg.roedel@amd.com> 4 * Leo Duran <leo.duran@amd.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#ifndef _ASM_X86_AMD_IOMMU_TYPES_H 21#define _ASM_X86_AMD_IOMMU_TYPES_H 22 23#include <linux/types.h> 24#include <linux/list.h> 25#include <linux/spinlock.h> 26 27/* 28 * some size calculation constants 29 */ 30#define DEV_TABLE_ENTRY_SIZE 32 31#define ALIAS_TABLE_ENTRY_SIZE 2 32#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) 33 34/* Length of the MMIO region for the AMD IOMMU */ 35#define MMIO_REGION_LENGTH 0x4000 36 37/* Capability offsets used by the driver */ 38#define MMIO_CAP_HDR_OFFSET 0x00 39#define MMIO_RANGE_OFFSET 0x0c 40#define MMIO_MISC_OFFSET 0x10 41 42/* Masks, shifts and macros to parse the device range capability */ 43#define MMIO_RANGE_LD_MASK 0xff000000 44#define MMIO_RANGE_FD_MASK 0x00ff0000 45#define MMIO_RANGE_BUS_MASK 0x0000ff00 46#define MMIO_RANGE_LD_SHIFT 24 47#define MMIO_RANGE_FD_SHIFT 16 48#define MMIO_RANGE_BUS_SHIFT 8 49#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) 50#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) 51#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) 52#define MMIO_MSI_NUM(x) ((x) & 0x1f) 53 54/* Flag masks for the AMD IOMMU exclusion range */ 55#define MMIO_EXCL_ENABLE_MASK 0x01ULL 56#define MMIO_EXCL_ALLOW_MASK 0x02ULL 57 58/* Used offsets into the MMIO space */ 59#define MMIO_DEV_TABLE_OFFSET 0x0000 60#define MMIO_CMD_BUF_OFFSET 0x0008 61#define MMIO_EVT_BUF_OFFSET 0x0010 62#define MMIO_CONTROL_OFFSET 0x0018 63#define MMIO_EXCL_BASE_OFFSET 0x0020 64#define MMIO_EXCL_LIMIT_OFFSET 0x0028 65#define MMIO_CMD_HEAD_OFFSET 0x2000 66#define MMIO_CMD_TAIL_OFFSET 0x2008 67#define MMIO_EVT_HEAD_OFFSET 0x2010 68#define MMIO_EVT_TAIL_OFFSET 0x2018 69#define MMIO_STATUS_OFFSET 0x2020 70 71/* MMIO status bits */ 72#define MMIO_STATUS_COM_WAIT_INT_MASK 0x04 73 74/* event logging constants */ 75#define EVENT_ENTRY_SIZE 0x10 76#define EVENT_TYPE_SHIFT 28 77#define EVENT_TYPE_MASK 0xf 78#define EVENT_TYPE_ILL_DEV 0x1 79#define EVENT_TYPE_IO_FAULT 0x2 80#define EVENT_TYPE_DEV_TAB_ERR 0x3 81#define EVENT_TYPE_PAGE_TAB_ERR 0x4 82#define EVENT_TYPE_ILL_CMD 0x5 83#define EVENT_TYPE_CMD_HARD_ERR 0x6 84#define EVENT_TYPE_IOTLB_INV_TO 0x7 85#define EVENT_TYPE_INV_DEV_REQ 0x8 86#define EVENT_DEVID_MASK 0xffff 87#define EVENT_DEVID_SHIFT 0 88#define EVENT_DOMID_MASK 0xffff 89#define EVENT_DOMID_SHIFT 0 90#define EVENT_FLAGS_MASK 0xfff 91#define EVENT_FLAGS_SHIFT 0x10 92 93/* feature control bits */ 94#define CONTROL_IOMMU_EN 0x00ULL 95#define CONTROL_HT_TUN_EN 0x01ULL 96#define CONTROL_EVT_LOG_EN 0x02ULL 97#define CONTROL_EVT_INT_EN 0x03ULL 98#define CONTROL_COMWAIT_EN 0x04ULL 99#define CONTROL_PASSPW_EN 0x08ULL 100#define CONTROL_RESPASSPW_EN 0x09ULL 101#define CONTROL_COHERENT_EN 0x0aULL 102#define CONTROL_ISOC_EN 0x0bULL 103#define CONTROL_CMDBUF_EN 0x0cULL 104#define CONTROL_PPFLOG_EN 0x0dULL 105#define CONTROL_PPFINT_EN 0x0eULL 106 107/* command specific defines */ 108#define CMD_COMPL_WAIT 0x01 109#define CMD_INV_DEV_ENTRY 0x02 110#define CMD_INV_IOMMU_PAGES 0x03 111 112#define CMD_COMPL_WAIT_STORE_MASK 0x01 113#define CMD_COMPL_WAIT_INT_MASK 0x02 114#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 115#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 116 117#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL 118 119/* macros and definitions for device table entries */ 120#define DEV_ENTRY_VALID 0x00 121#define DEV_ENTRY_TRANSLATION 0x01 122#define DEV_ENTRY_IR 0x3d 123#define DEV_ENTRY_IW 0x3e 124#define DEV_ENTRY_NO_PAGE_FAULT 0x62 125#define DEV_ENTRY_EX 0x67 126#define DEV_ENTRY_SYSMGT1 0x68 127#define DEV_ENTRY_SYSMGT2 0x69 128#define DEV_ENTRY_INIT_PASS 0xb8 129#define DEV_ENTRY_EINT_PASS 0xb9 130#define DEV_ENTRY_NMI_PASS 0xba 131#define DEV_ENTRY_LINT0_PASS 0xbe 132#define DEV_ENTRY_LINT1_PASS 0xbf 133#define DEV_ENTRY_MODE_MASK 0x07 134#define DEV_ENTRY_MODE_SHIFT 0x09 135 136/* constants to configure the command buffer */ 137#define CMD_BUFFER_SIZE 8192 138#define CMD_BUFFER_ENTRIES 512 139#define MMIO_CMD_SIZE_SHIFT 56 140#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) 141 142/* constants for event buffer handling */ 143#define EVT_BUFFER_SIZE 8192 /* 512 entries */ 144#define EVT_LEN_MASK (0x9ULL << 56) 145 146#define PAGE_MODE_1_LEVEL 0x01 147#define PAGE_MODE_2_LEVEL 0x02 148#define PAGE_MODE_3_LEVEL 0x03 149 150#define IOMMU_PDE_NL_0 0x000ULL 151#define IOMMU_PDE_NL_1 0x200ULL 152#define IOMMU_PDE_NL_2 0x400ULL 153#define IOMMU_PDE_NL_3 0x600ULL 154 155#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL) 156#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL) 157#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL) 158 159#define IOMMU_MAP_SIZE_L1 (1ULL << 21) 160#define IOMMU_MAP_SIZE_L2 (1ULL << 30) 161#define IOMMU_MAP_SIZE_L3 (1ULL << 39) 162 163#define IOMMU_PTE_P (1ULL << 0) 164#define IOMMU_PTE_TV (1ULL << 1) 165#define IOMMU_PTE_U (1ULL << 59) 166#define IOMMU_PTE_FC (1ULL << 60) 167#define IOMMU_PTE_IR (1ULL << 61) 168#define IOMMU_PTE_IW (1ULL << 62) 169 170#define IOMMU_L1_PDE(address) \ 171 ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) 172#define IOMMU_L2_PDE(address) \ 173 ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) 174 175#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) 176#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) 177#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) 178#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) 179 180#define IOMMU_PROT_MASK 0x03 181#define IOMMU_PROT_IR 0x01 182#define IOMMU_PROT_IW 0x02 183 184/* IOMMU capabilities */ 185#define IOMMU_CAP_IOTLB 24 186#define IOMMU_CAP_NPCACHE 26 187 188#define MAX_DOMAIN_ID 65536 189 190/* FIXME: move this macro to <linux/pci.h> */ 191#define PCI_BUS(x) (((x) >> 8) & 0xff) 192 193/* 194 * This structure contains generic data for IOMMU protection domains 195 * independent of their use. 196 */ 197struct protection_domain { 198 spinlock_t lock; /* mostly used to lock the page table*/ 199 u16 id; /* the domain id written to the device table */ 200 int mode; /* paging mode (0-6 levels) */ 201 u64 *pt_root; /* page table root pointer */ 202 void *priv; /* private data */ 203}; 204 205/* 206 * Data container for a dma_ops specific protection domain 207 */ 208struct dma_ops_domain { 209 struct list_head list; 210 211 /* generic protection domain information */ 212 struct protection_domain domain; 213 214 /* size of the aperture for the mappings */ 215 unsigned long aperture_size; 216 217 /* address we start to search for free addresses */ 218 unsigned long next_bit; 219 220 /* address allocation bitmap */ 221 unsigned long *bitmap; 222 223 /* 224 * Array of PTE pages for the aperture. In this array we save all the 225 * leaf pages of the domain page table used for the aperture. This way 226 * we don't need to walk the page table to find a specific PTE. We can 227 * just calculate its address in constant time. 228 */ 229 u64 **pte_pages; 230 231 /* This will be set to true when TLB needs to be flushed */ 232 bool need_flush; 233 234 /* 235 * if this is a preallocated domain, keep the device for which it was 236 * preallocated in this variable 237 */ 238 u16 target_dev; 239}; 240 241/* 242 * Structure where we save information about one hardware AMD IOMMU in the 243 * system. 244 */ 245struct amd_iommu { 246 struct list_head list; 247 248 /* locks the accesses to the hardware */ 249 spinlock_t lock; 250 251 /* Pointer to PCI device of this IOMMU */ 252 struct pci_dev *dev; 253 254 /* physical address of MMIO space */ 255 u64 mmio_phys; 256 /* virtual address of MMIO space */ 257 u8 *mmio_base; 258 259 /* capabilities of that IOMMU read from ACPI */ 260 u32 cap; 261 262 /* 263 * Capability pointer. There could be more than one IOMMU per PCI 264 * device function if there are more than one AMD IOMMU capability 265 * pointers. 266 */ 267 u16 cap_ptr; 268 269 /* pci domain of this IOMMU */ 270 u16 pci_seg; 271 272 /* first device this IOMMU handles. read from PCI */ 273 u16 first_device; 274 /* last device this IOMMU handles. read from PCI */ 275 u16 last_device; 276 277 /* start of exclusion range of that IOMMU */ 278 u64 exclusion_start; 279 /* length of exclusion range of that IOMMU */ 280 u64 exclusion_length; 281 282 /* command buffer virtual address */ 283 u8 *cmd_buf; 284 /* size of command buffer */ 285 u32 cmd_buf_size; 286 287 /* size of event buffer */ 288 u32 evt_buf_size; 289 /* event buffer virtual address */ 290 u8 *evt_buf; 291 /* MSI number for event interrupt */ 292 u16 evt_msi_num; 293 294 /* true if interrupts for this IOMMU are already enabled */ 295 bool int_enabled; 296 297 /* if one, we need to send a completion wait command */ 298 int need_sync; 299 300 /* default dma_ops domain for that IOMMU */ 301 struct dma_ops_domain *default_dom; 302}; 303 304/* 305 * List with all IOMMUs in the system. This list is not locked because it is 306 * only written and read at driver initialization or suspend time 307 */ 308extern struct list_head amd_iommu_list; 309 310/* 311 * Structure defining one entry in the device table 312 */ 313struct dev_table_entry { 314 u32 data[8]; 315}; 316 317/* 318 * One entry for unity mappings parsed out of the ACPI table. 319 */ 320struct unity_map_entry { 321 struct list_head list; 322 323 /* starting device id this entry is used for (including) */ 324 u16 devid_start; 325 /* end device id this entry is used for (including) */ 326 u16 devid_end; 327 328 /* start address to unity map (including) */ 329 u64 address_start; 330 /* end address to unity map (including) */ 331 u64 address_end; 332 333 /* required protection */ 334 int prot; 335}; 336 337/* 338 * List of all unity mappings. It is not locked because as runtime it is only 339 * read. It is created at ACPI table parsing time. 340 */ 341extern struct list_head amd_iommu_unity_map; 342 343/* 344 * Data structures for device handling 345 */ 346 347/* 348 * Device table used by hardware. Read and write accesses by software are 349 * locked with the amd_iommu_pd_table lock. 350 */ 351extern struct dev_table_entry *amd_iommu_dev_table; 352 353/* 354 * Alias table to find requestor ids to device ids. Not locked because only 355 * read on runtime. 356 */ 357extern u16 *amd_iommu_alias_table; 358 359/* 360 * Reverse lookup table to find the IOMMU which translates a specific device. 361 */ 362extern struct amd_iommu **amd_iommu_rlookup_table; 363 364/* size of the dma_ops aperture as power of 2 */ 365extern unsigned amd_iommu_aperture_order; 366 367/* largest PCI device id we expect translation requests for */ 368extern u16 amd_iommu_last_bdf; 369 370/* data structures for protection domain handling */ 371extern struct protection_domain **amd_iommu_pd_table; 372 373/* allocation bitmap for domain ids */ 374extern unsigned long *amd_iommu_pd_alloc_bitmap; 375 376/* will be 1 if device isolation is enabled */ 377extern int amd_iommu_isolate; 378 379/* 380 * If true, the addresses will be flushed on unmap time, not when 381 * they are reused 382 */ 383extern bool amd_iommu_unmap_flush; 384 385/* takes a PCI device id and prints it out in a readable form */ 386static inline void print_devid(u16 devid, int nl) 387{ 388 int bus = devid >> 8; 389 int dev = devid >> 3 & 0x1f; 390 int fn = devid & 0x07; 391 392 printk("%02x:%02x.%x", bus, dev, fn); 393 if (nl) 394 printk("\n"); 395} 396 397/* takes bus and device/function and returns the device id 398 * FIXME: should that be in generic PCI code? */ 399static inline u16 calc_devid(u8 bus, u8 devfn) 400{ 401 return (((u16)bus) << 8) | devfn; 402} 403 404#endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ 405