LXR linux/arch/powerpc/include/asm/cputable.h

   1#ifndef __ASM_POWERPC_CPUTABLE_H
   2#define __ASM_POWERPC_CPUTABLE_H
   3
   4#define PPC_FEATURE_32                  0x80000000
   5#define PPC_FEATURE_64                  0x40000000
   6#define PPC_FEATURE_601_INSTR           0x20000000
   7#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
   8#define PPC_FEATURE_HAS_FPU             0x08000000
   9#define PPC_FEATURE_HAS_MMU             0x04000000
  10#define PPC_FEATURE_HAS_4xxMAC          0x02000000
  11#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  12#define PPC_FEATURE_HAS_SPE             0x00800000
  13#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
  14#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
  15#define PPC_FEATURE_NO_TB               0x00100000
  16#define PPC_FEATURE_POWER4              0x00080000
  17#define PPC_FEATURE_POWER5              0x00040000
  18#define PPC_FEATURE_POWER5_PLUS         0x00020000
  19#define PPC_FEATURE_CELL                0x00010000
  20#define PPC_FEATURE_BOOKE               0x00008000
  21#define PPC_FEATURE_SMT                 0x00004000
  22#define PPC_FEATURE_ICACHE_SNOOP        0x00002000
  23#define PPC_FEATURE_ARCH_2_05           0x00001000
  24#define PPC_FEATURE_PA6T                0x00000800
  25#define PPC_FEATURE_HAS_DFP             0x00000400
  26#define PPC_FEATURE_POWER6_EXT          0x00000200
  27#define PPC_FEATURE_ARCH_2_06           0x00000100
  28#define PPC_FEATURE_HAS_VSX             0x00000080
  29
  30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
  31                                        0x00000040
  32
  33#define PPC_FEATURE_TRUE_LE             0x00000002
  34#define PPC_FEATURE_PPC_LE              0x00000001
  35
  36#ifdef __KERNEL__
  37
  38#include <asm/asm-compat.h>
  39#include <asm/feature-fixups.h>
  40
  41#ifndef __ASSEMBLY__
  42
  43/* This structure can grow, it's real size is used by head.S code
  44 * via the mkdefs mechanism.
  45 */
  46struct cpu_spec;
  47
  48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  49typedef void (*cpu_restore_t)(void);
  50
  51enum powerpc_oprofile_type {
  52        PPC_OPROFILE_INVALID = 0,
  53        PPC_OPROFILE_RS64 = 1,
  54        PPC_OPROFILE_POWER4 = 2,
  55        PPC_OPROFILE_G4 = 3,
  56        PPC_OPROFILE_FSL_EMB = 4,
  57        PPC_OPROFILE_CELL = 5,
  58        PPC_OPROFILE_PA6T = 6,
  59};
  60
  61enum powerpc_pmc_type {
  62        PPC_PMC_DEFAULT = 0,
  63        PPC_PMC_IBM = 1,
  64        PPC_PMC_PA6T = 2,
  65        PPC_PMC_G4 = 3,
  66};
  67
  68struct pt_regs;
  69
  70extern int machine_check_generic(struct pt_regs *regs);
  71extern int machine_check_4xx(struct pt_regs *regs);
  72extern int machine_check_440A(struct pt_regs *regs);
  73extern int machine_check_e500(struct pt_regs *regs);
  74extern int machine_check_e200(struct pt_regs *regs);
  75
  76/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  77struct cpu_spec {
  78        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  79        unsigned int    pvr_mask;
  80        unsigned int    pvr_value;
  81
  82        char            *cpu_name;
  83        unsigned long   cpu_features;           /* Kernel features */
  84        unsigned int    cpu_user_features;      /* Userland features */
  85
  86        /* cache line sizes */
  87        unsigned int    icache_bsize;
  88        unsigned int    dcache_bsize;
  89
  90        /* number of performance monitor counters */
  91        unsigned int    num_pmcs;
  92        enum powerpc_pmc_type pmc_type;
  93
  94        /* this is called to initialize various CPU bits like L1 cache,
  95         * BHT, SPD, etc... from head.S before branching to identify_machine
  96         */
  97        cpu_setup_t     cpu_setup;
  98        /* Used to restore cpu setup on secondary processors and at resume */
  99        cpu_restore_t   cpu_restore;
 100
 101        /* Used by oprofile userspace to select the right counters */
 102        char            *oprofile_cpu_type;
 103
 104        /* Processor specific oprofile operations */
 105        enum powerpc_oprofile_type oprofile_type;
 106
 107        /* Bit locations inside the mmcra change */
 108        unsigned long   oprofile_mmcra_sihv;
 109        unsigned long   oprofile_mmcra_sipr;
 110
 111        /* Bits to clear during an oprofile exception */
 112        unsigned long   oprofile_mmcra_clear;
 113
 114        /* Name of processor class, for the ELF AT_PLATFORM entry */
 115        char            *platform;
 116
 117        /* Processor specific machine check handling. Return negative
 118         * if the error is fatal, 1 if it was fully recovered and 0 to
 119         * pass up (not CPU originated) */
 120        int             (*machine_check)(struct pt_regs *regs);
 121};
 122
 123extern struct cpu_spec          *cur_cpu_spec;
 124
 125extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
 126
 127extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 128extern void do_feature_fixups(unsigned long value, void *fixup_start,
 129                              void *fixup_end);
 130
 131extern const char *powerpc_base_platform;
 132
 133#endif /* __ASSEMBLY__ */
 134
 135/* CPU kernel features */
 136
 137/* Retain the 32b definitions all use bottom half of word */
 138#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000000000000001)
 139#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
 140#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
 141#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
 142#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
 143#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
 144#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
 145#define CPU_FTR_L2CSR                   ASM_CONST(0x0000000000000080)
 146#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
 147#define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
 148#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
 149#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
 150#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
 151#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
 152#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
 153#define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
 154#define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
 155#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
 156#define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
 157#define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
 158#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 159#define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 160#define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
 161#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
 162#define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
 163#define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
 164#define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
 165#define CPU_FTR_LWSYNC                  ASM_CONST(0x0000000008000000)
 166
 167/*
 168 * Add the 64-bit processor unique features in the top half of the word;
 169 * on 32-bit, make the names available but defined to be 0.
 170 */
 171#ifdef __powerpc64__
 172#define LONG_ASM_CONST(x)               ASM_CONST(x)
 173#else
 174#define LONG_ASM_CONST(x)               0
 175#endif
 176
 177#define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
 178#define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
 179#define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
 180#define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
 181#define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
 182#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
 183#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
 184#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
 185#define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
 186#define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
 187#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
 188#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 189#define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
 190#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 191#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
 192#define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
 193#define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
 194#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0010000000000000)
 195#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0020000000000000)
 196#define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0040000000000000)
 197
 198#ifndef __ASSEMBLY__
 199
 200#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
 201                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
 202                                 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
 203
 204/* We only set the altivec features if the kernel was compiled with altivec
 205 * support
 206 */
 207#ifdef CONFIG_ALTIVEC
 208#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 209#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 210#else
 211#define CPU_FTR_ALTIVEC_COMP    0
 212#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 213#endif
 214
 215/* We only set the VSX features if the kernel was compiled with VSX
 216 * support
 217 */
 218#ifdef CONFIG_VSX
 219#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
 220#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
 221#else
 222#define CPU_FTR_VSX_COMP        0
 223#define PPC_FEATURE_HAS_VSX_COMP    0
 224#endif
 225
 226/* We only set the spe features if the kernel was compiled with spe
 227 * support
 228 */
 229#ifdef CONFIG_SPE
 230#define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 231#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 232#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 233#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 234#else
 235#define CPU_FTR_SPE_COMP        0
 236#define PPC_FEATURE_HAS_SPE_COMP    0
 237#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 238#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 239#endif
 240
 241/* We need to mark all pages as being coherent if we're SMP or we have a
 242 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 243 * require it for PCI "streaming/prefetch" to work properly.
 244 */
 245#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 246        || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
 247#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 248#else
 249#define CPU_FTR_COMMON                  0
 250#endif
 251
 252/* The powersave features NAP & DOZE seems to confuse BDI when
 253   debugging. So if a BDI is used, disable theses
 254 */
 255#ifndef CONFIG_BDI_SWITCH
 256#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 257#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 258#else
 259#define CPU_FTR_MAYBE_CAN_DOZE  0
 260#define CPU_FTR_MAYBE_CAN_NAP   0
 261#endif
 262
 263#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 264                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 265                     !defined(CONFIG_BOOKE))
 266
 267#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
 268        CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 269#define CPU_FTRS_603    (CPU_FTR_COMMON | \
 270            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 271            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 272#define CPU_FTRS_604    (CPU_FTR_COMMON | \
 273            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
 274#define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 275            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 276            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 277#define CPU_FTRS_740    (CPU_FTR_COMMON | \
 278            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 279            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 280            CPU_FTR_PPC_LE)
 281#define CPU_FTRS_750    (CPU_FTR_COMMON | \
 282            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 283            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 284            CPU_FTR_PPC_LE)
 285#define CPU_FTRS_750CL  (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
 286#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 287#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 288#define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
 289                CPU_FTR_HAS_HIGH_BATS)
 290#define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 291#define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 292            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 293            CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 294            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 295#define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 296            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 297            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 298            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 299#define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 300            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 301            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 302            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 303#define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 304            CPU_FTR_USE_TB | \
 305            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 306            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 307            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 308            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 309#define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 310            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 311            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 312            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 313            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 314#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 315            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 316            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 317            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
 318            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 319#define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 320            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 321            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 322            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 323            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 324            CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 325#define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 326            CPU_FTR_USE_TB | \
 327            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 328            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 329            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 330            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 331#define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 332            CPU_FTR_USE_TB | \
 333            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 334            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 335            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 336            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 337            CPU_FTR_NEED_PAIRED_STWCX)
 338#define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 339            CPU_FTR_USE_TB | \
 340            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 341            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 342            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 343            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 344#define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 345            CPU_FTR_USE_TB | \
 346            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 347            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 348            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 349            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 350#define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 351            CPU_FTR_USE_TB | \
 352            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 353            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 354            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 355            CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 356#define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 357            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 358#define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 359            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
 360#define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 361            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
 362            CPU_FTR_COMMON)
 363#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 364            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
 365            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 366#define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | \
 367            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
 368#define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
 369#define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
 370#define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
 371#define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 372            CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 373            CPU_FTR_UNIFIED_ID_CACHE)
 374#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 375            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
 376#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 377            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
 378            CPU_FTR_NODSISRALIGN)
 379#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 380            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
 381            CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
 382#define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 383
 384/* 64-bit CPUs */
 385#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 386            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
 387#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 388            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
 389            CPU_FTR_MMCRA | CPU_FTR_CTRL)
 390#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 391            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 392            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)
 393#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 394            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 395            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
 396            CPU_FTR_CP_USE_DCBTZ)
 397#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 398            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 399            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 400            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 401            CPU_FTR_PURR)
 402#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 403            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 404            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 405            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 406            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 407            CPU_FTR_DSCR)
 408#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 409            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 410            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 411            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 412            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 413            CPU_FTR_DSCR | CPU_FTR_SAO)
 414#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 415            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 416            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 417            CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
 418            CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ)
 419#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 420            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
 421            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
 422            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
 423#define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | \
 424            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
 425
 426#ifdef __powerpc64__
 427#define CPU_FTRS_POSSIBLE       \
 428            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
 429            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
 430            CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
 431            CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
 432#else
 433enum {
 434        CPU_FTRS_POSSIBLE =
 435#if CLASSIC_PPC
 436            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 437            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 438            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 439            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 440            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 441            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 442            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 443            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 444            CPU_FTRS_CLASSIC32 |
 445#else
 446            CPU_FTRS_GENERIC_32 |
 447#endif
 448#ifdef CONFIG_8xx
 449            CPU_FTRS_8XX |
 450#endif
 451#ifdef CONFIG_40x
 452            CPU_FTRS_40X |
 453#endif
 454#ifdef CONFIG_44x
 455            CPU_FTRS_44X |
 456#endif
 457#ifdef CONFIG_E200
 458            CPU_FTRS_E200 |
 459#endif
 460#ifdef CONFIG_E500
 461            CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
 462#endif
 463            0,
 464};
 465#endif /* __powerpc64__ */
 466
 467#ifdef __powerpc64__
 468#define CPU_FTRS_ALWAYS         \
 469            (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
 470            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
 471            CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 472#else
 473enum {
 474        CPU_FTRS_ALWAYS =
 475#if CLASSIC_PPC
 476            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 477            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 478            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 479            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 480            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 481            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 482            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 483            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 484            CPU_FTRS_CLASSIC32 &
 485#else
 486            CPU_FTRS_GENERIC_32 &
 487#endif
 488#ifdef CONFIG_8xx
 489            CPU_FTRS_8XX &
 490#endif
 491#ifdef CONFIG_40x
 492            CPU_FTRS_40X &
 493#endif
 494#ifdef CONFIG_44x
 495            CPU_FTRS_44X &
 496#endif
 497#ifdef CONFIG_E200
 498            CPU_FTRS_E200 &
 499#endif
 500#ifdef CONFIG_E500
 501            CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
 502#endif
 503            CPU_FTRS_POSSIBLE,
 504};
 505#endif /* __powerpc64__ */
 506
 507static inline int cpu_has_feature(unsigned long feature)
 508{
 509        return (CPU_FTRS_ALWAYS & feature) ||
 510               (CPU_FTRS_POSSIBLE
 511                & cur_cpu_spec->cpu_features
 512                & feature);
 513}
 514
 515#endif /* !__ASSEMBLY__ */
 516
 517#endif /* __KERNEL__ */
 518#endif /* __ASM_POWERPC_CPUTABLE_H */
 519