1/* arch/arm/mach-s3c2410/include/mach/regs-serial.h 2 * 3 * From linux/include/asm-arm/hardware/serial_s3c2410.h 4 * 5 * Internal header file for Samsung S3C2410 serial ports (UART0-2) 6 * 7 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 8 * 9 * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk) 10 * 11 * Adapted from: 12 * 13 * Internal header file for MX1ADS serial ports (UART1 & 2) 14 * 15 * Copyright (C) 2002 Shane Nay (shane@minirl.com) 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2 of the License, or 20 * (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 30*/ 31 32#ifndef __ASM_ARM_REGS_SERIAL_H 33#define __ASM_ARM_REGS_SERIAL_H 34 35#define S3C24XX_VA_UART0 (S3C_VA_UART) 36#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) 37#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) 38#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) 39 40#define S3C2410_PA_UART0 (S3C24XX_PA_UART) 41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) 42#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) 43#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) 44 45#define S3C2410_URXH (0x24) 46#define S3C2410_UTXH (0x20) 47#define S3C2410_ULCON (0x00) 48#define S3C2410_UCON (0x04) 49#define S3C2410_UFCON (0x08) 50#define S3C2410_UMCON (0x0C) 51#define S3C2410_UBRDIV (0x28) 52#define S3C2410_UTRSTAT (0x10) 53#define S3C2410_UERSTAT (0x14) 54#define S3C2410_UFSTAT (0x18) 55#define S3C2410_UMSTAT (0x1C) 56 57#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) 58 59#define S3C2410_LCON_CS5 (0x0) 60#define S3C2410_LCON_CS6 (0x1) 61#define S3C2410_LCON_CS7 (0x2) 62#define S3C2410_LCON_CS8 (0x3) 63#define S3C2410_LCON_CSMASK (0x3) 64 65#define S3C2410_LCON_PNONE (0x0) 66#define S3C2410_LCON_PEVEN (0x5 << 3) 67#define S3C2410_LCON_PODD (0x4 << 3) 68#define S3C2410_LCON_PMASK (0x7 << 3) 69 70#define S3C2410_LCON_STOPB (1<<2) 71#define S3C2410_LCON_IRM (1<<6) 72 73#define S3C2440_UCON_CLKMASK (3<<10) 74#define S3C2440_UCON_PCLK (0<<10) 75#define S3C2440_UCON_UCLK (1<<10) 76#define S3C2440_UCON_PCLK2 (2<<10) 77#define S3C2440_UCON_FCLK (3<<10) 78#define S3C2443_UCON_EPLL (3<<10) 79 80#define S3C2440_UCON2_FCLK_EN (1<<15) 81#define S3C2440_UCON0_DIVMASK (15 << 12) 82#define S3C2440_UCON1_DIVMASK (15 << 12) 83#define S3C2440_UCON2_DIVMASK (7 << 12) 84#define S3C2440_UCON_DIVSHIFT (12) 85 86#define S3C2412_UCON_CLKMASK (3<<10) 87#define S3C2412_UCON_UCLK (1<<10) 88#define S3C2412_UCON_USYSCLK (3<<10) 89#define S3C2412_UCON_PCLK (0<<10) 90#define S3C2412_UCON_PCLK2 (2<<10) 91 92#define S3C2410_UCON_UCLK (1<<10) 93#define S3C2410_UCON_SBREAK (1<<4) 94 95#define S3C2410_UCON_TXILEVEL (1<<9) 96#define S3C2410_UCON_RXILEVEL (1<<8) 97#define S3C2410_UCON_TXIRQMODE (1<<2) 98#define S3C2410_UCON_RXIRQMODE (1<<0) 99#define S3C2410_UCON_RXFIFO_TOI (1<<7) 100#define S3C2443_UCON_RXERR_IRQEN (1<<6) 101#define S3C2443_UCON_LOOPBACK (1<<5) 102 103#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 104 S3C2410_UCON_RXILEVEL | \ 105 S3C2410_UCON_TXIRQMODE | \ 106 S3C2410_UCON_RXIRQMODE | \ 107 S3C2410_UCON_RXFIFO_TOI) 108 109#define S3C2410_UFCON_FIFOMODE (1<<0) 110#define S3C2410_UFCON_TXTRIG0 (0<<6) 111#define S3C2410_UFCON_RXTRIG8 (1<<4) 112#define S3C2410_UFCON_RXTRIG12 (2<<4) 113 114/* S3C2440 FIFO trigger levels */ 115#define S3C2440_UFCON_RXTRIG1 (0<<4) 116#define S3C2440_UFCON_RXTRIG8 (1<<4) 117#define S3C2440_UFCON_RXTRIG16 (2<<4) 118#define S3C2440_UFCON_RXTRIG32 (3<<4) 119 120#define S3C2440_UFCON_TXTRIG0 (0<<6) 121#define S3C2440_UFCON_TXTRIG16 (1<<6) 122#define S3C2440_UFCON_TXTRIG32 (2<<6) 123#define S3C2440_UFCON_TXTRIG48 (3<<6) 124 125#define S3C2410_UFCON_RESETBOTH (3<<1) 126#define S3C2410_UFCON_RESETTX (1<<2) 127#define S3C2410_UFCON_RESETRX (1<<1) 128 129#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 130 S3C2410_UFCON_TXTRIG0 | \ 131 S3C2410_UFCON_RXTRIG8 ) 132 133#define S3C2410_UMCOM_AFC (1<<4) 134#define S3C2410_UMCOM_RTS_LOW (1<<0) 135 136#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ 137#define S3C2412_UMCON_AFC_56 (1<<5) 138#define S3C2412_UMCON_AFC_48 (2<<5) 139#define S3C2412_UMCON_AFC_40 (3<<5) 140#define S3C2412_UMCON_AFC_32 (4<<5) 141#define S3C2412_UMCON_AFC_24 (5<<5) 142#define S3C2412_UMCON_AFC_16 (6<<5) 143#define S3C2412_UMCON_AFC_8 (7<<5) 144 145#define S3C2410_UFSTAT_TXFULL (1<<9) 146#define S3C2410_UFSTAT_RXFULL (1<<8) 147#define S3C2410_UFSTAT_TXMASK (15<<4) 148#define S3C2410_UFSTAT_TXSHIFT (4) 149#define S3C2410_UFSTAT_RXMASK (15<<0) 150#define S3C2410_UFSTAT_RXSHIFT (0) 151 152/* UFSTAT S3C2443 same as S3C2440 */ 153#define S3C2440_UFSTAT_TXFULL (1<<14) 154#define S3C2440_UFSTAT_RXFULL (1<<6) 155#define S3C2440_UFSTAT_TXSHIFT (8) 156#define S3C2440_UFSTAT_RXSHIFT (0) 157#define S3C2440_UFSTAT_TXMASK (63<<8) 158#define S3C2440_UFSTAT_RXMASK (63) 159 160#define S3C2410_UTRSTAT_TXE (1<<2) 161#define S3C2410_UTRSTAT_TXFE (1<<1) 162#define S3C2410_UTRSTAT_RXDR (1<<0) 163 164#define S3C2410_UERSTAT_OVERRUN (1<<0) 165#define S3C2410_UERSTAT_FRAME (1<<2) 166#define S3C2410_UERSTAT_BREAK (1<<3) 167#define S3C2443_UERSTAT_PARITY (1<<1) 168 169#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ 170 S3C2410_UERSTAT_FRAME | \ 171 S3C2410_UERSTAT_BREAK) 172 173#define S3C2410_UMSTAT_CTS (1<<0) 174#define S3C2410_UMSTAT_DeltaCTS (1<<2) 175 176#define S3C2443_DIVSLOT (0x2C) 177 178#ifndef __ASSEMBLY__ 179 180/* struct s3c24xx_uart_clksrc 181 * 182 * this structure defines a named clock source that can be used for the 183 * uart, so that the best clock can be selected for the requested baud 184 * rate. 185 * 186 * min_baud and max_baud define the range of baud-rates this clock is 187 * acceptable for, if they are both zero, it is assumed any baud rate that 188 * can be generated from this clock will be used. 189 * 190 * divisor gives the divisor from the clock to the one seen by the uart 191*/ 192 193struct s3c24xx_uart_clksrc { 194 const char *name; 195 unsigned int divisor; 196 unsigned int min_baud; 197 unsigned int max_baud; 198}; 199 200/* configuration structure for per-machine configurations for the 201 * serial port 202 * 203 * the pointer is setup by the machine specific initialisation from the 204 * arch/arm/mach-s3c2410/ directory. 205*/ 206 207struct s3c2410_uartcfg { 208 unsigned char hwport; /* hardware port number */ 209 unsigned char unused; 210 unsigned short flags; 211 upf_t uart_flags; /* default uart flags */ 212 213 unsigned long ucon; /* value of ucon for port */ 214 unsigned long ulcon; /* value of ulcon for port */ 215 unsigned long ufcon; /* value of ufcon for port */ 216 217 struct s3c24xx_uart_clksrc *clocks; 218 unsigned int clocks_size; 219}; 220 221/* s3c24xx_uart_devs 222 * 223 * this is exported from the core as we cannot use driver_register(), 224 * or platform_add_device() before the console_initcall() 225*/ 226 227extern struct platform_device *s3c24xx_uart_devs[3]; 228 229#endif /* __ASSEMBLY__ */ 230 231#endif /* __ASM_ARM_REGS_SERIAL_H */ 232 233