1/* arch/arm/mach-s3c2410/include/mach/irqs.h 2 * 3 * Copyright (c) 2003-2005 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9*/ 10 11 12#ifndef __ASM_ARCH_IRQS_H 13#define __ASM_ARCH_IRQS_H __FILE__ 14 15#ifndef __ASM_ARM_IRQ_H 16#error "Do not include this directly, instead #include <asm/irq.h>" 17#endif 18 19/* we keep the first set of CPU IRQs out of the range of 20 * the ISA space, so that the PC104 has them to itself 21 * and we don't end up having to do horrible things to the 22 * standard ISA drivers.... 23 */ 24 25#define S3C2410_CPUIRQ_OFFSET (16) 26 27#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) 28 29/* main cpu interrupts */ 30#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ 31#define IRQ_EINT1 S3C2410_IRQ(1) 32#define IRQ_EINT2 S3C2410_IRQ(2) 33#define IRQ_EINT3 S3C2410_IRQ(3) 34#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ 35#define IRQ_EINT8t23 S3C2410_IRQ(5) 36#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ 37#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ 38#define IRQ_BATT_FLT S3C2410_IRQ(7) 39#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ 40#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ 41#define IRQ_TIMER0 S3C2410_IRQ(10) 42#define IRQ_TIMER1 S3C2410_IRQ(11) 43#define IRQ_TIMER2 S3C2410_IRQ(12) 44#define IRQ_TIMER3 S3C2410_IRQ(13) 45#define IRQ_TIMER4 S3C2410_IRQ(14) 46#define IRQ_UART2 S3C2410_IRQ(15) 47#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ 48#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ 49#define IRQ_DMA1 S3C2410_IRQ(18) 50#define IRQ_DMA2 S3C2410_IRQ(19) 51#define IRQ_DMA3 S3C2410_IRQ(20) 52#define IRQ_SDI S3C2410_IRQ(21) 53#define IRQ_SPI0 S3C2410_IRQ(22) 54#define IRQ_UART1 S3C2410_IRQ(23) 55#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ 56#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ 57#define IRQ_USBD S3C2410_IRQ(25) 58#define IRQ_USBH S3C2410_IRQ(26) 59#define IRQ_IIC S3C2410_IRQ(27) 60#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ 61#define IRQ_SPI1 S3C2410_IRQ(29) 62#define IRQ_RTC S3C2410_IRQ(30) 63#define IRQ_ADCPARENT S3C2410_IRQ(31) 64 65/* interrupts generated from the external interrupts sources */ 66#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ 67#define IRQ_EINT5 S3C2410_IRQ(33) 68#define IRQ_EINT6 S3C2410_IRQ(34) 69#define IRQ_EINT7 S3C2410_IRQ(35) 70#define IRQ_EINT8 S3C2410_IRQ(36) 71#define IRQ_EINT9 S3C2410_IRQ(37) 72#define IRQ_EINT10 S3C2410_IRQ(38) 73#define IRQ_EINT11 S3C2410_IRQ(39) 74#define IRQ_EINT12 S3C2410_IRQ(40) 75#define IRQ_EINT13 S3C2410_IRQ(41) 76#define IRQ_EINT14 S3C2410_IRQ(42) 77#define IRQ_EINT15 S3C2410_IRQ(43) 78#define IRQ_EINT16 S3C2410_IRQ(44) 79#define IRQ_EINT17 S3C2410_IRQ(45) 80#define IRQ_EINT18 S3C2410_IRQ(46) 81#define IRQ_EINT19 S3C2410_IRQ(47) 82#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ 83#define IRQ_EINT21 S3C2410_IRQ(49) 84#define IRQ_EINT22 S3C2410_IRQ(50) 85#define IRQ_EINT23 S3C2410_IRQ(51) 86 87 88#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) 89 90#define IRQ_LCD_FIFO S3C2410_IRQ(52) 91#define IRQ_LCD_FRAME S3C2410_IRQ(53) 92 93/* IRQs for the interal UARTs, and ADC 94 * these need to be ordered in number of appearance in the 95 * SUBSRC mask register 96*/ 97 98#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) 99 100#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ 101#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) 102#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) 103 104#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ 105#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) 106#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) 107 108#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ 109#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) 110#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) 111 112#define IRQ_TC S3C2410_IRQSUB(9) 113#define IRQ_ADC S3C2410_IRQSUB(10) 114 115/* extra irqs for s3c2412 */ 116 117#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) 118 119#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) 120#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) 121 122/* extra irqs for s3c2440 */ 123 124#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ 125#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ 126#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) 127#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) 128 129/* irqs for s3c2443 */ 130 131#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ 132#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ 133#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ 134#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ 135#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ 136 137#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) 138#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) 139#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) 140#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) 141 142#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) 143#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) 144#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) 145#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) 146#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) 147#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) 148 149/* UART3 */ 150#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) 151#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) 152#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) 153 154#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) 155#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) 156 157#ifdef CONFIG_CPU_S3C2443 158#define NR_IRQS (IRQ_S3C2443_AC97+1) 159#else 160#define NR_IRQS (IRQ_S3C2440_AC97+1) 161#endif 162 163/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ 164#define FIQ_START IRQ_EINT0 165 166#endif /* __ASM_ARCH_IRQ_H */ 167
