1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/wait.h>
18#include <linux/clk.h>
19#include <linux/delay.h>
20
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/ac97_codec.h>
24#include <sound/initval.h>
25#include <sound/soc.h>
26
27#include <asm/irq.h>
28#include <linux/mutex.h>
29#include <asm/hardware.h>
30#include <asm/arch/pxa-regs.h>
31#include <asm/arch/pxa2xx-gpio.h>
32#include <asm/arch/audio.h>
33
34#include "pxa2xx-pcm.h"
35#include "pxa2xx-ac97.h"
36
37static DEFINE_MUTEX(car_mutex);
38static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
39static volatile long gsr_bits;
40static struct clk *ac97_clk;
41#ifdef CONFIG_PXA27x
42static struct clk *ac97conf_clk;
43#endif
44
45
46
47
48
49
50
51
52
53
54
55static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97,
56 unsigned short reg)
57{
58 unsigned short val = -1;
59 volatile u32 *reg_addr;
60
61 mutex_lock(&car_mutex);
62
63
64#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
65 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
66#else
67 if (reg == AC97_GPIO_STATUS)
68 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
69 else
70 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
71#endif
72 reg_addr += (reg >> 1);
73
74#ifndef CONFIG_PXA27x
75 if (reg == AC97_GPIO_STATUS) {
76
77 val = *reg_addr;
78 goto out;
79 }
80#endif
81
82
83 GSR = GSR_CDONE | GSR_SDONE;
84 gsr_bits = 0;
85 val = *reg_addr;
86
87 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
88 if (!((GSR | gsr_bits) & GSR_SDONE)) {
89 printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n",
90 __func__, reg, GSR | gsr_bits);
91 val = -1;
92 goto out;
93 }
94
95
96 GSR = GSR_CDONE | GSR_SDONE;
97 gsr_bits = 0;
98 val = *reg_addr;
99
100 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
101
102out: mutex_unlock(&car_mutex);
103 return val;
104}
105
106static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
107 unsigned short val)
108{
109 volatile u32 *reg_addr;
110
111 mutex_lock(&car_mutex);
112
113
114#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
115 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
116#else
117 if (reg == AC97_GPIO_STATUS)
118 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
119 else
120 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
121#endif
122 reg_addr += (reg >> 1);
123
124 GSR = GSR_CDONE | GSR_SDONE;
125 gsr_bits = 0;
126 *reg_addr = val;
127 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1);
128 if (!((GSR | gsr_bits) & GSR_CDONE))
129 printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n",
130 __func__, reg, GSR | gsr_bits);
131
132 mutex_unlock(&car_mutex);
133}
134
135static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
136{
137#ifdef CONFIG_PXA3xx
138 int timeout = 100;
139#endif
140 gsr_bits = 0;
141
142#ifdef CONFIG_PXA27x
143
144
145 pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
146 udelay(10);
147 GCR |= GCR_WARM_RST;
148 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
149 udelay(500);
150#elif defined(CONFIG_PXA3xx)
151
152 GCR |= GCR_WARM_RST;
153 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
154 mdelay(1);
155#else
156 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
157 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
158#endif
159
160 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
161 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
162 __func__, gsr_bits);
163
164 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
165 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
166}
167
168static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
169{
170#ifdef CONFIG_PXA3xx
171 int timeout = 1000;
172
173
174 GCR = 0;
175 GCR = GCR_CLKBPB;
176 udelay(100);
177 GCR = 0;
178#endif
179
180 GCR &= GCR_COLD_RST;
181 GCR &= ~GCR_COLD_RST;
182
183 gsr_bits = 0;
184#ifdef CONFIG_PXA27x
185
186 clk_enable(ac97conf_clk);
187 udelay(5);
188 clk_disable(ac97conf_clk);
189 GCR = GCR_COLD_RST;
190 udelay(50);
191#elif defined(CONFIG_PXA3xx)
192
193 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
194
195 GCR = GCR_WARM_RST | GCR_COLD_RST;
196 while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
197 mdelay(10);
198#else
199 GCR = GCR_COLD_RST;
200 GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
201 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
202#endif
203
204 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
205 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
206 __func__, gsr_bits);
207
208 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
209 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
210}
211
212static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
213{
214 long status;
215
216 status = GSR;
217 if (status) {
218 GSR = status;
219 gsr_bits |= status;
220 wake_up(&gsr_wq);
221
222#ifdef CONFIG_PXA27x
223
224
225
226 MISR = MISR_EOC;
227 PISR = PISR_EOC;
228 MCSR = MCSR_EOC;
229#endif
230
231 return IRQ_HANDLED;
232 }
233
234 return IRQ_NONE;
235}
236
237struct snd_ac97_bus_ops soc_ac97_ops = {
238 .read = pxa2xx_ac97_read,
239 .write = pxa2xx_ac97_write,
240 .warm_reset = pxa2xx_ac97_warm_reset,
241 .reset = pxa2xx_ac97_cold_reset,
242};
243
244static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
245 .name = "AC97 PCM Stereo out",
246 .dev_addr = __PREG(PCDR),
247 .drcmr = &DRCMRTXPCDR,
248 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
249 DCMD_BURST32 | DCMD_WIDTH4,
250};
251
252static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
253 .name = "AC97 PCM Stereo in",
254 .dev_addr = __PREG(PCDR),
255 .drcmr = &DRCMRRXPCDR,
256 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
257 DCMD_BURST32 | DCMD_WIDTH4,
258};
259
260static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
261 .name = "AC97 Aux PCM (Slot 5) Mono out",
262 .dev_addr = __PREG(MODR),
263 .drcmr = &DRCMRTXMODR,
264 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
265 DCMD_BURST16 | DCMD_WIDTH2,
266};
267
268static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
269 .name = "AC97 Aux PCM (Slot 5) Mono in",
270 .dev_addr = __PREG(MODR),
271 .drcmr = &DRCMRRXMODR,
272 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
273 DCMD_BURST16 | DCMD_WIDTH2,
274};
275
276static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
277 .name = "AC97 Mic PCM (Slot 6) Mono in",
278 .dev_addr = __PREG(MCDR),
279 .drcmr = &DRCMRRXMCDR,
280 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
281 DCMD_BURST16 | DCMD_WIDTH2,
282};
283
284#ifdef CONFIG_PM
285static int pxa2xx_ac97_suspend(struct platform_device *pdev,
286 struct snd_soc_cpu_dai *dai)
287{
288 GCR |= GCR_ACLINK_OFF;
289 clk_disable(ac97_clk);
290 return 0;
291}
292
293static int pxa2xx_ac97_resume(struct platform_device *pdev,
294 struct snd_soc_cpu_dai *dai)
295{
296 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
297 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
298 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
299 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
300#ifdef CONFIG_PXA27x
301
302 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
303#endif
304 clk_enable(ac97_clk);
305 return 0;
306}
307
308#else
309#define pxa2xx_ac97_suspend NULL
310#define pxa2xx_ac97_resume NULL
311#endif
312
313static int pxa2xx_ac97_probe(struct platform_device *pdev)
314{
315 int ret;
316
317 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
318 if (ret < 0)
319 goto err;
320
321 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
322 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
323 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
324 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
325#ifdef CONFIG_PXA27x
326
327 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
328
329 ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK");
330 if (IS_ERR(ac97conf_clk)) {
331 ret = PTR_ERR(ac97conf_clk);
332 ac97conf_clk = NULL;
333 goto err_irq;
334 }
335#endif
336 ac97_clk = clk_get(&pdev->dev, "AC97CLK");
337 if (IS_ERR(ac97_clk)) {
338 ret = PTR_ERR(ac97_clk);
339 ac97_clk = NULL;
340 goto err_irq;
341 }
342 clk_enable(ac97_clk);
343 return 0;
344
345 err_irq:
346 GCR |= GCR_ACLINK_OFF;
347#ifdef CONFIG_PXA27x
348 if (ac97conf_clk) {
349 clk_put(ac97conf_clk);
350 ac97conf_clk = NULL;
351 }
352#endif
353 free_irq(IRQ_AC97, NULL);
354 err:
355 return ret;
356}
357
358static void pxa2xx_ac97_remove(struct platform_device *pdev)
359{
360 GCR |= GCR_ACLINK_OFF;
361 free_irq(IRQ_AC97, NULL);
362#ifdef CONFIG_PXA27x
363 clk_put(ac97conf_clk);
364 ac97conf_clk = NULL;
365#endif
366 clk_disable(ac97_clk);
367 clk_put(ac97_clk);
368 ac97_clk = NULL;
369}
370
371static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
372 struct snd_pcm_hw_params *params)
373{
374 struct snd_soc_pcm_runtime *rtd = substream->private_data;
375 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
376
377 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
378 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out;
379 else
380 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in;
381
382 return 0;
383}
384
385static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream,
386 struct snd_pcm_hw_params *params)
387{
388 struct snd_soc_pcm_runtime *rtd = substream->private_data;
389 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
390
391 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
392 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out;
393 else
394 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in;
395
396 return 0;
397}
398
399static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
400 struct snd_pcm_hw_params *params)
401{
402 struct snd_soc_pcm_runtime *rtd = substream->private_data;
403 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
404
405 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
406 return -ENODEV;
407 else
408 cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in;
409
410 return 0;
411}
412
413#define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
414 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
415 SNDRV_PCM_RATE_48000)
416
417
418
419
420
421struct snd_soc_cpu_dai pxa_ac97_dai[] = {
422{
423 .name = "pxa2xx-ac97",
424 .id = 0,
425 .type = SND_SOC_DAI_AC97,
426 .probe = pxa2xx_ac97_probe,
427 .remove = pxa2xx_ac97_remove,
428 .suspend = pxa2xx_ac97_suspend,
429 .resume = pxa2xx_ac97_resume,
430 .playback = {
431 .stream_name = "AC97 Playback",
432 .channels_min = 2,
433 .channels_max = 2,
434 .rates = PXA2XX_AC97_RATES,
435 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
436 .capture = {
437 .stream_name = "AC97 Capture",
438 .channels_min = 2,
439 .channels_max = 2,
440 .rates = PXA2XX_AC97_RATES,
441 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
442 .ops = {
443 .hw_params = pxa2xx_ac97_hw_params,},
444},
445{
446 .name = "pxa2xx-ac97-aux",
447 .id = 1,
448 .type = SND_SOC_DAI_AC97,
449 .playback = {
450 .stream_name = "AC97 Aux Playback",
451 .channels_min = 1,
452 .channels_max = 1,
453 .rates = PXA2XX_AC97_RATES,
454 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
455 .capture = {
456 .stream_name = "AC97 Aux Capture",
457 .channels_min = 1,
458 .channels_max = 1,
459 .rates = PXA2XX_AC97_RATES,
460 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
461 .ops = {
462 .hw_params = pxa2xx_ac97_hw_aux_params,},
463},
464{
465 .name = "pxa2xx-ac97-mic",
466 .id = 2,
467 .type = SND_SOC_DAI_AC97,
468 .capture = {
469 .stream_name = "AC97 Mic Capture",
470 .channels_min = 1,
471 .channels_max = 1,
472 .rates = PXA2XX_AC97_RATES,
473 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
474 .ops = {
475 .hw_params = pxa2xx_ac97_hw_mic_params,},
476},
477};
478
479EXPORT_SYMBOL_GPL(pxa_ac97_dai);
480EXPORT_SYMBOL_GPL(soc_ac97_ops);
481
482MODULE_AUTHOR("Nicolas Pitre");
483MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
484MODULE_LICENSE("GPL");
485
