LXR linux/include/asm-blackfin/bfin5xx

   1/************************************************************
   2
   3* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
   4*
   5* FILE bfin5xx_spi.h
   6* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
   7*
   8*
   9* DATE OF CREATION: March. 10th 2006
  10*
  11* SYNOPSIS:
  12*
  13* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
  14**************************************************************
  15
  16* MODIFICATION HISTORY:
  17* March 10, 2006  bfin5xx_spi.h Created. (Luke Yang)
  18
  19************************************************************/
  20
  21#ifndef _SPI_CHANNEL_H_
  22#define _SPI_CHANNEL_H_
  23
  24#define SPI_READ              0
  25#define SPI_WRITE             1
  26
  27#define SPI_CTRL_OFF            0x0
  28#define SPI_FLAG_OFF            0x4
  29#define SPI_STAT_OFF            0x8
  30#define SPI_TXBUFF_OFF          0xc
  31#define SPI_RXBUFF_OFF          0x10
  32#define SPI_BAUD_OFF            0x14
  33#define SPI_SHAW_OFF            0x18
  34
  35
  36#define BIT_CTL_ENABLE      0x4000
  37#define BIT_CTL_OPENDRAIN   0x2000
  38#define BIT_CTL_MASTER      0x1000
  39#define BIT_CTL_POLAR       0x0800
  40#define BIT_CTL_PHASE       0x0400
  41#define BIT_CTL_BITORDER    0x0200
  42#define BIT_CTL_WORDSIZE    0x0100
  43#define BIT_CTL_MISOENABLE  0x0020
  44#define BIT_CTL_RXMOD       0x0000
  45#define BIT_CTL_TXMOD       0x0001
  46#define BIT_CTL_TIMOD_DMA_TX 0x0003
  47#define BIT_CTL_TIMOD_DMA_RX 0x0002
  48#define BIT_CTL_SENDOPT     0x0004
  49#define BIT_CTL_TIMOD       0x0003
  50
  51#define BIT_STAT_SPIF       0x0001
  52#define BIT_STAT_MODF       0x0002
  53#define BIT_STAT_TXE        0x0004
  54#define BIT_STAT_TXS        0x0008
  55#define BIT_STAT_RBSY       0x0010
  56#define BIT_STAT_RXS        0x0020
  57#define BIT_STAT_TXCOL      0x0040
  58#define BIT_STAT_CLR        0xFFFF
  59
  60#define BIT_STU_SENDOVER    0x0001
  61#define BIT_STU_RECVFULL    0x0020
  62
  63#define CFG_SPI_ENABLE      1
  64#define CFG_SPI_DISABLE     0
  65
  66#define CFG_SPI_OUTENABLE   1
  67#define CFG_SPI_OUTDISABLE  0
  68
  69#define CFG_SPI_ACTLOW      1
  70#define CFG_SPI_ACTHIGH     0
  71
  72#define CFG_SPI_PHASESTART  1
  73#define CFG_SPI_PHASEMID    0
  74
  75#define CFG_SPI_MASTER      1
  76#define CFG_SPI_SLAVE       0
  77
  78#define CFG_SPI_SENELAST    0
  79#define CFG_SPI_SENDZERO    1
  80
  81#define CFG_SPI_RCVFLUSH    1
  82#define CFG_SPI_RCVDISCARD  0
  83
  84#define CFG_SPI_LSBFIRST    1
  85#define CFG_SPI_MSBFIRST    0
  86
  87#define CFG_SPI_WORDSIZE16  1
  88#define CFG_SPI_WORDSIZE8   0
  89
  90#define CFG_SPI_MISOENABLE   1
  91#define CFG_SPI_MISODISABLE  0
  92
  93#define CFG_SPI_READ      0x00
  94#define CFG_SPI_WRITE     0x01
  95#define CFG_SPI_DMAREAD   0x02
  96#define CFG_SPI_DMAWRITE  0x03
  97
  98#define CFG_SPI_CSCLEARALL  0
  99#define CFG_SPI_CHIPSEL1    1
 100#define CFG_SPI_CHIPSEL2    2
 101#define CFG_SPI_CHIPSEL3    3
 102#define CFG_SPI_CHIPSEL4    4
 103#define CFG_SPI_CHIPSEL5    5
 104#define CFG_SPI_CHIPSEL6    6
 105#define CFG_SPI_CHIPSEL7    7
 106
 107#define CFG_SPI_CS1VALUE    1
 108#define CFG_SPI_CS2VALUE    2
 109#define CFG_SPI_CS3VALUE    3
 110#define CFG_SPI_CS4VALUE    4
 111#define CFG_SPI_CS5VALUE    5
 112#define CFG_SPI_CS6VALUE    6
 113#define CFG_SPI_CS7VALUE    7
 114
 115#define CMD_SPI_SET_BAUDRATE  2
 116#define CMD_SPI_GET_SYSTEMCLOCK   25
 117#define CMD_SPI_SET_WRITECONTINUOUS     26
 118
 119/* device.platform_data for SSP controller devices */
 120struct bfin5xx_spi_master {
 121        u16 num_chipselect;
 122        u8 enable_dma;
 123        u16 pin_req[4];
 124};
 125
 126/* spi_board_info.controller_data for SPI slave devices,
 127 * copied to spi_device.platform_data ... mostly for dma tuning
 128 */
 129struct bfin5xx_spi_chip {
 130        u16 ctl_reg;
 131        u8 enable_dma;
 132        u8 bits_per_word;
 133        u8 cs_change_per_word;
 134        u16 cs_chg_udelay; /* Some devices require 16-bit delays */
 135};
 136
 137#endif /* _SPI_CHANNEL_H_ */
 138