LXR linux/arch/x86/kernel/cpu/mcheck/p5.c/

   1/*
   2 * P5 specific Machine Check Exception Reporting
   3 * (C) Copyright 2002 Alan Cox <alan@redhat.com>
   4 */
   5
   6#include <linux/init.h>
   7#include <linux/types.h>
   8#include <linux/kernel.h>
   9#include <linux/interrupt.h>
  10#include <linux/smp.h>
  11
  12#include <asm/processor.h>
  13#include <asm/system.h>
  14#include <asm/msr.h>
  15
  16#include "mce.h"
  17
  18/* Machine check handler for Pentium class Intel */
  19static void pentium_machine_check(struct pt_regs *regs, long error_code)
  20{
  21        u32 loaddr, hi, lotype;
  22        rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
  23        rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
  24        printk(KERN_EMERG "CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
  25        if (lotype&(1<<5))
  26                printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
  27        add_taint(TAINT_MACHINE_CHECK);
  28}
  29
  30/* Set up machine check reporting for processors with Intel style MCE */
  31void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
  32{
  33        u32 l, h;
  34
  35        /*Check for MCE support */
  36        if (!cpu_has(c, X86_FEATURE_MCE))
  37                return;
  38
  39        /* Default P5 to off as its often misconnected */
  40        if (mce_disabled != -1)
  41                return;
  42        machine_check_vector = pentium_machine_check;
  43        wmb();
  44
  45        /* Read registers before enabling */
  46        rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
  47        rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
  48        printk(KERN_INFO "Intel old style machine check architecture supported.\n");
  49
  50        /* Enable MCE */
  51        set_in_cr4(X86_CR4_MCE);
  52        printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
  53}
  54