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14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <asm/mach/irq.h>
18#include <asm/irq.h>
19#include <asm/hardware.h>
20#include <asm/mach-types.h>
21
22static u32 iop32x_mask;
23
24static void intctl_write(u32 val)
25{
26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
27}
28
29static void intstr_write(u32 val)
30{
31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
32}
33
34static void
35iop32x_irq_mask(unsigned int irq)
36{
37 iop32x_mask &= ~(1 << irq);
38 intctl_write(iop32x_mask);
39}
40
41static void
42iop32x_irq_unmask(unsigned int irq)
43{
44 iop32x_mask |= 1 << irq;
45 intctl_write(iop32x_mask);
46}
47
48struct irq_chip ext_chip = {
49 .name = "IOP32x",
50 .ack = iop32x_irq_mask,
51 .mask = iop32x_irq_mask,
52 .unmask = iop32x_irq_unmask,
53};
54
55void __init iop32x_init_irq(void)
56{
57 int i;
58
59 iop_init_cp6_handler();
60
61 intctl_write(0);
62 intstr_write(0);
63 if (machine_is_glantank() ||
64 machine_is_iq80321() ||
65 machine_is_iq31244() ||
66 machine_is_n2100() ||
67 machine_is_em7210())
68 *IOP3XX_PCIIRSR = 0x0f;
69
70 for (i = 0; i < NR_IRQS; i++) {
71 set_irq_chip(i, &ext_chip);
72 set_irq_handler(i, handle_level_irq);
73 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
74 }
75}
76