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10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/mm.h>
13#include <linux/ioport.h>
14#include <linux/list.h>
15#include <linux/init.h>
16
17#include <asm/pgtable.h>
18#include <asm/page.h>
19#include <asm/irq.h>
20#include <asm/io.h>
21#include <asm/mach-types.h>
22#include <asm/setup.h>
23#include <asm/hardware/dec21285.h>
24
25#include <asm/mach/irq.h>
26#include <asm/mach/map.h>
27
28#include "common.h"
29
30extern void __init isa_init_irq(unsigned int irq);
31
32unsigned int mem_fclk_21285 = 50000000;
33
34EXPORT_SYMBOL(mem_fclk_21285);
35
36static int __init parse_tag_memclk(const struct tag *tag)
37{
38 mem_fclk_21285 = tag->u.memclk.fmemclk;
39 return 0;
40}
41
42__tagtable(ATAG_MEMCLK, parse_tag_memclk);
43
44
45
46
47
48static const int fb_irq_mask[] = {
49 IRQ_MASK_UART_RX,
50 IRQ_MASK_UART_TX,
51 IRQ_MASK_TIMER1,
52 IRQ_MASK_TIMER2,
53 IRQ_MASK_TIMER3,
54 IRQ_MASK_IN0,
55 IRQ_MASK_IN1,
56 IRQ_MASK_IN2,
57 IRQ_MASK_IN3,
58 IRQ_MASK_DOORBELLHOST,
59 IRQ_MASK_DMA1,
60 IRQ_MASK_DMA2,
61 IRQ_MASK_PCI,
62 IRQ_MASK_SDRAMPARITY,
63 IRQ_MASK_I2OINPOST,
64 IRQ_MASK_PCI_ABORT,
65 IRQ_MASK_PCI_SERR,
66 IRQ_MASK_DISCARD_TIMER,
67 IRQ_MASK_PCI_DPERR,
68 IRQ_MASK_PCI_PERR,
69};
70
71static void fb_mask_irq(unsigned int irq)
72{
73 *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(irq)];
74}
75
76static void fb_unmask_irq(unsigned int irq)
77{
78 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
79}
80
81static struct irq_chip fb_chip = {
82 .ack = fb_mask_irq,
83 .mask = fb_mask_irq,
84 .unmask = fb_unmask_irq,
85};
86
87static void __init __fb_init_irq(void)
88{
89 unsigned int irq;
90
91
92
93
94 *CSR_IRQ_DISABLE = -1;
95 *CSR_FIQ_DISABLE = -1;
96
97 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
98 set_irq_chip(irq, &fb_chip);
99 set_irq_handler(irq, handle_level_irq);
100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
101 }
102}
103
104void __init footbridge_init_irq(void)
105{
106 __fb_init_irq();
107
108 if (!footbridge_cfn_mode())
109 return;
110
111 if (machine_is_ebsa285())
112
113
114
115
116
117 isa_init_irq(IRQ_PCI);
118
119 if (machine_is_cats())
120 isa_init_irq(IRQ_IN2);
121
122 if (machine_is_netwinder())
123 isa_init_irq(IRQ_IN3);
124}
125
126
127
128
129
130
131static struct map_desc fb_common_io_desc[] __initdata = {
132 {
133 .virtual = ARMCSR_BASE,
134 .pfn = __phys_to_pfn(DC21285_ARMCSR_BASE),
135 .length = ARMCSR_SIZE,
136 .type = MT_DEVICE,
137 }, {
138 .virtual = XBUS_BASE,
139 .pfn = __phys_to_pfn(0x40000000),
140 .length = XBUS_SIZE,
141 .type = MT_DEVICE,
142 }
143};
144
145
146
147
148
149static struct map_desc ebsa285_host_io_desc[] __initdata = {
150#if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
151 {
152 .virtual = PCIMEM_BASE,
153 .pfn = __phys_to_pfn(DC21285_PCI_MEM),
154 .length = PCIMEM_SIZE,
155 .type = MT_DEVICE,
156 }, {
157 .virtual = PCICFG0_BASE,
158 .pfn = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
159 .length = PCICFG0_SIZE,
160 .type = MT_DEVICE,
161 }, {
162 .virtual = PCICFG1_BASE,
163 .pfn = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
164 .length = PCICFG1_SIZE,
165 .type = MT_DEVICE,
166 }, {
167 .virtual = PCIIACK_BASE,
168 .pfn = __phys_to_pfn(DC21285_PCI_IACK),
169 .length = PCIIACK_SIZE,
170 .type = MT_DEVICE,
171 }, {
172 .virtual = PCIO_BASE,
173 .pfn = __phys_to_pfn(DC21285_PCI_IO),
174 .length = PCIO_SIZE,
175 .type = MT_DEVICE,
176 },
177#endif
178};
179
180
181
182
183static struct map_desc co285_io_desc[] __initdata = {
184#ifdef CONFIG_ARCH_CO285
185 {
186 .virtual = PCIO_BASE,
187 .pfn = __phys_to_pfn(DC21285_PCI_IO),
188 .length = PCIO_SIZE,
189 .type = MT_DEVICE,
190 }, {
191 .virtual = PCIMEM_BASE,
192 .pfn = __phys_to_pfn(DC21285_PCI_MEM),
193 .length = PCIMEM_SIZE,
194 .type = MT_DEVICE,
195 },
196#endif
197};
198
199void __init footbridge_map_io(void)
200{
201
202
203
204
205 iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
206
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209
210
211 if (machine_is_co285())
212 iotable_init(co285_io_desc, ARRAY_SIZE(co285_io_desc));
213 if (footbridge_cfn_mode())
214 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
215}
216
217#ifdef CONFIG_FOOTBRIDGE_ADDIN
218
219
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221
222
223
224unsigned long __virt_to_bus(unsigned long res)
225{
226 WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
227
228 return (res - PAGE_OFFSET) + (*CSR_PCISDRAMBASE & 0xfffffff0);
229}
230EXPORT_SYMBOL(__virt_to_bus);
231
232unsigned long __bus_to_virt(unsigned long res)
233{
234 res -= (*CSR_PCISDRAMBASE & 0xfffffff0);
235 res += PAGE_OFFSET;
236
237 WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
238
239 return res;
240}
241EXPORT_SYMBOL(__bus_to_virt);
242
243#endif
244