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10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/string.h>
14#include <linux/slab.h>
15#include <linux/delay.h>
16#include <linux/init.h>
17#include <linux/fb.h>
18#include <linux/mm.h>
19#include <linux/uaccess.h>
20
21#include <asm/io.h>
22#include <asm/prom.h>
23#include <asm/of_device.h>
24#include <asm/fbio.h>
25
26#include "sbuslib.h"
27
28
29
30
31
32static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
33 unsigned, struct fb_info *);
34
35static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
36static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
37static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);
38
39
40
41
42
43static struct fb_ops cg14_ops = {
44 .owner = THIS_MODULE,
45 .fb_setcolreg = cg14_setcolreg,
46 .fb_pan_display = cg14_pan_display,
47 .fb_fillrect = cfb_fillrect,
48 .fb_copyarea = cfb_copyarea,
49 .fb_imageblit = cfb_imageblit,
50 .fb_mmap = cg14_mmap,
51 .fb_ioctl = cg14_ioctl,
52#ifdef CONFIG_COMPAT
53 .fb_compat_ioctl = sbusfb_compat_ioctl,
54#endif
55};
56
57#define CG14_MCR_INTENABLE_SHIFT 7
58#define CG14_MCR_INTENABLE_MASK 0x80
59#define CG14_MCR_VIDENABLE_SHIFT 6
60#define CG14_MCR_VIDENABLE_MASK 0x40
61#define CG14_MCR_PIXMODE_SHIFT 4
62#define CG14_MCR_PIXMODE_MASK 0x30
63#define CG14_MCR_TMR_SHIFT 2
64#define CG14_MCR_TMR_MASK 0x0c
65#define CG14_MCR_TMENABLE_SHIFT 1
66#define CG14_MCR_TMENABLE_MASK 0x02
67#define CG14_MCR_RESET_SHIFT 0
68#define CG14_MCR_RESET_MASK 0x01
69#define CG14_REV_REVISION_SHIFT 4
70#define CG14_REV_REVISION_MASK 0xf0
71#define CG14_REV_IMPL_SHIFT 0
72#define CG14_REV_IMPL_MASK 0x0f
73#define CG14_VBR_FRAMEBASE_SHIFT 12
74#define CG14_VBR_FRAMEBASE_MASK 0x00fff000
75#define CG14_VMCR1_SETUP_SHIFT 0
76#define CG14_VMCR1_SETUP_MASK 0x000001ff
77#define CG14_VMCR1_VCONFIG_SHIFT 9
78#define CG14_VMCR1_VCONFIG_MASK 0x00000e00
79#define CG14_VMCR2_REFRESH_SHIFT 0
80#define CG14_VMCR2_REFRESH_MASK 0x00000001
81#define CG14_VMCR2_TESTROWCNT_SHIFT 1
82#define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
83#define CG14_VMCR2_FBCONFIG_SHIFT 2
84#define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
85#define CG14_VCR_REFRESHREQ_SHIFT 0
86#define CG14_VCR_REFRESHREQ_MASK 0x000003ff
87#define CG14_VCR1_REFRESHENA_SHIFT 10
88#define CG14_VCR1_REFRESHENA_MASK 0x00000400
89#define CG14_VCA_CAD_SHIFT 0
90#define CG14_VCA_CAD_MASK 0x000003ff
91#define CG14_VCA_VERS_SHIFT 10
92#define CG14_VCA_VERS_MASK 0x00000c00
93#define CG14_VCA_RAMSPEED_SHIFT 12
94#define CG14_VCA_RAMSPEED_MASK 0x00001000
95#define CG14_VCA_8MB_SHIFT 13
96#define CG14_VCA_8MB_MASK 0x00002000
97
98#define CG14_MCR_PIXMODE_8 0
99#define CG14_MCR_PIXMODE_16 2
100#define CG14_MCR_PIXMODE_32 3
101
102struct cg14_regs{
103 u8 mcr;
104 u8 ppr;
105 u8 tms[2];
106 u8 msr;
107 u8 fsr;
108 u8 rev;
109 u8 ccr;
110 u32 tmr;
111 u8 mod;
112 u8 acr;
113 u8 xxx0[6];
114 u16 hct;
115 u16 vct;
116 u16 hbs;
117 u16 hbc;
118 u16 hss;
119 u16 hsc;
120 u16 csc;
121 u16 vbs;
122 u16 vbc;
123 u16 vss;
124 u16 vsc;
125 u16 xcs;
126 u16 xcc;
127 u16 fsa;
128 u16 adr;
129 u8 xxx1[0xce];
130 u8 pcg[0x100];
131 u32 vbr;
132 u32 vmcr;
133 u32 vcr;
134 u32 vca;
135};
136
137#define CG14_CCR_ENABLE 0x04
138#define CG14_CCR_SELECT 0x02
139
140struct cg14_cursor {
141 u32 cpl0[32];
142 u32 cpl1[32];
143 u8 ccr;
144 u8 xxx0[3];
145 u16 cursx;
146 u16 cursy;
147 u32 color0;
148 u32 color1;
149 u32 xxx1[0x1bc];
150 u32 cpl0i[32];
151 u32 cpl1i[32];
152};
153
154struct cg14_dac {
155 u8 addr;
156 u8 xxx0[255];
157 u8 glut;
158 u8 xxx1[255];
159 u8 select;
160 u8 xxx2[255];
161 u8 mode;
162};
163
164struct cg14_xlut{
165 u8 x_xlut [256];
166 u8 x_xlutd [256];
167 u8 xxx0[0x600];
168 u8 x_xlut_inc [256];
169 u8 x_xlutd_inc [256];
170};
171
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179
180
181
182struct cg14_clut {
183 u32 c_clut [256];
184 u32 c_clutd [256];
185 u32 c_clut_inc [256];
186 u32 c_clutd_inc [256];
187};
188
189#define CG14_MMAP_ENTRIES 16
190
191struct cg14_par {
192 spinlock_t lock;
193 struct cg14_regs __iomem *regs;
194 struct cg14_clut __iomem *clut;
195 struct cg14_cursor __iomem *cursor;
196
197 u32 flags;
198#define CG14_FLAG_BLANKED 0x00000001
199
200 unsigned long physbase;
201 unsigned long iospace;
202 unsigned long fbsize;
203
204 struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
205
206 int mode;
207 int ramsize;
208};
209
210static void __cg14_reset(struct cg14_par *par)
211{
212 struct cg14_regs __iomem *regs = par->regs;
213 u8 val;
214
215 val = sbus_readb(®s->mcr);
216 val &= ~(CG14_MCR_PIXMODE_MASK);
217 sbus_writeb(val, ®s->mcr);
218}
219
220static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
221{
222 struct cg14_par *par = (struct cg14_par *) info->par;
223 unsigned long flags;
224
225
226
227
228 spin_lock_irqsave(&par->lock, flags);
229 __cg14_reset(par);
230 spin_unlock_irqrestore(&par->lock, flags);
231
232 if (var->xoffset || var->yoffset || var->vmode)
233 return -EINVAL;
234 return 0;
235}
236
237
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241
242
243
244
245
246static int cg14_setcolreg(unsigned regno,
247 unsigned red, unsigned green, unsigned blue,
248 unsigned transp, struct fb_info *info)
249{
250 struct cg14_par *par = (struct cg14_par *) info->par;
251 struct cg14_clut __iomem *clut = par->clut;
252 unsigned long flags;
253 u32 val;
254
255 if (regno >= 256)
256 return 1;
257
258 red >>= 8;
259 green >>= 8;
260 blue >>= 8;
261 val = (red | (green << 8) | (blue << 16));
262
263 spin_lock_irqsave(&par->lock, flags);
264 sbus_writel(val, &clut->c_clut[regno]);
265 spin_unlock_irqrestore(&par->lock, flags);
266
267 return 0;
268}
269
270static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
271{
272 struct cg14_par *par = (struct cg14_par *) info->par;
273
274 return sbusfb_mmap_helper(par->mmap_map,
275 par->physbase, par->fbsize,
276 par->iospace, vma);
277}
278
279static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
280{
281 struct cg14_par *par = (struct cg14_par *) info->par;
282 struct cg14_regs __iomem *regs = par->regs;
283 struct mdi_cfginfo kmdi, __user *mdii;
284 unsigned long flags;
285 int cur_mode, mode, ret = 0;
286
287 switch (cmd) {
288 case MDI_RESET:
289 spin_lock_irqsave(&par->lock, flags);
290 __cg14_reset(par);
291 spin_unlock_irqrestore(&par->lock, flags);
292 break;
293
294 case MDI_GET_CFGINFO:
295 memset(&kmdi, 0, sizeof(kmdi));
296
297 spin_lock_irqsave(&par->lock, flags);
298 kmdi.mdi_type = FBTYPE_MDICOLOR;
299 kmdi.mdi_height = info->var.yres;
300 kmdi.mdi_width = info->var.xres;
301 kmdi.mdi_mode = par->mode;
302 kmdi.mdi_pixfreq = 72;
303 kmdi.mdi_size = par->ramsize;
304 spin_unlock_irqrestore(&par->lock, flags);
305
306 mdii = (struct mdi_cfginfo __user *) arg;
307 if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
308 ret = -EFAULT;
309 break;
310
311 case MDI_SET_PIXELMODE:
312 if (get_user(mode, (int __user *) arg)) {
313 ret = -EFAULT;
314 break;
315 }
316
317 spin_lock_irqsave(&par->lock, flags);
318 cur_mode = sbus_readb(®s->mcr);
319 cur_mode &= ~CG14_MCR_PIXMODE_MASK;
320 switch(mode) {
321 case MDI_32_PIX:
322 cur_mode |= (CG14_MCR_PIXMODE_32 <<
323 CG14_MCR_PIXMODE_SHIFT);
324 break;
325
326 case MDI_16_PIX:
327 cur_mode |= (CG14_MCR_PIXMODE_16 <<
328 CG14_MCR_PIXMODE_SHIFT);
329 break;
330
331 case MDI_8_PIX:
332 break;
333
334 default:
335 ret = -ENOSYS;
336 break;
337 };
338 if (!ret) {
339 sbus_writeb(cur_mode, ®s->mcr);
340 par->mode = mode;
341 }
342 spin_unlock_irqrestore(&par->lock, flags);
343 break;
344
345 default:
346 ret = sbusfb_ioctl_helper(cmd, arg, info,
347 FBTYPE_MDICOLOR, 8, par->fbsize);
348 break;
349 };
350
351 return ret;
352}
353
354
355
356
357
358static void __devinit cg14_init_fix(struct fb_info *info, int linebytes,
359 struct device_node *dp)
360{
361 const char *name = dp->name;
362
363 strlcpy(info->fix.id, name, sizeof(info->fix.id));
364
365 info->fix.type = FB_TYPE_PACKED_PIXELS;
366 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
367
368 info->fix.line_length = linebytes;
369
370 info->fix.accel = FB_ACCEL_SUN_CG14;
371}
372
373static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] __devinitdata = {
374 {
375 .voff = CG14_REGS,
376 .poff = 0x80000000,
377 .size = 0x1000
378 },
379 {
380 .voff = CG14_XLUT,
381 .poff = 0x80003000,
382 .size = 0x1000
383 },
384 {
385 .voff = CG14_CLUT1,
386 .poff = 0x80004000,
387 .size = 0x1000
388 },
389 {
390 .voff = CG14_CLUT2,
391 .poff = 0x80005000,
392 .size = 0x1000
393 },
394 {
395 .voff = CG14_CLUT3,
396 .poff = 0x80006000,
397 .size = 0x1000
398 },
399 {
400 .voff = CG3_MMAP_OFFSET - 0x7000,
401 .poff = 0x80000000,
402 .size = 0x7000
403 },
404 {
405 .voff = CG3_MMAP_OFFSET,
406 .poff = 0x00000000,
407 .size = SBUS_MMAP_FBSIZE(1)
408 },
409 {
410 .voff = MDI_CURSOR_MAP,
411 .poff = 0x80001000,
412 .size = 0x1000
413 },
414 {
415 .voff = MDI_CHUNKY_BGR_MAP,
416 .poff = 0x01000000,
417 .size = 0x400000
418 },
419 {
420 .voff = MDI_PLANAR_X16_MAP,
421 .poff = 0x02000000,
422 .size = 0x200000
423 },
424 {
425 .voff = MDI_PLANAR_C16_MAP,
426 .poff = 0x02800000,
427 .size = 0x200000
428 },
429 {
430 .voff = MDI_PLANAR_X32_MAP,
431 .poff = 0x03000000,
432 .size = 0x100000
433 },
434 {
435 .voff = MDI_PLANAR_B32_MAP,
436 .poff = 0x03400000,
437 .size = 0x100000
438 },
439 {
440 .voff = MDI_PLANAR_G32_MAP,
441 .poff = 0x03800000,
442 .size = 0x100000
443 },
444 {
445 .voff = MDI_PLANAR_R32_MAP,
446 .poff = 0x03c00000,
447 .size = 0x100000
448 },
449 { .size = 0 }
450};
451
452static void cg14_unmap_regs(struct of_device *op, struct fb_info *info,
453 struct cg14_par *par)
454{
455 if (par->regs)
456 of_iounmap(&op->resource[0],
457 par->regs, sizeof(struct cg14_regs));
458 if (par->clut)
459 of_iounmap(&op->resource[0],
460 par->clut, sizeof(struct cg14_clut));
461 if (par->cursor)
462 of_iounmap(&op->resource[0],
463 par->cursor, sizeof(struct cg14_cursor));
464 if (info->screen_base)
465 of_iounmap(&op->resource[1],
466 info->screen_base, par->fbsize);
467}
468
469static int __devinit cg14_probe(struct of_device *op, const struct of_device_id *match)
470{
471 struct device_node *dp = op->node;
472 struct fb_info *info;
473 struct cg14_par *par;
474 int is_8mb, linebytes, i, err;
475
476 info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);
477
478 err = -ENOMEM;
479 if (!info)
480 goto out_err;
481 par = info->par;
482
483 spin_lock_init(&par->lock);
484
485 sbusfb_fill_var(&info->var, dp->node, 8);
486 info->var.red.length = 8;
487 info->var.green.length = 8;
488 info->var.blue.length = 8;
489
490 linebytes = of_getintprop_default(dp, "linebytes",
491 info->var.xres);
492 par->fbsize = PAGE_ALIGN(linebytes * info->var.yres);
493
494 if (!strcmp(dp->parent->name, "sbus") ||
495 !strcmp(dp->parent->name, "sbi")) {
496 par->physbase = op->resource[0].start;
497 par->iospace = op->resource[0].flags & IORESOURCE_BITS;
498 } else {
499 par->physbase = op->resource[1].start;
500 par->iospace = op->resource[0].flags & IORESOURCE_BITS;
501 }
502
503 par->regs = of_ioremap(&op->resource[0], 0,
504 sizeof(struct cg14_regs), "cg14 regs");
505 par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
506 sizeof(struct cg14_clut), "cg14 clut");
507 par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
508 sizeof(struct cg14_cursor), "cg14 cursor");
509
510 info->screen_base = of_ioremap(&op->resource[1], 0,
511 par->fbsize, "cg14 ram");
512
513 if (!par->regs || !par->clut || !par->cursor || !info->screen_base)
514 goto out_unmap_regs;
515
516 is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
517 (8 * 1024 * 1024));
518
519 BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
520
521 memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));
522
523 for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
524 struct sbus_mmap_map *map = &par->mmap_map[i];
525
526 if (!map->size)
527 break;
528 if (map->poff & 0x80000000)
529 map->poff = (map->poff & 0x7fffffff) +
530 (op->resource[0].start -
531 op->resource[1].start);
532 if (is_8mb &&
533 map->size >= 0x100000 &&
534 map->size <= 0x400000)
535 map->size *= 2;
536 }
537
538 par->mode = MDI_8_PIX;
539 par->ramsize = (is_8mb ? 0x800000 : 0x400000);
540
541 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
542 info->fbops = &cg14_ops;
543
544 __cg14_reset(par);
545
546 if (fb_alloc_cmap(&info->cmap, 256, 0))
547 goto out_unmap_regs;
548
549 fb_set_cmap(&info->cmap, info);
550
551 cg14_init_fix(info, linebytes, dp);
552
553 err = register_framebuffer(info);
554 if (err < 0)
555 goto out_dealloc_cmap;
556
557 dev_set_drvdata(&op->dev, info);
558
559 printk("%s: cgfourteen at %lx:%lx, %dMB\n",
560 dp->full_name,
561 par->iospace, par->physbase,
562 par->ramsize >> 20);
563
564 return 0;
565
566out_dealloc_cmap:
567 fb_dealloc_cmap(&info->cmap);
568
569out_unmap_regs:
570 cg14_unmap_regs(op, info, par);
571
572out_err:
573 return err;
574}
575
576static int __devexit cg14_remove(struct of_device *op)
577{
578 struct fb_info *info = dev_get_drvdata(&op->dev);
579 struct cg14_par *par = info->par;
580
581 unregister_framebuffer(info);
582 fb_dealloc_cmap(&info->cmap);
583
584 cg14_unmap_regs(op, info, par);
585
586 framebuffer_release(info);
587
588 dev_set_drvdata(&op->dev, NULL);
589
590 return 0;
591}
592
593static struct of_device_id cg14_match[] = {
594 {
595 .name = "cgfourteen",
596 },
597 {},
598};
599MODULE_DEVICE_TABLE(of, cg14_match);
600
601static struct of_platform_driver cg14_driver = {
602 .name = "cg14",
603 .match_table = cg14_match,
604 .probe = cg14_probe,
605 .remove = __devexit_p(cg14_remove),
606};
607
608int __init cg14_init(void)
609{
610 if (fb_get_options("cg14fb", NULL))
611 return -ENODEV;
612
613 return of_register_driver(&cg14_driver, &of_bus_type);
614}
615
616void __exit cg14_exit(void)
617{
618 of_unregister_driver(&cg14_driver);
619}
620
621module_init(cg14_init);
622module_exit(cg14_exit);
623
624MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
625MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
626MODULE_VERSION("2.0");
627MODULE_LICENSE("GPL");
628
