1#ifndef __ARCH_X86_64_ATOMIC__
2#define __ARCH_X86_64_ATOMIC__
3
4#include <asm/alternative.h>
5#include <asm/cmpxchg.h>
6
7
8
9
10
11
12
13
14#ifdef CONFIG_SMP
15#define LOCK "lock ; "
16#else
17#define LOCK ""
18#endif
19
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22
23
24
25typedef struct { int counter; } atomic_t;
26
27#define ATOMIC_INIT(i) { (i) }
28
29
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33
34
35#define atomic_read(v) ((v)->counter)
36
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41
42
43
44#define atomic_set(v,i) (((v)->counter) = (i))
45
46
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51
52
53static __inline__ void atomic_add(int i, atomic_t *v)
54{
55 __asm__ __volatile__(
56 LOCK_PREFIX "addl %1,%0"
57 :"=m" (v->counter)
58 :"ir" (i), "m" (v->counter));
59}
60
61
62
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64
65
66
67
68static __inline__ void atomic_sub(int i, atomic_t *v)
69{
70 __asm__ __volatile__(
71 LOCK_PREFIX "subl %1,%0"
72 :"=m" (v->counter)
73 :"ir" (i), "m" (v->counter));
74}
75
76
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83
84
85static __inline__ int atomic_sub_and_test(int i, atomic_t *v)
86{
87 unsigned char c;
88
89 __asm__ __volatile__(
90 LOCK_PREFIX "subl %2,%0; sete %1"
91 :"=m" (v->counter), "=qm" (c)
92 :"ir" (i), "m" (v->counter) : "memory");
93 return c;
94}
95
96
97
98
99
100
101
102static __inline__ void atomic_inc(atomic_t *v)
103{
104 __asm__ __volatile__(
105 LOCK_PREFIX "incl %0"
106 :"=m" (v->counter)
107 :"m" (v->counter));
108}
109
110
111
112
113
114
115
116static __inline__ void atomic_dec(atomic_t *v)
117{
118 __asm__ __volatile__(
119 LOCK_PREFIX "decl %0"
120 :"=m" (v->counter)
121 :"m" (v->counter));
122}
123
124
125
126
127
128
129
130
131
132static __inline__ int atomic_dec_and_test(atomic_t *v)
133{
134 unsigned char c;
135
136 __asm__ __volatile__(
137 LOCK_PREFIX "decl %0; sete %1"
138 :"=m" (v->counter), "=qm" (c)
139 :"m" (v->counter) : "memory");
140 return c != 0;
141}
142
143
144
145
146
147
148
149
150
151static __inline__ int atomic_inc_and_test(atomic_t *v)
152{
153 unsigned char c;
154
155 __asm__ __volatile__(
156 LOCK_PREFIX "incl %0; sete %1"
157 :"=m" (v->counter), "=qm" (c)
158 :"m" (v->counter) : "memory");
159 return c != 0;
160}
161
162
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166
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168
169
170
171static __inline__ int atomic_add_negative(int i, atomic_t *v)
172{
173 unsigned char c;
174
175 __asm__ __volatile__(
176 LOCK_PREFIX "addl %2,%0; sets %1"
177 :"=m" (v->counter), "=qm" (c)
178 :"ir" (i), "m" (v->counter) : "memory");
179 return c;
180}
181
182
183
184
185
186
187
188
189static __inline__ int atomic_add_return(int i, atomic_t *v)
190{
191 int __i = i;
192 __asm__ __volatile__(
193 LOCK_PREFIX "xaddl %0, %1"
194 :"+r" (i), "+m" (v->counter)
195 : : "memory");
196 return i + __i;
197}
198
199static __inline__ int atomic_sub_return(int i, atomic_t *v)
200{
201 return atomic_add_return(-i,v);
202}
203
204#define atomic_inc_return(v) (atomic_add_return(1,v))
205#define atomic_dec_return(v) (atomic_sub_return(1,v))
206
207
208
209typedef struct { long counter; } atomic64_t;
210
211#define ATOMIC64_INIT(i) { (i) }
212
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217
218
219
220#define atomic64_read(v) ((v)->counter)
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227
228
229#define atomic64_set(v,i) (((v)->counter) = (i))
230
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236
237
238static __inline__ void atomic64_add(long i, atomic64_t *v)
239{
240 __asm__ __volatile__(
241 LOCK_PREFIX "addq %1,%0"
242 :"=m" (v->counter)
243 :"ir" (i), "m" (v->counter));
244}
245
246
247
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249
250
251
252
253static __inline__ void atomic64_sub(long i, atomic64_t *v)
254{
255 __asm__ __volatile__(
256 LOCK_PREFIX "subq %1,%0"
257 :"=m" (v->counter)
258 :"ir" (i), "m" (v->counter));
259}
260
261
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264
265
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267
268
269
270static __inline__ int atomic64_sub_and_test(long i, atomic64_t *v)
271{
272 unsigned char c;
273
274 __asm__ __volatile__(
275 LOCK_PREFIX "subq %2,%0; sete %1"
276 :"=m" (v->counter), "=qm" (c)
277 :"ir" (i), "m" (v->counter) : "memory");
278 return c;
279}
280
281
282
283
284
285
286
287static __inline__ void atomic64_inc(atomic64_t *v)
288{
289 __asm__ __volatile__(
290 LOCK_PREFIX "incq %0"
291 :"=m" (v->counter)
292 :"m" (v->counter));
293}
294
295
296
297
298
299
300
301static __inline__ void atomic64_dec(atomic64_t *v)
302{
303 __asm__ __volatile__(
304 LOCK_PREFIX "decq %0"
305 :"=m" (v->counter)
306 :"m" (v->counter));
307}
308
309
310
311
312
313
314
315
316
317static __inline__ int atomic64_dec_and_test(atomic64_t *v)
318{
319 unsigned char c;
320
321 __asm__ __volatile__(
322 LOCK_PREFIX "decq %0; sete %1"
323 :"=m" (v->counter), "=qm" (c)
324 :"m" (v->counter) : "memory");
325 return c != 0;
326}
327
328
329
330
331
332
333
334
335
336static __inline__ int atomic64_inc_and_test(atomic64_t *v)
337{
338 unsigned char c;
339
340 __asm__ __volatile__(
341 LOCK_PREFIX "incq %0; sete %1"
342 :"=m" (v->counter), "=qm" (c)
343 :"m" (v->counter) : "memory");
344 return c != 0;
345}
346
347
348
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351
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353
354
355
356static __inline__ int atomic64_add_negative(long i, atomic64_t *v)
357{
358 unsigned char c;
359
360 __asm__ __volatile__(
361 LOCK_PREFIX "addq %2,%0; sets %1"
362 :"=m" (v->counter), "=qm" (c)
363 :"ir" (i), "m" (v->counter) : "memory");
364 return c;
365}
366
367
368
369
370
371
372
373
374static __inline__ long atomic64_add_return(long i, atomic64_t *v)
375{
376 long __i = i;
377 __asm__ __volatile__(
378 LOCK_PREFIX "xaddq %0, %1;"
379 :"+r" (i), "+m" (v->counter)
380 : : "memory");
381 return i + __i;
382}
383
384static __inline__ long atomic64_sub_return(long i, atomic64_t *v)
385{
386 return atomic64_add_return(-i,v);
387}
388
389#define atomic64_inc_return(v) (atomic64_add_return(1,v))
390#define atomic64_dec_return(v) (atomic64_sub_return(1,v))
391
392#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
393#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
394
395#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
396#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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405
406
407static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
408{
409 int c, old;
410 c = atomic_read(v);
411 for (;;) {
412 if (unlikely(c == (u)))
413 break;
414 old = atomic_cmpxchg((v), c, c + (a));
415 if (likely(old == c))
416 break;
417 c = old;
418 }
419 return c != (u);
420}
421
422#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
423
424
425
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430
431
432
433static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
434{
435 long c, old;
436 c = atomic64_read(v);
437 for (;;) {
438 if (unlikely(c == (u)))
439 break;
440 old = atomic64_cmpxchg((v), c, c + (a));
441 if (likely(old == c))
442 break;
443 c = old;
444 }
445 return c != (u);
446}
447
448#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
449
450
451#define atomic_clear_mask(mask, addr) \
452__asm__ __volatile__(LOCK_PREFIX "andl %0,%1" \
453: : "r" (~(mask)),"m" (*addr) : "memory")
454
455#define atomic_set_mask(mask, addr) \
456__asm__ __volatile__(LOCK_PREFIX "orl %0,%1" \
457: : "r" ((unsigned)mask),"m" (*(addr)) : "memory")
458
459
460#define smp_mb__before_atomic_dec() barrier()
461#define smp_mb__after_atomic_dec() barrier()
462#define smp_mb__before_atomic_inc() barrier()
463#define smp_mb__after_atomic_inc() barrier()
464
465#include <asm-generic/atomic.h>
466#endif
467