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19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
26#include <linux/in.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
39#include <linux/prefetch.h>
40#include <linux/dma-mapping.h>
41
42#include <net/checksum.h>
43#include <net/ip.h>
44
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/byteorder.h>
48#include <asm/uaccess.h>
49
50#ifdef CONFIG_SPARC
51#include <asm/idprom.h>
52#include <asm/prom.h>
53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
61#define TG3_TSO_SUPPORT 1
62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
67#define DRV_MODULE_VERSION "3.91"
68#define DRV_MODULE_RELDATE "April 18, 2008"
69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83
84
85
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93
94
95
96
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102
103
104
105
106
107
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127
128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
129
130
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133#define TG3_NUM_TEST 6
134
135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1;
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
209 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
210 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
212 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
213 {}
214};
215
216MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
217
218static const struct {
219 const char string[ETH_GSTRING_LEN];
220} ethtool_stats_keys[TG3_NUM_STATS] = {
221 { "rx_octets" },
222 { "rx_fragments" },
223 { "rx_ucast_packets" },
224 { "rx_mcast_packets" },
225 { "rx_bcast_packets" },
226 { "rx_fcs_errors" },
227 { "rx_align_errors" },
228 { "rx_xon_pause_rcvd" },
229 { "rx_xoff_pause_rcvd" },
230 { "rx_mac_ctrl_rcvd" },
231 { "rx_xoff_entered" },
232 { "rx_frame_too_long_errors" },
233 { "rx_jabbers" },
234 { "rx_undersize_packets" },
235 { "rx_in_length_errors" },
236 { "rx_out_length_errors" },
237 { "rx_64_or_less_octet_packets" },
238 { "rx_65_to_127_octet_packets" },
239 { "rx_128_to_255_octet_packets" },
240 { "rx_256_to_511_octet_packets" },
241 { "rx_512_to_1023_octet_packets" },
242 { "rx_1024_to_1522_octet_packets" },
243 { "rx_1523_to_2047_octet_packets" },
244 { "rx_2048_to_4095_octet_packets" },
245 { "rx_4096_to_8191_octet_packets" },
246 { "rx_8192_to_9022_octet_packets" },
247
248 { "tx_octets" },
249 { "tx_collisions" },
250
251 { "tx_xon_sent" },
252 { "tx_xoff_sent" },
253 { "tx_flow_control" },
254 { "tx_mac_errors" },
255 { "tx_single_collisions" },
256 { "tx_mult_collisions" },
257 { "tx_deferred" },
258 { "tx_excessive_collisions" },
259 { "tx_late_collisions" },
260 { "tx_collide_2times" },
261 { "tx_collide_3times" },
262 { "tx_collide_4times" },
263 { "tx_collide_5times" },
264 { "tx_collide_6times" },
265 { "tx_collide_7times" },
266 { "tx_collide_8times" },
267 { "tx_collide_9times" },
268 { "tx_collide_10times" },
269 { "tx_collide_11times" },
270 { "tx_collide_12times" },
271 { "tx_collide_13times" },
272 { "tx_collide_14times" },
273 { "tx_collide_15times" },
274 { "tx_ucast_packets" },
275 { "tx_mcast_packets" },
276 { "tx_bcast_packets" },
277 { "tx_carrier_sense_errors" },
278 { "tx_discards" },
279 { "tx_errors" },
280
281 { "dma_writeq_full" },
282 { "dma_write_prioq_full" },
283 { "rxbds_empty" },
284 { "rx_discards" },
285 { "rx_errors" },
286 { "rx_threshold_hit" },
287
288 { "dma_readq_full" },
289 { "dma_read_prioq_full" },
290 { "tx_comp_queue_full" },
291
292 { "ring_set_send_prod_index" },
293 { "ring_status_update" },
294 { "nic_irqs" },
295 { "nic_avoided_irqs" },
296 { "nic_tx_threshold_hit" }
297};
298
299static const struct {
300 const char string[ETH_GSTRING_LEN];
301} ethtool_test_keys[TG3_NUM_TEST] = {
302 { "nvram test (online) " },
303 { "link test (online) " },
304 { "register test (offline)" },
305 { "memory test (offline)" },
306 { "loopback test (offline)" },
307 { "interrupt test (offline)" },
308};
309
310static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
311{
312 writel(val, tp->regs + off);
313}
314
315static u32 tg3_read32(struct tg3 *tp, u32 off)
316{
317 return (readl(tp->regs + off));
318}
319
320static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
321{
322 writel(val, tp->aperegs + off);
323}
324
325static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
326{
327 return (readl(tp->aperegs + off));
328}
329
330static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
331{
332 unsigned long flags;
333
334 spin_lock_irqsave(&tp->indirect_lock, flags);
335 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
336 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
337 spin_unlock_irqrestore(&tp->indirect_lock, flags);
338}
339
340static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
341{
342 writel(val, tp->regs + off);
343 readl(tp->regs + off);
344}
345
346static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
347{
348 unsigned long flags;
349 u32 val;
350
351 spin_lock_irqsave(&tp->indirect_lock, flags);
352 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
353 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
354 spin_unlock_irqrestore(&tp->indirect_lock, flags);
355 return val;
356}
357
358static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
359{
360 unsigned long flags;
361
362 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
363 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
364 TG3_64BIT_REG_LOW, val);
365 return;
366 }
367 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
369 TG3_64BIT_REG_LOW, val);
370 return;
371 }
372
373 spin_lock_irqsave(&tp->indirect_lock, flags);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
375 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
376 spin_unlock_irqrestore(&tp->indirect_lock, flags);
377
378
379
380
381 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
382 (val == 0x1)) {
383 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
384 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
385 }
386}
387
388static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
389{
390 unsigned long flags;
391 u32 val;
392
393 spin_lock_irqsave(&tp->indirect_lock, flags);
394 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
395 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
396 spin_unlock_irqrestore(&tp->indirect_lock, flags);
397 return val;
398}
399
400
401
402
403
404
405static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
406{
407 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
408 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
409
410 tp->write32(tp, off, val);
411 else {
412
413 tg3_write32(tp, off, val);
414 if (usec_wait)
415 udelay(usec_wait);
416 tp->read32(tp, off);
417 }
418
419
420
421 if (usec_wait)
422 udelay(usec_wait);
423}
424
425static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
426{
427 tp->write32_mbox(tp, off, val);
428 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
429 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 tp->read32_mbox(tp, off);
431}
432
433static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
434{
435 void __iomem *mbox = tp->regs + off;
436 writel(val, mbox);
437 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
438 writel(val, mbox);
439 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
440 readl(mbox);
441}
442
443static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
444{
445 return (readl(tp->regs + off + GRCMBOX_BASE));
446}
447
448static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
449{
450 writel(val, tp->regs + off + GRCMBOX_BASE);
451}
452
453#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
454#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
455#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
456#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
457#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
458
459#define tw32(reg,val) tp->write32(tp, reg, val)
460#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
461#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
462#define tr32(reg) tp->read32(tp, reg)
463
464static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
465{
466 unsigned long flags;
467
468 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
469 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
470 return;
471
472 spin_lock_irqsave(&tp->indirect_lock, flags);
473 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
476
477
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
479 } else {
480 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
481 tw32_f(TG3PCI_MEM_WIN_DATA, val);
482
483
484 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
485 }
486 spin_unlock_irqrestore(&tp->indirect_lock, flags);
487}
488
489static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
490{
491 unsigned long flags;
492
493 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
494 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
495 *val = 0;
496 return;
497 }
498
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
503
504
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 } else {
507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 *val = tr32(TG3PCI_MEM_WIN_DATA);
509
510
511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
512 }
513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
514}
515
516static void tg3_ape_lock_init(struct tg3 *tp)
517{
518 int i;
519
520
521 for (i = 0; i < 8; i++)
522 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
523 APE_LOCK_GRANT_DRIVER);
524}
525
526static int tg3_ape_lock(struct tg3 *tp, int locknum)
527{
528 int i, off;
529 int ret = 0;
530 u32 status;
531
532 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
533 return 0;
534
535 switch (locknum) {
536 case TG3_APE_LOCK_MEM:
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 off = 4 * locknum;
543
544 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
545
546
547 for (i = 0; i < 100; i++) {
548 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
549 if (status == APE_LOCK_GRANT_DRIVER)
550 break;
551 udelay(10);
552 }
553
554 if (status != APE_LOCK_GRANT_DRIVER) {
555
556 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
557 APE_LOCK_GRANT_DRIVER);
558
559 ret = -EBUSY;
560 }
561
562 return ret;
563}
564
565static void tg3_ape_unlock(struct tg3 *tp, int locknum)
566{
567 int off;
568
569 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
570 return;
571
572 switch (locknum) {
573 case TG3_APE_LOCK_MEM:
574 break;
575 default:
576 return;
577 }
578
579 off = 4 * locknum;
580 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
581}
582
583static void tg3_disable_ints(struct tg3 *tp)
584{
585 tw32(TG3PCI_MISC_HOST_CTRL,
586 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
587 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
588}
589
590static inline void tg3_cond_int(struct tg3 *tp)
591{
592 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
593 (tp->hw_status->status & SD_STATUS_UPDATED))
594 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
595 else
596 tw32(HOSTCC_MODE, tp->coalesce_mode |
597 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
598}
599
600static void tg3_enable_ints(struct tg3 *tp)
601{
602 tp->irq_sync = 0;
603 wmb();
604
605 tw32(TG3PCI_MISC_HOST_CTRL,
606 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
607 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
608 (tp->last_tag << 24));
609 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611 (tp->last_tag << 24));
612 tg3_cond_int(tp);
613}
614
615static inline unsigned int tg3_has_work(struct tg3 *tp)
616{
617 struct tg3_hw_status *sblk = tp->hw_status;
618 unsigned int work_exists = 0;
619
620
621 if (!(tp->tg3_flags &
622 (TG3_FLAG_USE_LINKCHG_REG |
623 TG3_FLAG_POLL_SERDES))) {
624 if (sblk->status & SD_STATUS_LINK_CHG)
625 work_exists = 1;
626 }
627
628 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
629 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
630 work_exists = 1;
631
632 return work_exists;
633}
634
635
636
637
638
639
640static void tg3_restart_ints(struct tg3 *tp)
641{
642 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
643 tp->last_tag << 24);
644 mmiowb();
645
646
647
648
649
650 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
651 tg3_has_work(tp))
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
654}
655
656static inline void tg3_netif_stop(struct tg3 *tp)
657{
658 tp->dev->trans_start = jiffies;
659 napi_disable(&tp->napi);
660 netif_tx_disable(tp->dev);
661}
662
663static inline void tg3_netif_start(struct tg3 *tp)
664{
665 netif_wake_queue(tp->dev);
666
667
668
669
670 napi_enable(&tp->napi);
671 tp->hw_status->status |= SD_STATUS_UPDATED;
672 tg3_enable_ints(tp);
673}
674
675static void tg3_switch_clocks(struct tg3 *tp)
676{
677 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
678 u32 orig_clock_ctrl;
679
680 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
681 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
682 return;
683
684 orig_clock_ctrl = clock_ctrl;
685 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
686 CLOCK_CTRL_CLKRUN_OENABLE |
687 0x1f);
688 tp->pci_clock_ctrl = clock_ctrl;
689
690 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
691 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
692 tw32_wait_f(TG3PCI_CLOCK_CTRL,
693 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
694 }
695 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
696 tw32_wait_f(TG3PCI_CLOCK_CTRL,
697 clock_ctrl |
698 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
699 40);
700 tw32_wait_f(TG3PCI_CLOCK_CTRL,
701 clock_ctrl | (CLOCK_CTRL_ALTCLK),
702 40);
703 }
704 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
705}
706
707#define PHY_BUSY_LOOPS 5000
708
709static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
710{
711 u32 frame_val;
712 unsigned int loops;
713 int ret;
714
715 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
716 tw32_f(MAC_MI_MODE,
717 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
718 udelay(80);
719 }
720
721 *val = 0x0;
722
723 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
724 MI_COM_PHY_ADDR_MASK);
725 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
726 MI_COM_REG_ADDR_MASK);
727 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
728
729 tw32_f(MAC_MI_COM, frame_val);
730
731 loops = PHY_BUSY_LOOPS;
732 while (loops != 0) {
733 udelay(10);
734 frame_val = tr32(MAC_MI_COM);
735
736 if ((frame_val & MI_COM_BUSY) == 0) {
737 udelay(5);
738 frame_val = tr32(MAC_MI_COM);
739 break;
740 }
741 loops -= 1;
742 }
743
744 ret = -EBUSY;
745 if (loops != 0) {
746 *val = frame_val & MI_COM_DATA_MASK;
747 ret = 0;
748 }
749
750 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
751 tw32_f(MAC_MI_MODE, tp->mi_mode);
752 udelay(80);
753 }
754
755 return ret;
756}
757
758static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
759{
760 u32 frame_val;
761 unsigned int loops;
762 int ret;
763
764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
765 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
766 return 0;
767
768 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
769 tw32_f(MAC_MI_MODE,
770 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
771 udelay(80);
772 }
773
774 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
775 MI_COM_PHY_ADDR_MASK);
776 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
777 MI_COM_REG_ADDR_MASK);
778 frame_val |= (val & MI_COM_DATA_MASK);
779 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
780
781 tw32_f(MAC_MI_COM, frame_val);
782
783 loops = PHY_BUSY_LOOPS;
784 while (loops != 0) {
785 udelay(10);
786 frame_val = tr32(MAC_MI_COM);
787 if ((frame_val & MI_COM_BUSY) == 0) {
788 udelay(5);
789 frame_val = tr32(MAC_MI_COM);
790 break;
791 }
792 loops -= 1;
793 }
794
795 ret = -EBUSY;
796 if (loops != 0)
797 ret = 0;
798
799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE, tp->mi_mode);
801 udelay(80);
802 }
803
804 return ret;
805}
806
807static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
808{
809 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
810 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
811}
812
813static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
814{
815 u32 phy;
816
817 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
818 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
819 return;
820
821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
822 u32 ephy;
823
824 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
825 tg3_writephy(tp, MII_TG3_EPHY_TEST,
826 ephy | MII_TG3_EPHY_SHADOW_EN);
827 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
828 if (enable)
829 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
830 else
831 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
832 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
833 }
834 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
835 }
836 } else {
837 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
838 MII_TG3_AUXCTL_SHDWSEL_MISC;
839 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
840 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
841 if (enable)
842 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
843 else
844 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
845 phy |= MII_TG3_AUXCTL_MISC_WREN;
846 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
847 }
848 }
849}
850
851static void tg3_phy_set_wirespeed(struct tg3 *tp)
852{
853 u32 val;
854
855 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
856 return;
857
858 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
859 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
860 tg3_writephy(tp, MII_TG3_AUX_CTRL,
861 (val | (1 << 15) | (1 << 4)));
862}
863
864static int tg3_bmcr_reset(struct tg3 *tp)
865{
866 u32 phy_control;
867 int limit, err;
868
869
870
871
872 phy_control = BMCR_RESET;
873 err = tg3_writephy(tp, MII_BMCR, phy_control);
874 if (err != 0)
875 return -EBUSY;
876
877 limit = 5000;
878 while (limit--) {
879 err = tg3_readphy(tp, MII_BMCR, &phy_control);
880 if (err != 0)
881 return -EBUSY;
882
883 if ((phy_control & BMCR_RESET) == 0) {
884 udelay(40);
885 break;
886 }
887 udelay(10);
888 }
889 if (limit <= 0)
890 return -EBUSY;
891
892 return 0;
893}
894
895static void tg3_phy_apply_otp(struct tg3 *tp)
896{
897 u32 otp, phy;
898
899 if (!tp->phy_otp)
900 return;
901
902 otp = tp->phy_otp;
903
904
905 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
906 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
907 MII_TG3_AUXCTL_ACTL_TX_6DB;
908 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
909
910 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
911 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
912 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
913
914 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
915 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
916 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
917
918 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
919 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
920 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
921
922 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
923 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
924
925 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
926 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
927
928 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
929 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
930 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
931
932
933 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
934 MII_TG3_AUXCTL_ACTL_TX_6DB;
935 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
936}
937
938static int tg3_wait_macro_done(struct tg3 *tp)
939{
940 int limit = 100;
941
942 while (limit--) {
943 u32 tmp32;
944
945 if (!tg3_readphy(tp, 0x16, &tmp32)) {
946 if ((tmp32 & 0x1000) == 0)
947 break;
948 }
949 }
950 if (limit <= 0)
951 return -EBUSY;
952
953 return 0;
954}
955
956static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
957{
958 static const u32 test_pat[4][6] = {
959 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
960 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
961 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
962 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
963 };
964 int chan;
965
966 for (chan = 0; chan < 4; chan++) {
967 int i;
968
969 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
970 (chan * 0x2000) | 0x0200);
971 tg3_writephy(tp, 0x16, 0x0002);
972
973 for (i = 0; i < 6; i++)
974 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
975 test_pat[chan][i]);
976
977 tg3_writephy(tp, 0x16, 0x0202);
978 if (tg3_wait_macro_done(tp)) {
979 *resetp = 1;
980 return -EBUSY;
981 }
982
983 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
984 (chan * 0x2000) | 0x0200);
985 tg3_writephy(tp, 0x16, 0x0082);
986 if (tg3_wait_macro_done(tp)) {
987 *resetp = 1;
988 return -EBUSY;
989 }
990
991 tg3_writephy(tp, 0x16, 0x0802);
992 if (tg3_wait_macro_done(tp)) {
993 *resetp = 1;
994 return -EBUSY;
995 }
996
997 for (i = 0; i < 6; i += 2) {
998 u32 low, high;
999
1000 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1001 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1002 tg3_wait_macro_done(tp)) {
1003 *resetp = 1;
1004 return -EBUSY;
1005 }
1006 low &= 0x7fff;
1007 high &= 0x000f;
1008 if (low != test_pat[chan][i] ||
1009 high != test_pat[chan][i+1]) {
1010 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1011 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1012 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1013
1014 return -EBUSY;
1015 }
1016 }
1017 }
1018
1019 return 0;
1020}
1021
1022static int tg3_phy_reset_chanpat(struct tg3 *tp)
1023{
1024 int chan;
1025
1026 for (chan = 0; chan < 4; chan++) {
1027 int i;
1028
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1030 (chan * 0x2000) | 0x0200);
1031 tg3_writephy(tp, 0x16, 0x0002);
1032 for (i = 0; i < 6; i++)
1033 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1034 tg3_writephy(tp, 0x16, 0x0202);
1035 if (tg3_wait_macro_done(tp))
1036 return -EBUSY;
1037 }
1038
1039 return 0;
1040}
1041
1042static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1043{
1044 u32 reg32, phy9_orig;
1045 int retries, do_phy_reset, err;
1046
1047 retries = 10;
1048 do_phy_reset = 1;
1049 do {
1050 if (do_phy_reset) {
1051 err = tg3_bmcr_reset(tp);
1052 if (err)
1053 return err;
1054 do_phy_reset = 0;
1055 }
1056
1057
1058 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1059 continue;
1060
1061 reg32 |= 0x3000;
1062 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1063
1064
1065 tg3_writephy(tp, MII_BMCR,
1066 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1067
1068
1069 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1070 continue;
1071
1072 tg3_writephy(tp, MII_TG3_CTRL,
1073 (MII_TG3_CTRL_AS_MASTER |
1074 MII_TG3_CTRL_ENABLE_AS_MASTER));
1075
1076
1077 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1078
1079
1080 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1081 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1082
1083 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1084 if (!err)
1085 break;
1086 } while (--retries);
1087
1088 err = tg3_phy_reset_chanpat(tp);
1089 if (err)
1090 return err;
1091
1092 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1093 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1094
1095 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1096 tg3_writephy(tp, 0x16, 0x0000);
1097
1098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1100
1101 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1102 }
1103 else {
1104 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1105 }
1106
1107 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1108
1109 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1110 reg32 &= ~0x3000;
1111 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1112 } else if (!err)
1113 err = -EBUSY;
1114
1115 return err;
1116}
1117
1118static void tg3_link_report(struct tg3 *);
1119
1120
1121
1122
1123static int tg3_phy_reset(struct tg3 *tp)
1124{
1125 u32 cpmuctrl;
1126 u32 phy_status;
1127 int err;
1128
1129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1130 u32 val;
1131
1132 val = tr32(GRC_MISC_CFG);
1133 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1134 udelay(40);
1135 }
1136 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1137 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1138 if (err != 0)
1139 return -EBUSY;
1140
1141 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1142 netif_carrier_off(tp->dev);
1143 tg3_link_report(tp);
1144 }
1145
1146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1148 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1149 err = tg3_phy_reset_5703_4_5(tp);
1150 if (err)
1151 return err;
1152 goto out;
1153 }
1154
1155 cpmuctrl = 0;
1156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1157 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1158 cpmuctrl = tr32(TG3_CPMU_CTRL);
1159 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1160 tw32(TG3_CPMU_CTRL,
1161 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1162 }
1163
1164 err = tg3_bmcr_reset(tp);
1165 if (err)
1166 return err;
1167
1168 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1169 u32 phy;
1170
1171 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1172 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1173
1174 tw32(TG3_CPMU_CTRL, cpmuctrl);
1175 }
1176
1177 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1178 u32 val;
1179
1180 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1181 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1182 CPMU_LSPD_1000MB_MACCLK_12_5) {
1183 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1184 udelay(40);
1185 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1186 }
1187
1188
1189 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1190 MII_TG3_MISC_SHDW_WREN |
1191 MII_TG3_MISC_SHDW_APD_SEL |
1192 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1193 }
1194
1195 tg3_phy_apply_otp(tp);
1196
1197out:
1198 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1199 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1200 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1201 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1202 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1203 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1204 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1205 }
1206 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1207 tg3_writephy(tp, 0x1c, 0x8d68);
1208 tg3_writephy(tp, 0x1c, 0x8d68);
1209 }
1210 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1211 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1212 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1213 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1214 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1215 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1216 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1217 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1218 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1219 }
1220 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1221 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1222 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1223 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1224 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1225 tg3_writephy(tp, MII_TG3_TEST1,
1226 MII_TG3_TEST1_TRIM_EN | 0x4);
1227 } else
1228 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1229 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1230 }
1231
1232
1233 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1234
1235 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1236 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1237 u32 phy_reg;
1238
1239
1240 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1241 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1242 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1243 }
1244
1245
1246
1247
1248 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1249 u32 phy_reg;
1250
1251 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1252 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1253 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1254 }
1255
1256 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1257
1258 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1259 }
1260
1261 tg3_phy_toggle_automdix(tp, 1);
1262 tg3_phy_set_wirespeed(tp);
1263 return 0;
1264}
1265
1266static void tg3_frob_aux_power(struct tg3 *tp)
1267{
1268 struct tg3 *tp_peer = tp;
1269
1270 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1271 return;
1272
1273 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1274 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1275 struct net_device *dev_peer;
1276
1277 dev_peer = pci_get_drvdata(tp->pdev_peer);
1278
1279 if (!dev_peer)
1280 tp_peer = tp;
1281 else
1282 tp_peer = netdev_priv(dev_peer);
1283 }
1284
1285 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1286 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1287 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1288 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1291 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1292 (GRC_LCLCTRL_GPIO_OE0 |
1293 GRC_LCLCTRL_GPIO_OE1 |
1294 GRC_LCLCTRL_GPIO_OE2 |
1295 GRC_LCLCTRL_GPIO_OUTPUT0 |
1296 GRC_LCLCTRL_GPIO_OUTPUT1),
1297 100);
1298 } else {
1299 u32 no_gpio2;
1300 u32 grc_local_ctrl = 0;
1301
1302 if (tp_peer != tp &&
1303 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1304 return;
1305
1306
1307 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1308 ASIC_REV_5714) {
1309 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1310 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1311 grc_local_ctrl, 100);
1312 }
1313
1314
1315 no_gpio2 = tp->nic_sram_data_cfg &
1316 NIC_SRAM_DATA_CFG_NO_GPIO2;
1317
1318 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1319 GRC_LCLCTRL_GPIO_OE1 |
1320 GRC_LCLCTRL_GPIO_OE2 |
1321 GRC_LCLCTRL_GPIO_OUTPUT1 |
1322 GRC_LCLCTRL_GPIO_OUTPUT2;
1323 if (no_gpio2) {
1324 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1325 GRC_LCLCTRL_GPIO_OUTPUT2);
1326 }
1327 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1328 grc_local_ctrl, 100);
1329
1330 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1331
1332 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1333 grc_local_ctrl, 100);
1334
1335 if (!no_gpio2) {
1336 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1337 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1338 grc_local_ctrl, 100);
1339 }
1340 }
1341 } else {
1342 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1343 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1344 if (tp_peer != tp &&
1345 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1346 return;
1347
1348 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1349 (GRC_LCLCTRL_GPIO_OE1 |
1350 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1351
1352 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1353 GRC_LCLCTRL_GPIO_OE1, 100);
1354
1355 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1356 (GRC_LCLCTRL_GPIO_OE1 |
1357 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1358 }
1359 }
1360}
1361
1362static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1363{
1364 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1365 return 1;
1366 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1367 if (speed != SPEED_10)
1368 return 1;
1369 } else if (speed == SPEED_10)
1370 return 1;
1371
1372 return 0;
1373}
1374
1375static int tg3_setup_phy(struct tg3 *, int);
1376
1377#define RESET_KIND_SHUTDOWN 0
1378#define RESET_KIND_INIT 1
1379#define RESET_KIND_SUSPEND 2
1380
1381static void tg3_write_sig_post_reset(struct tg3 *, int);
1382static int tg3_halt_cpu(struct tg3 *, u32);
1383static int tg3_nvram_lock(struct tg3 *);
1384static void tg3_nvram_unlock(struct tg3 *);
1385
1386static void tg3_power_down_phy(struct tg3 *tp)
1387{
1388 u32 val;
1389
1390 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1392 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1393 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1394
1395 sg_dig_ctrl |=
1396 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1397 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1398 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1399 }
1400 return;
1401 }
1402
1403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1404 tg3_bmcr_reset(tp);
1405 val = tr32(GRC_MISC_CFG);
1406 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1407 udelay(40);
1408 return;
1409 } else {
1410 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1411 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1412 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1413 }
1414
1415
1416
1417
1418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1420 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1421 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1422 return;
1423
1424 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1425 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1426 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1427 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1428 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1429 }
1430
1431 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1432}
1433
1434static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1435{
1436 u32 misc_host_ctrl;
1437 u16 power_control, power_caps;
1438 int pm = tp->pm_cap;
1439
1440
1441
1442
1443 pci_write_config_dword(tp->pdev,
1444 TG3PCI_MISC_HOST_CTRL,
1445 tp->misc_host_ctrl);
1446
1447 pci_read_config_word(tp->pdev,
1448 pm + PCI_PM_CTRL,
1449 &power_control);
1450 power_control |= PCI_PM_CTRL_PME_STATUS;
1451 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1452 switch (state) {
1453 case PCI_D0:
1454 power_control |= 0;
1455 pci_write_config_word(tp->pdev,
1456 pm + PCI_PM_CTRL,
1457 power_control);
1458 udelay(100);
1459
1460
1461 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1462 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1463
1464 return 0;
1465
1466 case PCI_D1:
1467 power_control |= 1;
1468 break;
1469
1470 case PCI_D2:
1471 power_control |= 2;
1472 break;
1473
1474 case PCI_D3hot:
1475 power_control |= 3;
1476 break;
1477
1478 default:
1479 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1480 "requested.\n",
1481 tp->dev->name, state);
1482 return -EINVAL;
1483 };
1484
1485 power_control |= PCI_PM_CTRL_PME_ENABLE;
1486
1487 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1488 tw32(TG3PCI_MISC_HOST_CTRL,
1489 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1490
1491 if (tp->link_config.phy_is_low_power == 0) {
1492 tp->link_config.phy_is_low_power = 1;
1493 tp->link_config.orig_speed = tp->link_config.speed;
1494 tp->link_config.orig_duplex = tp->link_config.duplex;
1495 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1496 }
1497
1498 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1499 tp->link_config.speed = SPEED_10;
1500 tp->link_config.duplex = DUPLEX_HALF;
1501 tp->link_config.autoneg = AUTONEG_ENABLE;
1502 tg3_setup_phy(tp, 0);
1503 }
1504
1505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1506 u32 val;
1507
1508 val = tr32(GRC_VCPU_EXT_CTRL);
1509 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1510 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1511 int i;
1512 u32 val;
1513
1514 for (i = 0; i < 200; i++) {
1515 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1516 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1517 break;
1518 msleep(1);
1519 }
1520 }
1521 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1522 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1523 WOL_DRV_STATE_SHUTDOWN |
1524 WOL_DRV_WOL |
1525 WOL_SET_MAGIC_PKT);
1526
1527 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1528
1529 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1530 u32 mac_mode;
1531
1532 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1533 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1534 udelay(40);
1535
1536 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1537 mac_mode = MAC_MODE_PORT_MODE_GMII;
1538 else
1539 mac_mode = MAC_MODE_PORT_MODE_MII;
1540
1541 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1542 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1543 ASIC_REV_5700) {
1544 u32 speed = (tp->tg3_flags &
1545 TG3_FLAG_WOL_SPEED_100MB) ?
1546 SPEED_100 : SPEED_10;
1547 if (tg3_5700_link_polarity(tp, speed))
1548 mac_mode |= MAC_MODE_LINK_POLARITY;
1549 else
1550 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1551 }
1552 } else {
1553 mac_mode = MAC_MODE_PORT_MODE_TBI;
1554 }
1555
1556 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1557 tw32(MAC_LED_CTRL, tp->led_ctrl);
1558
1559 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1560 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1561 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1562
1563 tw32_f(MAC_MODE, mac_mode);
1564 udelay(100);
1565
1566 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1567 udelay(10);
1568 }
1569
1570 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1571 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1573 u32 base_val;
1574
1575 base_val = tp->pci_clock_ctrl;
1576 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1577 CLOCK_CTRL_TXCLK_DISABLE);
1578
1579 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1580 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1581 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1582 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1583 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1584
1585 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1586 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1587 u32 newbits1, newbits2;
1588
1589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1590 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1591 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1592 CLOCK_CTRL_TXCLK_DISABLE |
1593 CLOCK_CTRL_ALTCLK);
1594 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1595 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1596 newbits1 = CLOCK_CTRL_625_CORE;
1597 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1598 } else {
1599 newbits1 = CLOCK_CTRL_ALTCLK;
1600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1601 }
1602
1603 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1604 40);
1605
1606 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1607 40);
1608
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1610 u32 newbits3;
1611
1612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1614 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1615 CLOCK_CTRL_TXCLK_DISABLE |
1616 CLOCK_CTRL_44MHZ_CORE);
1617 } else {
1618 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1619 }
1620
1621 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1622 tp->pci_clock_ctrl | newbits3, 40);
1623 }
1624 }
1625
1626 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1627 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1628 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
1629 tg3_power_down_phy(tp);
1630
1631 tg3_frob_aux_power(tp);
1632
1633
1634 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1635 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1636 u32 val = tr32(0x7d00);
1637
1638 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1639 tw32(0x7d00, val);
1640 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1641 int err;
1642
1643 err = tg3_nvram_lock(tp);
1644 tg3_halt_cpu(tp, RX_CPU_BASE);
1645 if (!err)
1646 tg3_nvram_unlock(tp);
1647 }
1648 }
1649
1650 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1651
1652
1653 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1654 udelay(100);
1655
1656 return 0;
1657}
1658
1659static void tg3_link_report(struct tg3 *tp)
1660{
1661 if (!netif_carrier_ok(tp->dev)) {
1662 if (netif_msg_link(tp))
1663 printk(KERN_INFO PFX "%s: Link is down.\n",
1664 tp->dev->name);
1665 } else if (netif_msg_link(tp)) {
1666 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1667 tp->dev->name,
1668 (tp->link_config.active_speed == SPEED_1000 ?
1669 1000 :
1670 (tp->link_config.active_speed == SPEED_100 ?
1671 100 : 10)),
1672 (tp->link_config.active_duplex == DUPLEX_FULL ?
1673 "full" : "half"));
1674
1675 printk(KERN_INFO PFX
1676 "%s: Flow control is %s for TX and %s for RX.\n",
1677 tp->dev->name,
1678 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1679 "on" : "off",
1680 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1681 "on" : "off");
1682 }
1683}
1684
1685static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1686{
1687 u16 miireg;
1688
1689 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1690 miireg = ADVERTISE_PAUSE_CAP;
1691 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1692 miireg = ADVERTISE_PAUSE_ASYM;
1693 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1694 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1695 else
1696 miireg = 0;
1697
1698 return miireg;
1699}
1700
1701static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1702{
1703 u16 miireg;
1704
1705 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1706 miireg = ADVERTISE_1000XPAUSE;
1707 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1708 miireg = ADVERTISE_1000XPSE_ASYM;
1709 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1710 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1711 else
1712 miireg = 0;
1713
1714 return miireg;
1715}
1716
1717static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1718{
1719 u8 cap = 0;
1720
1721 if (lcladv & ADVERTISE_PAUSE_CAP) {
1722 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1723 if (rmtadv & LPA_PAUSE_CAP)
1724 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1725 else if (rmtadv & LPA_PAUSE_ASYM)
1726 cap = TG3_FLOW_CTRL_RX;
1727 } else {
1728 if (rmtadv & LPA_PAUSE_CAP)
1729 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1730 }
1731 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1732 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1733 cap = TG3_FLOW_CTRL_TX;
1734 }
1735
1736 return cap;
1737}
1738
1739static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1740{
1741 u8 cap = 0;
1742
1743 if (lcladv & ADVERTISE_1000XPAUSE) {
1744 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1745 if (rmtadv & LPA_1000XPAUSE)
1746 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1747 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1748 cap = TG3_FLOW_CTRL_RX;
1749 } else {
1750 if (rmtadv & LPA_1000XPAUSE)
1751 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1752 }
1753 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1754 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1755 cap = TG3_FLOW_CTRL_TX;
1756 }
1757
1758 return cap;
1759}
1760
1761static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1762{
1763 u8 new_tg3_flags = 0;
1764 u32 old_rx_mode = tp->rx_mode;
1765 u32 old_tx_mode = tp->tx_mode;
1766
1767 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1768 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1769 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1770 new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1771 remote_adv);
1772 else
1773 new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1774 remote_adv);
1775 } else {
1776 new_tg3_flags = tp->link_config.flowctrl;
1777 }
1778
1779 tp->link_config.active_flowctrl = new_tg3_flags;
1780
1781 if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1782 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1783 else
1784 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1785
1786 if (old_rx_mode != tp->rx_mode) {
1787 tw32_f(MAC_RX_MODE, tp->rx_mode);
1788 }
1789
1790 if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1791 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1792 else
1793 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1794
1795 if (old_tx_mode != tp->tx_mode) {
1796 tw32_f(MAC_TX_MODE, tp->tx_mode);
1797 }
1798}
1799
1800static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1801{
1802 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1803 case MII_TG3_AUX_STAT_10HALF:
1804 *speed = SPEED_10;
1805 *duplex = DUPLEX_HALF;
1806 break;
1807
1808 case MII_TG3_AUX_STAT_10FULL:
1809 *speed = SPEED_10;
1810 *duplex = DUPLEX_FULL;
1811 break;
1812
1813 case MII_TG3_AUX_STAT_100HALF:
1814 *speed = SPEED_100;
1815 *duplex = DUPLEX_HALF;
1816 break;
1817
1818 case MII_TG3_AUX_STAT_100FULL:
1819 *speed = SPEED_100;
1820 *duplex = DUPLEX_FULL;
1821 break;
1822
1823 case MII_TG3_AUX_STAT_1000HALF:
1824 *speed = SPEED_1000;
1825 *duplex = DUPLEX_HALF;
1826 break;
1827
1828 case MII_TG3_AUX_STAT_1000FULL:
1829 *speed = SPEED_1000;
1830 *duplex = DUPLEX_FULL;
1831 break;
1832
1833 default:
1834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1835 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1836 SPEED_10;
1837 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1838 DUPLEX_HALF;
1839 break;
1840 }
1841 *speed = SPEED_INVALID;
1842 *duplex = DUPLEX_INVALID;
1843 break;
1844 };
1845}
1846
1847static void tg3_phy_copper_begin(struct tg3 *tp)
1848{
1849 u32 new_adv;
1850 int i;
1851
1852 if (tp->link_config.phy_is_low_power) {
1853
1854
1855
1856 tg3_writephy(tp, MII_TG3_CTRL, 0);
1857
1858 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1859 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1860 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1861 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1862
1863 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1864 } else if (tp->link_config.speed == SPEED_INVALID) {
1865 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1866 tp->link_config.advertising &=
1867 ~(ADVERTISED_1000baseT_Half |
1868 ADVERTISED_1000baseT_Full);
1869
1870 new_adv = ADVERTISE_CSMA;
1871 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1872 new_adv |= ADVERTISE_10HALF;
1873 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1874 new_adv |= ADVERTISE_10FULL;
1875 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1876 new_adv |= ADVERTISE_100HALF;
1877 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1878 new_adv |= ADVERTISE_100FULL;
1879
1880 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1881
1882 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1883
1884 if (tp->link_config.advertising &
1885 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1886 new_adv = 0;
1887 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1888 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1889 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1890 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1891 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1892 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1893 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1894 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1895 MII_TG3_CTRL_ENABLE_AS_MASTER);
1896 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1897 } else {
1898 tg3_writephy(tp, MII_TG3_CTRL, 0);
1899 }
1900 } else {
1901 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1902 new_adv |= ADVERTISE_CSMA;
1903
1904
1905 if (tp->link_config.speed == SPEED_1000) {
1906 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1907
1908 if (tp->link_config.duplex == DUPLEX_FULL)
1909 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1910 else
1911 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1912 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1913 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1914 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1915 MII_TG3_CTRL_ENABLE_AS_MASTER);
1916 } else {
1917 if (tp->link_config.speed == SPEED_100) {
1918 if (tp->link_config.duplex == DUPLEX_FULL)
1919 new_adv |= ADVERTISE_100FULL;
1920 else
1921 new_adv |= ADVERTISE_100HALF;
1922 } else {
1923 if (tp->link_config.duplex == DUPLEX_FULL)
1924 new_adv |= ADVERTISE_10FULL;
1925 else
1926 new_adv |= ADVERTISE_10HALF;
1927 }
1928 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1929
1930 new_adv = 0;
1931 }
1932
1933 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1934 }
1935
1936 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1937 tp->link_config.speed != SPEED_INVALID) {
1938 u32 bmcr, orig_bmcr;
1939
1940 tp->link_config.active_speed = tp->link_config.speed;
1941 tp->link_config.active_duplex = tp->link_config.duplex;
1942
1943 bmcr = 0;
1944 switch (tp->link_config.speed) {
1945 default:
1946 case SPEED_10:
1947 break;
1948
1949 case SPEED_100:
1950 bmcr |= BMCR_SPEED100;
1951 break;
1952
1953 case SPEED_1000:
1954 bmcr |= TG3_BMCR_SPEED1000;
1955 break;
1956 };
1957
1958 if (tp->link_config.duplex == DUPLEX_FULL)
1959 bmcr |= BMCR_FULLDPLX;
1960
1961 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1962 (bmcr != orig_bmcr)) {
1963 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1964 for (i = 0; i < 1500; i++) {
1965 u32 tmp;
1966
1967 udelay(10);
1968 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1969 tg3_readphy(tp, MII_BMSR, &tmp))
1970 continue;
1971 if (!(tmp & BMSR_LSTATUS)) {
1972 udelay(40);
1973 break;
1974 }
1975 }
1976 tg3_writephy(tp, MII_BMCR, bmcr);
1977 udelay(40);
1978 }
1979 } else {
1980 tg3_writephy(tp, MII_BMCR,
1981 BMCR_ANENABLE | BMCR_ANRESTART);
1982 }
1983}
1984
1985static int tg3_init_5401phy_dsp(struct tg3 *tp)
1986{
1987 int err;
1988
1989
1990
1991 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1992
1993 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1994 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1995
1996 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1997 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1998
1999 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2000 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2001
2002 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2003 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2004
2005 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2006 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2007
2008 udelay(40);
2009
2010 return err;
2011}
2012
2013static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2014{
2015 u32 adv_reg, all_mask = 0;
2016
2017 if (mask & ADVERTISED_10baseT_Half)
2018 all_mask |= ADVERTISE_10HALF;
2019 if (mask & ADVERTISED_10baseT_Full)
2020 all_mask |= ADVERTISE_10FULL;
2021 if (mask & ADVERTISED_100baseT_Half)
2022 all_mask |= ADVERTISE_100HALF;
2023 if (mask & ADVERTISED_100baseT_Full)
2024 all_mask |= ADVERTISE_100FULL;
2025
2026 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2027 return 0;
2028
2029 if ((adv_reg & all_mask) != all_mask)
2030 return 0;
2031 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2032 u32 tg3_ctrl;
2033
2034 all_mask = 0;
2035 if (mask & ADVERTISED_1000baseT_Half)
2036 all_mask |= ADVERTISE_1000HALF;
2037 if (mask & ADVERTISED_1000baseT_Full)
2038 all_mask |= ADVERTISE_1000FULL;
2039
2040 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2041 return 0;
2042
2043 if ((tg3_ctrl & all_mask) != all_mask)
2044 return 0;
2045 }
2046 return 1;
2047}
2048
2049static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2050{
2051 u32 curadv, reqadv;
2052
2053 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2054 return 1;
2055
2056 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2057 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2058
2059 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2060 if (curadv != reqadv)
2061 return 0;
2062
2063 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2064 tg3_readphy(tp, MII_LPA, rmtadv);
2065 } else {
2066
2067
2068
2069
2070
2071
2072 if (curadv != reqadv) {
2073 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2074 ADVERTISE_PAUSE_ASYM);
2075 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2076 }
2077 }
2078
2079 return 1;
2080}
2081
2082static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2083{
2084 int current_link_up;
2085 u32 bmsr, dummy;
2086 u32 lcl_adv, rmt_adv;
2087 u16 current_speed;
2088 u8 current_duplex;
2089 int i, err;
2090
2091 tw32(MAC_EVENT, 0);
2092
2093 tw32_f(MAC_STATUS,
2094 (MAC_STATUS_SYNC_CHANGED |
2095 MAC_STATUS_CFG_CHANGED |
2096 MAC_STATUS_MI_COMPLETION |
2097 MAC_STATUS_LNKSTATE_CHANGED));
2098 udelay(40);
2099
2100 tp->mi_mode = MAC_MI_MODE_BASE;
2101 tw32_f(MAC_MI_MODE, tp->mi_mode);
2102 udelay(80);
2103
2104 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2105
2106
2107
2108
2109 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2112 netif_carrier_ok(tp->dev)) {
2113 tg3_readphy(tp, MII_BMSR, &bmsr);
2114 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2115 !(bmsr & BMSR_LSTATUS))
2116 force_reset = 1;
2117 }
2118 if (force_reset)
2119 tg3_phy_reset(tp);
2120
2121 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2122 tg3_readphy(tp, MII_BMSR, &bmsr);
2123 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2124 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2125 bmsr = 0;
2126
2127 if (!(bmsr & BMSR_LSTATUS)) {
2128 err = tg3_init_5401phy_dsp(tp);
2129 if (err)
2130 return err;
2131
2132 tg3_readphy(tp, MII_BMSR, &bmsr);
2133 for (i = 0; i < 1000; i++) {
2134 udelay(10);
2135 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2136 (bmsr & BMSR_LSTATUS)) {
2137 udelay(40);
2138 break;
2139 }
2140 }
2141
2142 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2143 !(bmsr & BMSR_LSTATUS) &&
2144 tp->link_config.active_speed == SPEED_1000) {
2145 err = tg3_phy_reset(tp);
2146 if (!err)
2147 err = tg3_init_5401phy_dsp(tp);
2148 if (err)
2149 return err;
2150 }
2151 }
2152 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2153 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2154
2155 tg3_writephy(tp, 0x15, 0x0a75);
2156 tg3_writephy(tp, 0x1c, 0x8c68);
2157 tg3_writephy(tp, 0x1c, 0x8d68);
2158 tg3_writephy(tp, 0x1c, 0x8c68);
2159 }
2160
2161
2162 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2163 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2164
2165 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2166 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2167 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2168 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2169
2170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2172 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2173 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2174 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2175 else
2176 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2177 }
2178
2179 current_link_up = 0;
2180 current_speed = SPEED_INVALID;
2181 current_duplex = DUPLEX_INVALID;
2182
2183 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2184 u32 val;
2185
2186 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2187 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2188 if (!(val & (1 << 10))) {
2189 val |= (1 << 10);
2190 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2191 goto relink;
2192 }
2193 }
2194
2195 bmsr = 0;
2196 for (i = 0; i < 100; i++) {
2197 tg3_readphy(tp, MII_BMSR, &bmsr);
2198 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2199 (bmsr & BMSR_LSTATUS))
2200 break;
2201 udelay(40);
2202 }
2203
2204 if (bmsr & BMSR_LSTATUS) {
2205 u32 aux_stat, bmcr;
2206
2207 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2208 for (i = 0; i < 2000; i++) {
2209 udelay(10);
2210 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2211 aux_stat)
2212 break;
2213 }
2214
2215 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2216 ¤t_speed,
2217 ¤t_duplex);
2218
2219 bmcr = 0;
2220 for (i = 0; i < 200; i++) {
2221 tg3_readphy(tp, MII_BMCR, &bmcr);
2222 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2223 continue;
2224 if (bmcr && bmcr != 0x7fff)
2225 break;
2226 udelay(10);
2227 }
2228
2229 lcl_adv = 0;
2230 rmt_adv = 0;
2231
2232 tp->link_config.active_speed = current_speed;
2233 tp->link_config.active_duplex = current_duplex;
2234
2235 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2236 if ((bmcr & BMCR_ANENABLE) &&
2237 tg3_copper_is_advertising_all(tp,
2238 tp->link_config.advertising)) {
2239 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2240 &rmt_adv))
2241 current_link_up = 1;
2242 }
2243 } else {
2244 if (!(bmcr & BMCR_ANENABLE) &&
2245 tp->link_config.speed == current_speed &&
2246 tp->link_config.duplex == current_duplex &&
2247 tp->link_config.flowctrl ==
2248 tp->link_config.active_flowctrl) {
2249 current_link_up = 1;
2250 }
2251 }
2252
2253 if (current_link_up == 1 &&
2254 tp->link_config.active_duplex == DUPLEX_FULL)
2255 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2256 }
2257
2258relink:
2259 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2260 u32 tmp;
2261
2262 tg3_phy_copper_begin(tp);
2263
2264 tg3_readphy(tp, MII_BMSR, &tmp);
2265 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2266 (tmp & BMSR_LSTATUS))
2267 current_link_up = 1;
2268 }
2269
2270 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2271 if (current_link_up == 1) {
2272 if (tp->link_config.active_speed == SPEED_100 ||
2273 tp->link_config.active_speed == SPEED_10)
2274 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2275 else
2276 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2277 } else
2278 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2279
2280 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2281 if (tp->link_config.active_duplex == DUPLEX_HALF)
2282 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2283
2284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2285 if (current_link_up == 1 &&
2286 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2287 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2288 else
2289 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2290 }
2291
2292
2293
2294
2295 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2296 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2297 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2298 tw32_f(MAC_MI_MODE, tp->mi_mode);
2299 udelay(80);
2300 }
2301
2302 tw32_f(MAC_MODE, tp->mac_mode);
2303 udelay(40);
2304
2305 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2306
2307 tw32_f(MAC_EVENT, 0);
2308 } else {
2309 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2310 }
2311 udelay(40);
2312
2313 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2314 current_link_up == 1 &&
2315 tp->link_config.active_speed == SPEED_1000 &&
2316 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2317 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2318 udelay(120);
2319 tw32_f(MAC_STATUS,
2320 (MAC_STATUS_SYNC_CHANGED |
2321 MAC_STATUS_CFG_CHANGED));
2322 udelay(40);
2323 tg3_write_mem(tp,
2324 NIC_SRAM_FIRMWARE_MBOX,
2325 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2326 }
2327
2328 if (current_link_up != netif_carrier_ok(tp->dev)) {
2329 if (current_link_up)
2330 netif_carrier_on(tp->dev);
2331 else
2332 netif_carrier_off(tp->dev);
2333 tg3_link_report(tp);
2334 }
2335
2336 return 0;
2337}
2338
2339struct tg3_fiber_aneginfo {
2340 int state;
2341#define ANEG_STATE_UNKNOWN 0
2342#define ANEG_STATE_AN_ENABLE 1
2343#define ANEG_STATE_RESTART_INIT 2
2344#define ANEG_STATE_RESTART 3
2345#define ANEG_STATE_DISABLE_LINK_OK 4
2346#define ANEG_STATE_ABILITY_DETECT_INIT 5
2347#define ANEG_STATE_ABILITY_DETECT 6
2348#define ANEG_STATE_ACK_DETECT_INIT 7
2349#define ANEG_STATE_ACK_DETECT 8
2350#define ANEG_STATE_COMPLETE_ACK_INIT 9
2351#define ANEG_STATE_COMPLETE_ACK 10
2352#define ANEG_STATE_IDLE_DETECT_INIT 11
2353#define ANEG_STATE_IDLE_DETECT 12
2354#define ANEG_STATE_LINK_OK 13
2355#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2356#define ANEG_STATE_NEXT_PAGE_WAIT 15
2357
2358 u32 flags;
2359#define MR_AN_ENABLE 0x00000001
2360#define MR_RESTART_AN 0x00000002
2361#define MR_AN_COMPLETE 0x00000004
2362#define MR_PAGE_RX 0x00000008
2363#define MR_NP_LOADED 0x00000010
2364#define MR_TOGGLE_TX 0x00000020
2365#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2366#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2367#define MR_LP_ADV_SYM_PAUSE 0x00000100
2368#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2369#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2370#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2371#define MR_LP_ADV_NEXT_PAGE 0x00001000
2372#define MR_TOGGLE_RX 0x00002000
2373#define MR_NP_RX 0x00004000
2374
2375#define MR_LINK_OK 0x80000000
2376
2377 unsigned long link_time, cur_time;
2378
2379 u32 ability_match_cfg;
2380 int ability_match_count;
2381
2382 char ability_match, idle_match, ack_match;
2383
2384 u32 txconfig, rxconfig;
2385#define ANEG_CFG_NP 0x00000080
2386#define ANEG_CFG_ACK 0x00000040
2387#define ANEG_CFG_RF2 0x00000020
2388#define ANEG_CFG_RF1 0x00000010
2389#define ANEG_CFG_PS2 0x00000001
2390#define ANEG_CFG_PS1 0x00008000
2391#define ANEG_CFG_HD 0x00004000
2392#define ANEG_CFG_FD 0x00002000
2393#define ANEG_CFG_INVAL 0x00001f06
2394
2395};
2396#define ANEG_OK 0
2397#define ANEG_DONE 1
2398#define ANEG_TIMER_ENAB 2
2399#define ANEG_FAILED -1
2400
2401#define ANEG_STATE_SETTLE_TIME 10000
2402
2403static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2404 struct tg3_fiber_aneginfo *ap)
2405{
2406 u16 flowctrl;
2407 unsigned long delta;
2408 u32 rx_cfg_reg;
2409 int ret;
2410
2411 if (ap->state == ANEG_STATE_UNKNOWN) {
2412 ap->rxconfig = 0;
2413 ap->link_time = 0;
2414 ap->cur_time = 0;
2415 ap->ability_match_cfg = 0;
2416 ap->ability_match_count = 0;
2417 ap->ability_match = 0;
2418 ap->idle_match = 0;
2419 ap->ack_match = 0;
2420 }
2421 ap->cur_time++;
2422
2423 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2424 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2425
2426 if (rx_cfg_reg != ap->ability_match_cfg) {
2427 ap->ability_match_cfg = rx_cfg_reg;
2428 ap->ability_match = 0;
2429 ap->ability_match_count = 0;
2430 } else {
2431 if (++ap->ability_match_count > 1) {
2432 ap->ability_match = 1;
2433 ap->ability_match_cfg = rx_cfg_reg;
2434 }
2435 }
2436 if (rx_cfg_reg & ANEG_CFG_ACK)
2437 ap->ack_match = 1;
2438 else
2439 ap->ack_match = 0;
2440
2441 ap->idle_match = 0;
2442 } else {
2443 ap->idle_match = 1;
2444 ap->ability_match_cfg = 0;
2445 ap->ability_match_count = 0;
2446 ap->ability_match = 0;
2447 ap->ack_match = 0;
2448
2449 rx_cfg_reg = 0;
2450 }
2451
2452 ap->rxconfig = rx_cfg_reg;
2453 ret = ANEG_OK;
2454
2455 switch(ap->state) {
2456 case ANEG_STATE_UNKNOWN:
2457 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2458 ap->state = ANEG_STATE_AN_ENABLE;
2459
2460
2461 case ANEG_STATE_AN_ENABLE:
2462 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2463 if (ap->flags & MR_AN_ENABLE) {
2464 ap->link_time = 0;
2465 ap->cur_time = 0;
2466 ap->ability_match_cfg = 0;
2467 ap->ability_match_count = 0;
2468 ap->ability_match = 0;
2469 ap->idle_match = 0;
2470 ap->ack_match = 0;
2471
2472 ap->state = ANEG_STATE_RESTART_INIT;
2473 } else {
2474 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2475 }
2476 break;
2477
2478 case ANEG_STATE_RESTART_INIT:
2479 ap->link_time = ap->cur_time;
2480 ap->flags &= ~(MR_NP_LOADED);
2481 ap->txconfig = 0;
2482 tw32(MAC_TX_AUTO_NEG, 0);
2483 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2484 tw32_f(MAC_MODE, tp->mac_mode);
2485 udelay(40);
2486
2487 ret = ANEG_TIMER_ENAB;
2488 ap->state = ANEG_STATE_RESTART;
2489
2490
2491 case ANEG_STATE_RESTART:
2492 delta = ap->cur_time - ap->link_time;
2493 if (delta > ANEG_STATE_SETTLE_TIME) {
2494 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2495 } else {
2496 ret = ANEG_TIMER_ENAB;
2497 }
2498 break;
2499
2500 case ANEG_STATE_DISABLE_LINK_OK:
2501 ret = ANEG_DONE;
2502 break;
2503
2504 case ANEG_STATE_ABILITY_DETECT_INIT:
2505 ap->flags &= ~(MR_TOGGLE_TX);
2506 ap->txconfig = ANEG_CFG_FD;
2507 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2508 if (flowctrl & ADVERTISE_1000XPAUSE)
2509 ap->txconfig |= ANEG_CFG_PS1;
2510 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2511 ap->txconfig |= ANEG_CFG_PS2;
2512 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2513 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2514 tw32_f(MAC_MODE, tp->mac_mode);
2515 udelay(40);
2516
2517 ap->state = ANEG_STATE_ABILITY_DETECT;
2518 break;
2519
2520 case ANEG_STATE_ABILITY_DETECT:
2521 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2522 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2523 }
2524 break;
2525
2526 case ANEG_STATE_ACK_DETECT_INIT:
2527 ap->txconfig |= ANEG_CFG_ACK;
2528 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2529 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2530 tw32_f(MAC_MODE, tp->mac_mode);
2531 udelay(40);
2532
2533 ap->state = ANEG_STATE_ACK_DETECT;
2534
2535
2536 case ANEG_STATE_ACK_DETECT:
2537 if (ap->ack_match != 0) {
2538 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2539 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2540 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2541 } else {
2542 ap->state = ANEG_STATE_AN_ENABLE;
2543 }
2544 } else if (ap->ability_match != 0 &&
2545 ap->rxconfig == 0) {
2546 ap->state = ANEG_STATE_AN_ENABLE;
2547 }
2548 break;
2549
2550 case ANEG_STATE_COMPLETE_ACK_INIT:
2551 if (ap->rxconfig & ANEG_CFG_INVAL) {
2552 ret = ANEG_FAILED;
2553 break;
2554 }
2555 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2556 MR_LP_ADV_HALF_DUPLEX |
2557 MR_LP_ADV_SYM_PAUSE |
2558 MR_LP_ADV_ASYM_PAUSE |
2559 MR_LP_ADV_REMOTE_FAULT1 |
2560 MR_LP_ADV_REMOTE_FAULT2 |
2561 MR_LP_ADV_NEXT_PAGE |
2562 MR_TOGGLE_RX |
2563 MR_NP_RX);
2564 if (ap->rxconfig & ANEG_CFG_FD)
2565 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2566 if (ap->rxconfig & ANEG_CFG_HD)
2567 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2568 if (ap->rxconfig & ANEG_CFG_PS1)
2569 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2570 if (ap->rxconfig & ANEG_CFG_PS2)
2571 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2572 if (ap->rxconfig & ANEG_CFG_RF1)
2573 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2574 if (ap->rxconfig & ANEG_CFG_RF2)
2575 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2576 if (ap->rxconfig & ANEG_CFG_NP)
2577 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2578
2579 ap->link_time = ap->cur_time;
2580
2581 ap->flags ^= (MR_TOGGLE_TX);
2582 if (ap->rxconfig & 0x0008)
2583 ap->flags |= MR_TOGGLE_RX;
2584 if (ap->rxconfig & ANEG_CFG_NP)
2585 ap->flags |= MR_NP_RX;
2586 ap->flags |= MR_PAGE_RX;
2587
2588 ap->state = ANEG_STATE_COMPLETE_ACK;
2589 ret = ANEG_TIMER_ENAB;
2590 break;
2591
2592 case ANEG_STATE_COMPLETE_ACK:
2593 if (ap->ability_match != 0 &&
2594 ap->rxconfig == 0) {
2595 ap->state = ANEG_STATE_AN_ENABLE;
2596 break;
2597 }
2598 delta = ap->cur_time - ap->link_time;
2599 if (delta > ANEG_STATE_SETTLE_TIME) {
2600 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2601 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2602 } else {
2603 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2604 !(ap->flags & MR_NP_RX)) {
2605 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2606 } else {
2607 ret = ANEG_FAILED;
2608 }
2609 }
2610 }
2611 break;
2612
2613 case ANEG_STATE_IDLE_DETECT_INIT:
2614 ap->link_time = ap->cur_time;
2615 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2616 tw32_f(MAC_MODE, tp->mac_mode);
2617 udelay(40);
2618
2619 ap->state = ANEG_STATE_IDLE_DETECT;
2620 ret = ANEG_TIMER_ENAB;
2621 break;
2622
2623 case ANEG_STATE_IDLE_DETECT:
2624 if (ap->ability_match != 0 &&
2625 ap->rxconfig == 0) {
2626 ap->state = ANEG_STATE_AN_ENABLE;
2627 break;
2628 }
2629 delta = ap->cur_time - ap->link_time;
2630 if (delta > ANEG_STATE_SETTLE_TIME) {
2631
2632 ap->state = ANEG_STATE_LINK_OK;
2633 }
2634 break;
2635
2636 case ANEG_STATE_LINK_OK:
2637 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2638 ret = ANEG_DONE;
2639 break;
2640
2641 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2642
2643 break;
2644
2645 case ANEG_STATE_NEXT_PAGE_WAIT:
2646
2647 break;
2648
2649 default:
2650 ret = ANEG_FAILED;
2651 break;
2652 };
2653
2654 return ret;
2655}
2656
2657static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
2658{
2659 int res = 0;
2660 struct tg3_fiber_aneginfo aninfo;
2661 int status = ANEG_FAILED;
2662 unsigned int tick;
2663 u32 tmp;
2664
2665 tw32_f(MAC_TX_AUTO_NEG, 0);
2666
2667 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2668 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2669 udelay(40);
2670
2671 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2672 udelay(40);
2673
2674 memset(&aninfo, 0, sizeof(aninfo));
2675 aninfo.flags |= MR_AN_ENABLE;
2676 aninfo.state = ANEG_STATE_UNKNOWN;
2677 aninfo.cur_time = 0;
2678 tick = 0;
2679 while (++tick < 195000) {
2680 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2681 if (status == ANEG_DONE || status == ANEG_FAILED)
2682 break;
2683
2684 udelay(1);
2685 }
2686
2687 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2688 tw32_f(MAC_MODE, tp->mac_mode);
2689 udelay(40);
2690
2691 *txflags = aninfo.txconfig;
2692 *rxflags = aninfo.flags;
2693
2694 if (status == ANEG_DONE &&
2695 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2696 MR_LP_ADV_FULL_DUPLEX)))
2697 res = 1;
2698
2699 return res;
2700}
2701
2702static void tg3_init_bcm8002(struct tg3 *tp)
2703{
2704 u32 mac_status = tr32(MAC_STATUS);
2705 int i;
2706
2707
2708 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2709 !(mac_status & MAC_STATUS_PCS_SYNCED))
2710 return;
2711
2712
2713 tg3_writephy(tp, 0x16, 0x8007);
2714
2715
2716 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2717
2718
2719
2720 for (i = 0; i < 500; i++)
2721 udelay(10);
2722
2723
2724 tg3_writephy(tp, 0x10, 0x8411);
2725
2726
2727 tg3_writephy(tp, 0x11, 0x0a10);
2728
2729 tg3_writephy(tp, 0x18, 0x00a0);
2730 tg3_writephy(tp, 0x16, 0x41ff);
2731
2732
2733 tg3_writephy(tp, 0x13, 0x0400);
2734 udelay(40);
2735 tg3_writephy(tp, 0x13, 0x0000);
2736
2737 tg3_writephy(tp, 0x11, 0x0a50);
2738 udelay(40);
2739 tg3_writephy(tp, 0x11, 0x0a10);
2740
2741
2742
2743 for (i = 0; i < 15000; i++)
2744 udelay(10);
2745
2746
2747
2748
2749 tg3_writephy(tp, 0x10, 0x8011);
2750}
2751
2752static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2753{
2754 u16 flowctrl;
2755 u32 sg_dig_ctrl, sg_dig_status;
2756 u32 serdes_cfg, expected_sg_dig_ctrl;
2757 int workaround, port_a;
2758 int current_link_up;
2759
2760 serdes_cfg = 0;
2761 expected_sg_dig_ctrl = 0;
2762 workaround = 0;
2763 port_a = 1;
2764 current_link_up = 0;
2765
2766 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2767 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2768 workaround = 1;
2769 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2770 port_a = 0;
2771
2772
2773
2774 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2775 }
2776
2777 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2778
2779 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2780 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
2781 if (workaround) {
2782 u32 val = serdes_cfg;
2783
2784 if (port_a)
2785 val |= 0xc010000;
2786 else
2787 val |= 0x4010000;
2788 tw32_f(MAC_SERDES_CFG, val);
2789 }
2790
2791 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2792 }
2793 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2794 tg3_setup_flow_control(tp, 0, 0);
2795 current_link_up = 1;
2796 }
2797 goto out;
2798 }
2799
2800
2801 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
2802
2803 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2804 if (flowctrl & ADVERTISE_1000XPAUSE)
2805 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
2806 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2807 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
2808
2809 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2810 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2811 tp->serdes_counter &&
2812 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2813 MAC_STATUS_RCVD_CFG)) ==
2814 MAC_STATUS_PCS_SYNCED)) {
2815 tp->serdes_counter--;
2816 current_link_up = 1;
2817 goto out;
2818 }
2819restart_autoneg:
2820 if (workaround)
2821 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2822 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
2823 udelay(5);
2824 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2825
2826 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2827 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2828 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2829 MAC_STATUS_SIGNAL_DET)) {
2830 sg_dig_status = tr32(SG_DIG_STATUS);
2831 mac_status = tr32(MAC_STATUS);
2832
2833 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
2834 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2835 u32 local_adv = 0, remote_adv = 0;
2836
2837 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
2838 local_adv |= ADVERTISE_1000XPAUSE;
2839 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
2840 local_adv |= ADVERTISE_1000XPSE_ASYM;
2841
2842 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
2843 remote_adv |= LPA_1000XPAUSE;
2844 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
2845 remote_adv |= LPA_1000XPAUSE_ASYM;
2846
2847 tg3_setup_flow_control(tp, local_adv, remote_adv);
2848 current_link_up = 1;
2849 tp->serdes_counter = 0;
2850 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2851 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
2852 if (tp->serdes_counter)
2853 tp->serdes_counter--;
2854 else {
2855 if (workaround) {
2856 u32 val = serdes_cfg;
2857
2858 if (port_a)
2859 val |= 0xc010000;
2860 else
2861 val |= 0x4010000;
2862
2863 tw32_f(MAC_SERDES_CFG, val);
2864 }
2865
2866 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2867 udelay(40);
2868
2869
2870
2871
2872 mac_status = tr32(MAC_STATUS);
2873 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2874 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2875 tg3_setup_flow_control(tp, 0, 0);
2876 current_link_up = 1;
2877 tp->tg3_flags2 |=
2878 TG3_FLG2_PARALLEL_DETECT;
2879 tp->serdes_counter =
2880 SERDES_PARALLEL_DET_TIMEOUT;
2881 } else
2882 goto restart_autoneg;
2883 }
2884 }
2885 } else {
2886 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2887 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2888 }
2889
2890out:
2891 return current_link_up;
2892}
2893
2894static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2895{
2896 int current_link_up = 0;
2897
2898 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2899 goto out;
2900
2901 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2902 u32 txflags, rxflags;
2903 int i;
2904
2905 if (fiber_autoneg(tp, &txflags, &rxflags)) {
2906 u32 local_adv = 0, remote_adv = 0;
2907
2908 if (txflags & ANEG_CFG_PS1)
2909 local_adv |= ADVERTISE_1000XPAUSE;
2910 if (txflags & ANEG_CFG_PS2)
2911 local_adv |= ADVERTISE_1000XPSE_ASYM;
2912
2913 if (rxflags & MR_LP_ADV_SYM_PAUSE)
2914 remote_adv |= LPA_1000XPAUSE;
2915 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
2916 remote_adv |= LPA_1000XPAUSE_ASYM;
2917
2918 tg3_setup_flow_control(tp, local_adv, remote_adv);
2919
2920 current_link_up = 1;
2921 }
2922 for (i = 0; i < 30; i++) {
2923 udelay(20);
2924 tw32_f(MAC_STATUS,
2925 (MAC_STATUS_SYNC_CHANGED |
2926 MAC_STATUS_CFG_CHANGED));
2927 udelay(40);
2928 if ((tr32(MAC_STATUS) &
2929 (MAC_STATUS_SYNC_CHANGED |
2930 MAC_STATUS_CFG_CHANGED)) == 0)
2931 break;
2932 }
2933
2934 mac_status = tr32(MAC_STATUS);
2935 if (current_link_up == 0 &&
2936 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2937 !(mac_status & MAC_STATUS_RCVD_CFG))
2938 current_link_up = 1;
2939 } else {
2940 tg3_setup_flow_control(tp, 0, 0);
2941
2942
2943 current_link_up = 1;
2944
2945 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2946 udelay(40);
2947
2948 tw32_f(MAC_MODE, tp->mac_mode);
2949 udelay(40);
2950 }
2951
2952out:
2953 return current_link_up;
2954}
2955
2956static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2957{
2958 u32 orig_pause_cfg;
2959 u16 orig_active_speed;
2960 u8 orig_active_duplex;
2961 u32 mac_status;
2962 int current_link_up;
2963 int i;
2964
2965 orig_pause_cfg = tp->link_config.active_flowctrl;
2966 orig_active_speed = tp->link_config.active_speed;
2967 orig_active_duplex = tp->link_config.active_duplex;
2968
2969 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2970 netif_carrier_ok(tp->dev) &&
2971 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2972 mac_status = tr32(MAC_STATUS);
2973 mac_status &= (MAC_STATUS_PCS_SYNCED |
2974 MAC_STATUS_SIGNAL_DET |
2975 MAC_STATUS_CFG_CHANGED |
2976 MAC_STATUS_RCVD_CFG);
2977 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2978 MAC_STATUS_SIGNAL_DET)) {
2979 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2980 MAC_STATUS_CFG_CHANGED));
2981 return 0;
2982 }
2983 }
2984
2985 tw32_f(MAC_TX_AUTO_NEG, 0);
2986
2987 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2988 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2989 tw32_f(MAC_MODE, tp->mac_mode);
2990 udelay(40);
2991
2992 if (tp->phy_id == PHY_ID_BCM8002)
2993 tg3_init_bcm8002(tp);
2994
2995
2996 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2997 udelay(40);
2998
2999 current_link_up = 0;
3000 mac_status = tr32(MAC_STATUS);
3001
3002 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3003 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3004 else
3005 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3006
3007 tp->hw_status->status =
3008 (SD_STATUS_UPDATED |
3009 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3010
3011 for (i = 0; i < 100; i++) {
3012 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3013 MAC_STATUS_CFG_CHANGED));
3014 udelay(5);
3015 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3016 MAC_STATUS_CFG_CHANGED |
3017 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3018 break;
3019 }
3020
3021 mac_status = tr32(MAC_STATUS);
3022 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3023 current_link_up = 0;
3024 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3025 tp->serdes_counter == 0) {
3026 tw32_f(MAC_MODE, (tp->mac_mode |
3027 MAC_MODE_SEND_CONFIGS));
3028 udelay(1);
3029 tw32_f(MAC_MODE, tp->mac_mode);
3030 }
3031 }
3032
3033 if (current_link_up == 1) {
3034 tp->link_config.active_speed = SPEED_1000;
3035 tp->link_config.active_duplex = DUPLEX_FULL;
3036 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3037 LED_CTRL_LNKLED_OVERRIDE |
3038 LED_CTRL_1000MBPS_ON));
3039 } else {
3040 tp->link_config.active_speed = SPEED_INVALID;
3041 tp->link_config.active_duplex = DUPLEX_INVALID;
3042 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3043 LED_CTRL_LNKLED_OVERRIDE |
3044 LED_CTRL_TRAFFIC_OVERRIDE));
3045 }
3046
3047 if (current_link_up != netif_carrier_ok(tp->dev)) {
3048 if (current_link_up)
3049 netif_carrier_on(tp->dev);
3050 else
3051 netif_carrier_off(tp->dev);
3052 tg3_link_report(tp);
3053 } else {
3054 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3055 if (orig_pause_cfg != now_pause_cfg ||
3056 orig_active_speed != tp->link_config.active_speed ||
3057 orig_active_duplex != tp->link_config.active_duplex)
3058 tg3_link_report(tp);
3059 }
3060
3061 return 0;
3062}
3063
3064static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3065{
3066 int current_link_up, err = 0;
3067 u32 bmsr, bmcr;
3068 u16 current_speed;
3069 u8 current_duplex;
3070 u32 local_adv, remote_adv;
3071
3072 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3073 tw32_f(MAC_MODE, tp->mac_mode);
3074 udelay(40);
3075
3076 tw32(MAC_EVENT, 0);
3077
3078 tw32_f(MAC_STATUS,
3079 (MAC_STATUS_SYNC_CHANGED |
3080 MAC_STATUS_CFG_CHANGED |
3081 MAC_STATUS_MI_COMPLETION |
3082 MAC_STATUS_LNKSTATE_CHANGED));
3083 udelay(40);
3084
3085 if (force_reset)
3086 tg3_phy_reset(tp);
3087
3088 current_link_up = 0;
3089 current_speed = SPEED_INVALID;
3090 current_duplex = DUPLEX_INVALID;
3091
3092 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3093 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3095 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3096 bmsr |= BMSR_LSTATUS;
3097 else
3098 bmsr &= ~BMSR_LSTATUS;
3099 }
3100
3101 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3102
3103 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3104 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3105 tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
3106
3107 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3108 u32 adv, new_adv;
3109
3110 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3111 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3112 ADVERTISE_1000XPAUSE |
3113 ADVERTISE_1000XPSE_ASYM |
3114 ADVERTISE_SLCT);
3115
3116 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3117
3118 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3119 new_adv |= ADVERTISE_1000XHALF;
3120 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3121 new_adv |= ADVERTISE_1000XFULL;
3122
3123 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3124 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3125 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3126 tg3_writephy(tp, MII_BMCR, bmcr);
3127
3128 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3129 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3130 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3131
3132 return err;
3133 }
3134 } else {
3135 u32 new_bmcr;
3136
3137 bmcr &= ~BMCR_SPEED1000;
3138 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3139
3140 if (tp->link_config.duplex == DUPLEX_FULL)
3141 new_bmcr |= BMCR_FULLDPLX;
3142
3143 if (new_bmcr != bmcr) {
3144
3145
3146
3147 new_bmcr |= BMCR_SPEED1000;
3148
3149
3150 if (netif_carrier_ok(tp->dev)) {
3151 u32 adv;
3152
3153 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3154 adv &= ~(ADVERTISE_1000XFULL |
3155 ADVERTISE_1000XHALF |
3156 ADVERTISE_SLCT);
3157 tg3_writephy(tp, MII_ADVERTISE, adv);
3158 tg3_writephy(tp, MII_BMCR, bmcr |
3159 BMCR_ANRESTART |
3160 BMCR_ANENABLE);
3161 udelay(10);
3162 netif_carrier_off(tp->dev);
3163 }
3164 tg3_writephy(tp, MII_BMCR, new_bmcr);
3165 bmcr = new_bmcr;
3166 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3167 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3168 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3169 ASIC_REV_5714) {
3170 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3171 bmsr |= BMSR_LSTATUS;
3172 else
3173 bmsr &= ~BMSR_LSTATUS;
3174 }
3175 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3176 }
3177 }
3178
3179 if (bmsr & BMSR_LSTATUS) {
3180 current_speed = SPEED_1000;
3181 current_link_up = 1;
3182 if (bmcr & BMCR_FULLDPLX)
3183 current_duplex = DUPLEX_FULL;
3184 else
3185 current_duplex = DUPLEX_HALF;
3186
3187 local_adv = 0;
3188 remote_adv = 0;
3189
3190 if (bmcr & BMCR_ANENABLE) {
3191 u32 common;
3192
3193 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3194 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3195 common = local_adv & remote_adv;
3196 if (common & (ADVERTISE_1000XHALF |
3197 ADVERTISE_1000XFULL)) {
3198 if (common & ADVERTISE_1000XFULL)
3199 current_duplex = DUPLEX_FULL;
3200 else
3201 current_duplex = DUPLEX_HALF;
3202 }
3203 else
3204 current_link_up = 0;
3205 }
3206 }
3207
3208 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3209 tg3_setup_flow_control(tp, local_adv, remote_adv);
3210
3211 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3212 if (tp->link_config.active_duplex == DUPLEX_HALF)
3213 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3214
3215 tw32_f(MAC_MODE, tp->mac_mode);
3216 udelay(40);
3217
3218 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3219
3220 tp->link_config.active_speed = current_speed;
3221 tp->link_config.active_duplex = current_duplex;
3222
3223 if (current_link_up != netif_carrier_ok(tp->dev)) {
3224 if (current_link_up)
3225 netif_carrier_on(tp->dev);
3226 else {
3227 netif_carrier_off(tp->dev);
3228 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3229 }
3230 tg3_link_report(tp);
3231 }
3232 return err;
3233}
3234
3235static void tg3_serdes_parallel_detect(struct tg3 *tp)
3236{
3237 if (tp->serdes_counter) {
3238
3239 tp->serdes_counter--;
3240 return;
3241 }
3242 if (!netif_carrier_ok(tp->dev) &&
3243 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3244 u32 bmcr;
3245
3246 tg3_readphy(tp, MII_BMCR, &bmcr);
3247 if (bmcr & BMCR_ANENABLE) {
3248 u32 phy1, phy2;
3249
3250
3251 tg3_writephy(tp, 0x1c, 0x7c00);
3252 tg3_readphy(tp, 0x1c, &phy1);
3253
3254
3255 tg3_writephy(tp, 0x17, 0x0f01);
3256 tg3_readphy(tp, 0x15, &phy2);
3257 tg3_readphy(tp, 0x15, &phy2);
3258
3259 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3260
3261
3262
3263
3264
3265 bmcr &= ~BMCR_ANENABLE;
3266 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3267 tg3_writephy(tp, MII_BMCR, bmcr);
3268 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3269 }
3270 }
3271 }
3272 else if (netif_carrier_ok(tp->dev) &&
3273 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3274 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3275 u32 phy2;
3276
3277
3278 tg3_writephy(tp, 0x17, 0x0f01);
3279 tg3_readphy(tp, 0x15, &phy2);
3280 if (phy2 & 0x20) {
3281 u32 bmcr;
3282
3283
3284 tg3_readphy(tp, MII_BMCR, &bmcr);
3285 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3286
3287 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3288
3289 }
3290 }
3291}
3292
3293static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3294{
3295 int err;
3296
3297 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3298 err = tg3_setup_fiber_phy(tp, force_reset);
3299 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3300 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3301 } else {
3302 err = tg3_setup_copper_phy(tp, force_reset);
3303 }
3304
3305 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3306 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3307 u32 val, scale;
3308
3309 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3310 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3311 scale = 65;
3312 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3313 scale = 6;
3314 else
3315 scale = 12;
3316
3317 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3318 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3319 tw32(GRC_MISC_CFG, val);
3320 }
3321
3322 if (tp->link_config.active_speed == SPEED_1000 &&
3323 tp->link_config.active_duplex == DUPLEX_HALF)
3324 tw32(MAC_TX_LENGTHS,
3325 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3326 (6 << TX_LENGTHS_IPG_SHIFT) |
3327 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3328 else
3329 tw32(MAC_TX_LENGTHS,
3330 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3331 (6 << TX_LENGTHS_IPG_SHIFT) |
3332 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3333
3334 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3335 if (netif_carrier_ok(tp->dev)) {
3336 tw32(HOSTCC_STAT_COAL_TICKS,
3337 tp->coal.stats_block_coalesce_usecs);
3338 } else {
3339 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3340 }
3341 }
3342
3343 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3344 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3345 if (!netif_carrier_ok(tp->dev))
3346 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3347 tp->pwrmgmt_thresh;
3348 else
3349 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3350 tw32(PCIE_PWR_MGMT_THRESH, val);
3351 }
3352
3353 return err;
3354}
3355
3356
3357
3358
3359
3360
3361
3362static void tg3_tx_recover(struct tg3 *tp)
3363{
3364 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3365 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3366
3367 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3368 "mapped I/O cycles to the network device, attempting to "
3369 "recover. Please report the problem to the driver maintainer "
3370 "and include system chipset information.\n", tp->dev->name);
3371
3372 spin_lock(&tp->lock);
3373 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3374 spin_unlock(&tp->lock);
3375}
3376
3377static inline u32 tg3_tx_avail(struct tg3 *tp)
3378{
3379 smp_mb();
3380 return (tp->tx_pending -
3381 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3382}
3383
3384
3385
3386
3387
3388static void tg3_tx(struct tg3 *tp)
3389{
3390 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3391 u32 sw_idx = tp->tx_cons;
3392
3393 while (sw_idx != hw_idx) {
3394 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3395 struct sk_buff *skb = ri->skb;
3396 int i, tx_bug = 0;
3397
3398 if (unlikely(skb == NULL)) {
3399 tg3_tx_recover(tp);
3400 return;
3401 }
3402
3403 pci_unmap_single(tp->pdev,
3404 pci_unmap_addr(ri, mapping),
3405 skb_headlen(skb),
3406 PCI_DMA_TODEVICE);
3407
3408 ri->skb = NULL;
3409
3410 sw_idx = NEXT_TX(sw_idx);
3411
3412 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3413 ri = &tp->tx_buffers[sw_idx];
3414 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3415 tx_bug = 1;
3416
3417 pci_unmap_page(tp->pdev,
3418 pci_unmap_addr(ri, mapping),
3419 skb_shinfo(skb)->frags[i].size,
3420 PCI_DMA_TODEVICE);
3421
3422 sw_idx = NEXT_TX(sw_idx);
3423 }
3424
3425 dev_kfree_skb(skb);
3426
3427 if (unlikely(tx_bug)) {
3428 tg3_tx_recover(tp);
3429 return;
3430 }
3431 }
3432
3433 tp->tx_cons = sw_idx;
3434
3435
3436
3437
3438
3439
3440 smp_mb();
3441
3442 if (unlikely(netif_queue_stopped(tp->dev) &&
3443 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3444 netif_tx_lock(tp->dev);
3445 if (netif_queue_stopped(tp->dev) &&
3446 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3447 netif_wake_queue(tp->dev);
3448 netif_tx_unlock(tp->dev);
3449 }
3450}
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3464 int src_idx, u32 dest_idx_unmasked)
3465{
3466 struct tg3_rx_buffer_desc *desc;
3467 struct ring_info *map, *src_map;
3468 struct sk_buff *skb;
3469 dma_addr_t mapping;
3470 int skb_size, dest_idx;
3471
3472 src_map = NULL;
3473 switch (opaque_key) {
3474 case RXD_OPAQUE_RING_STD:
3475 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3476 desc = &tp->rx_std[dest_idx];
3477 map = &tp->rx_std_buffers[dest_idx];
3478 if (src_idx >= 0)
3479 src_map = &tp->rx_std_buffers[src_idx];
3480 skb_size = tp->rx_pkt_buf_sz;
3481 break;
3482
3483 case RXD_OPAQUE_RING_JUMBO:
3484 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3485 desc = &tp->rx_jumbo[dest_idx];
3486 map = &tp->rx_jumbo_buffers[dest_idx];
3487 if (src_idx >= 0)
3488 src_map = &tp->rx_jumbo_buffers[src_idx];
3489 skb_size = RX_JUMBO_PKT_BUF_SZ;
3490 break;
3491
3492 default:
3493 return -EINVAL;
3494 };
3495
3496
3497
3498
3499
3500
3501
3502 skb = netdev_alloc_skb(tp->dev, skb_size);
3503 if (skb == NULL)
3504 return -ENOMEM;
3505
3506 skb_reserve(skb, tp->rx_offset);
3507
3508 mapping = pci_map_single(tp->pdev, skb->data,
3509 skb_size - tp->rx_offset,
3510 PCI_DMA_FROMDEVICE);
3511
3512 map->skb = skb;
3513 pci_unmap_addr_set(map, mapping, mapping);
3514
3515 if (src_map != NULL)
3516 src_map->skb = NULL;
3517
3518 desc->addr_hi = ((u64)mapping >> 32);
3519 desc->addr_lo = ((u64)mapping & 0xffffffff);
3520
3521 return skb_size;
3522}
3523
3524
3525
3526
3527
3528static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3529 int src_idx, u32 dest_idx_unmasked)
3530{
3531 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3532 struct ring_info *src_map, *dest_map;
3533 int dest_idx;
3534
3535 switch (opaque_key) {
3536 case RXD_OPAQUE_RING_STD:
3537 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3538 dest_desc = &tp->rx_std[dest_idx];
3539 dest_map = &tp->rx_std_buffers[dest_idx];
3540 src_desc = &tp->rx_std[src_idx];
3541 src_map = &tp->rx_std_buffers[src_idx];
3542 break;
3543
3544 case RXD_OPAQUE_RING_JUMBO:
3545 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3546 dest_desc = &tp->rx_jumbo[dest_idx];
3547 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3548 src_desc = &tp->rx_jumbo[src_idx];
3549 src_map = &tp->rx_jumbo_buffers[src_idx];
3550 break;
3551
3552 default:
3553 return;
3554 };
3555
3556 dest_map->skb = src_map->skb;
3557 pci_unmap_addr_set(dest_map, mapping,
3558 pci_unmap_addr(src_map, mapping));
3559 dest_desc->addr_hi = src_desc->addr_hi;
3560 dest_desc->addr_lo = src_desc->addr_lo;
3561
3562 src_map->skb = NULL;
3563}
3564
3565#if TG3_VLAN_TAG_USED
3566static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3567{
3568 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3569}
3570#endif
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596static int tg3_rx(struct tg3 *tp, int budget)
3597{
3598 u32 work_mask, rx_std_posted = 0;
3599 u32 sw_idx = tp->rx_rcb_ptr;
3600 u16 hw_idx;
3601 int received;
3602
3603 hw_idx = tp->hw_status->idx[0].rx_producer;
3604
3605
3606
3607
3608 rmb();
3609 work_mask = 0;
3610 received = 0;
3611 while (sw_idx != hw_idx && budget > 0) {
3612 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3613 unsigned int len;
3614 struct sk_buff *skb;
3615 dma_addr_t dma_addr;
3616 u32 opaque_key, desc_idx, *post_ptr;
3617
3618 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3619 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3620 if (opaque_key == RXD_OPAQUE_RING_STD) {
3621 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3622 mapping);
3623 skb = tp->rx_std_buffers[desc_idx].skb;
3624 post_ptr = &tp->rx_std_ptr;
3625 rx_std_posted++;
3626 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3627 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3628 mapping);
3629 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3630 post_ptr = &tp->rx_jumbo_ptr;
3631 }
3632 else {
3633 goto next_pkt_nopost;
3634 }
3635
3636 work_mask |= opaque_key;
3637
3638 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3639 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3640 drop_it:
3641 tg3_recycle_rx(tp, opaque_key,
3642 desc_idx, *post_ptr);
3643 drop_it_no_recycle:
3644
3645 tp->net_stats.rx_dropped++;
3646 goto next_pkt;
3647 }
3648
3649 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
3650
3651 if (len > RX_COPY_THRESHOLD
3652 && tp->rx_offset == 2
3653
3654
3655 ) {
3656 int skb_size;
3657
3658 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3659 desc_idx, *post_ptr);
3660 if (skb_size < 0)
3661 goto drop_it;
3662
3663 pci_unmap_single(tp->pdev, dma_addr,
3664 skb_size - tp->rx_offset,
3665 PCI_DMA_FROMDEVICE);
3666
3667 skb_put(skb, len);
3668 } else {
3669 struct sk_buff *copy_skb;
3670
3671 tg3_recycle_rx(tp, opaque_key,
3672 desc_idx, *post_ptr);
3673
3674 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3675 if (copy_skb == NULL)
3676 goto drop_it_no_recycle;
3677
3678 skb_reserve(copy_skb, 2);
3679 skb_put(copy_skb, len);
3680 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3681 skb_copy_from_linear_data(skb, copy_skb->data, len);
3682 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3683
3684
3685 skb = copy_skb;
3686 }
3687
3688 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3689 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3690 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3691 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3692 skb->ip_summed = CHECKSUM_UNNECESSARY;
3693 else
3694 skb->ip_summed = CHECKSUM_NONE;
3695
3696 skb->protocol = eth_type_trans(skb, tp->dev);
3697#if TG3_VLAN_TAG_USED
3698 if (tp->vlgrp != NULL &&
3699 desc->type_flags & RXD_FLAG_VLAN) {
3700 tg3_vlan_rx(tp, skb,
3701 desc->err_vlan & RXD_VLAN_MASK);
3702 } else
3703#endif
3704 netif_receive_skb(skb);
3705
3706 tp->dev->last_rx = jiffies;
3707 received++;
3708 budget--;
3709
3710next_pkt:
3711 (*post_ptr)++;
3712
3713 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3714 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3715
3716 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3717 TG3_64BIT_REG_LOW, idx);
3718 work_mask &= ~RXD_OPAQUE_RING_STD;
3719 rx_std_posted = 0;
3720 }
3721next_pkt_nopost:
3722 sw_idx++;
3723 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3724
3725
3726 if (sw_idx == hw_idx) {
3727 hw_idx = tp->hw_status->idx[0].rx_producer;
3728 rmb();
3729 }
3730 }
3731
3732
3733 tp->rx_rcb_ptr = sw_idx;
3734 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3735
3736
3737 if (work_mask & RXD_OPAQUE_RING_STD) {
3738 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3739 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3740 sw_idx);
3741 }
3742 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3743 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3744 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3745 sw_idx);
3746 }
3747 mmiowb();
3748
3749 return received;
3750}
3751
3752static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3753{
3754 struct tg3_hw_status *sblk = tp->hw_status;
3755
3756
3757 if (!(tp->tg3_flags &
3758 (TG3_FLAG_USE_LINKCHG_REG |
3759 TG3_FLAG_POLL_SERDES))) {
3760 if (sblk->status & SD_STATUS_LINK_CHG) {
3761 sblk->status = SD_STATUS_UPDATED |
3762 (sblk->status & ~SD_STATUS_LINK_CHG);
3763 spin_lock(&tp->lock);
3764 tg3_setup_phy(tp, 0);
3765 spin_unlock(&tp->lock);
3766 }
3767 }
3768
3769
3770 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3771 tg3_tx(tp);
3772 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3773 return work_done;
3774 }
3775
3776
3777
3778
3779
3780 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3781 work_done += tg3_rx(tp, budget - work_done);
3782
3783 return work_done;
3784}
3785
3786static int tg3_poll(struct napi_struct *napi, int budget)
3787{
3788 struct tg3 *tp = container_of(napi, struct tg3, napi);
3789 int work_done = 0;
3790 struct tg3_hw_status *sblk = tp->hw_status;
3791
3792 while (1) {
3793 work_done = tg3_poll_work(tp, work_done, budget);
3794
3795 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3796 goto tx_recovery;
3797
3798 if (unlikely(work_done >= budget))
3799 break;
3800
3801 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3802
3803
3804
3805
3806 tp->last_tag = sblk->status_tag;
3807 rmb();
3808 } else
3809 sblk->status &= ~SD_STATUS_UPDATED;
3810
3811 if (likely(!tg3_has_work(tp))) {
3812 netif_rx_complete(tp->dev, napi);
3813 tg3_restart_ints(tp);
3814 break;
3815 }
3816 }
3817
3818 return work_done;
3819
3820tx_recovery:
3821
3822 netif_rx_complete(tp->dev, napi);
3823 schedule_work(&tp->reset_task);
3824 return work_done;
3825}
3826
3827static void tg3_irq_quiesce(struct tg3 *tp)
3828{
3829 BUG_ON(tp->irq_sync);
3830
3831 tp->irq_sync = 1;
3832 smp_mb();
3833
3834 synchronize_irq(tp->pdev->irq);
3835}
3836
3837static inline int tg3_irq_sync(struct tg3 *tp)
3838{
3839 return tp->irq_sync;
3840}
3841
3842
3843
3844
3845
3846
3847static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3848{
3849 spin_lock_bh(&tp->lock);
3850 if (irq_sync)
3851 tg3_irq_quiesce(tp);
3852}
3853
3854static inline void tg3_full_unlock(struct tg3 *tp)
3855{
3856 spin_unlock_bh(&tp->lock);
3857}
3858
3859
3860
3861
3862static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3863{
3864 struct net_device *dev = dev_id;
3865 struct tg3 *tp = netdev_priv(dev);
3866
3867 prefetch(tp->hw_status);
3868 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3869
3870 if (likely(!tg3_irq_sync(tp)))
3871 netif_rx_schedule(dev, &tp->napi);
3872
3873 return IRQ_HANDLED;
3874}
3875
3876
3877
3878
3879
3880static irqreturn_t tg3_msi(int irq, void *dev_id)
3881{
3882 struct net_device *dev = dev_id;
3883 struct tg3 *tp = netdev_priv(dev);
3884
3885 prefetch(tp->hw_status);
3886 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3887
3888
3889
3890
3891
3892
3893
3894 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3895 if (likely(!tg3_irq_sync(tp)))
3896 netif_rx_schedule(dev, &tp->napi);
3897
3898 return IRQ_RETVAL(1);
3899}
3900
3901static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3902{
3903 struct net_device *dev = dev_id;
3904 struct tg3 *tp = netdev_priv(dev);
3905 struct tg3_hw_status *sblk = tp->hw_status;
3906 unsigned int handled = 1;
3907
3908
3909
3910
3911
3912
3913 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3914 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3915 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3916 handled = 0;
3917 goto out;
3918 }
3919 }
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3933 if (tg3_irq_sync(tp))
3934 goto out;
3935 sblk->status &= ~SD_STATUS_UPDATED;
3936 if (likely(tg3_has_work(tp))) {
3937 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3938 netif_rx_schedule(dev, &tp->napi);
3939 } else {
3940
3941
3942
3943 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3944 0x00000000);
3945 }
3946out:
3947 return IRQ_RETVAL(handled);
3948}
3949
3950static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3951{
3952 struct net_device *dev = dev_id;
3953 struct tg3 *tp = netdev_priv(dev);
3954 struct tg3_hw_status *sblk = tp->hw_status;
3955 unsigned int handled = 1;
3956
3957
3958
3959
3960
3961
3962 if (unlikely(sblk->status_tag == tp->last_tag)) {
3963 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3964 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3965 handled = 0;
3966 goto out;
3967 }
3968 }
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3982 if (tg3_irq_sync(tp))
3983 goto out;
3984 if (netif_rx_schedule_prep(dev, &tp->napi)) {
3985 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3986
3987
3988
3989
3990
3991 tp->last_tag = sblk->status_tag;
3992 __netif_rx_schedule(dev, &tp->napi);
3993 }
3994out:
3995 return IRQ_RETVAL(handled);
3996}
3997
3998
3999static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4000{
4001 struct net_device *dev = dev_id;
4002 struct tg3 *tp = netdev_priv(dev);
4003 struct tg3_hw_status *sblk = tp->hw_status;
4004
4005 if ((sblk->status & SD_STATUS_UPDATED) ||
4006 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4007 tg3_disable_ints(tp);
4008 return IRQ_RETVAL(1);
4009 }
4010 return IRQ_RETVAL(0);
4011}
4012
4013static int tg3_init_hw(struct tg3 *, int);
4014static int tg3_halt(struct tg3 *, int, int);
4015
4016
4017
4018
4019static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4020{
4021 int err;
4022
4023 err = tg3_init_hw(tp, reset_phy);
4024 if (err) {
4025 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4026 "aborting.\n", tp->dev->name);
4027 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4028 tg3_full_unlock(tp);
4029 del_timer_sync(&tp->timer);
4030 tp->irq_sync = 0;
4031 napi_enable(&tp->napi);
4032 dev_close(tp->dev);
4033 tg3_full_lock(tp, 0);
4034 }
4035 return err;
4036}
4037
4038#ifdef CONFIG_NET_POLL_CONTROLLER
4039static void tg3_poll_controller(struct net_device *dev)
4040{
4041 struct tg3 *tp = netdev_priv(dev);
4042
4043 tg3_interrupt(tp->pdev->irq, dev);
4044}
4045#endif
4046
4047static void tg3_reset_task(struct work_struct *work)
4048{
4049 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4050 unsigned int restart_timer;
4051
4052 tg3_full_lock(tp, 0);
4053
4054 if (!netif_running(tp->dev)) {
4055 tg3_full_unlock(tp);
4056 return;
4057 }
4058
4059 tg3_full_unlock(tp);
4060
4061 tg3_netif_stop(tp);
4062
4063 tg3_full_lock(tp, 1);
4064
4065 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4066 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4067
4068 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4069 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4070 tp->write32_rx_mbox = tg3_write_flush_reg32;
4071 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4072 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4073 }
4074
4075 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4076 if (tg3_init_hw(tp, 1))
4077 goto out;
4078
4079 tg3_netif_start(tp);
4080
4081 if (restart_timer)
4082 mod_timer(&tp->timer, jiffies + 1);
4083
4084out:
4085 tg3_full_unlock(tp);
4086}
4087
4088static void tg3_dump_short_state(struct tg3 *tp)
4089{
4090 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4091 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4092 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4093 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4094}
4095
4096static void tg3_tx_timeout(struct net_device *dev)
4097{
4098 struct tg3 *tp = netdev_priv(dev);
4099
4100 if (netif_msg_tx_err(tp)) {
4101 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4102 dev->name);
4103 tg3_dump_short_state(tp);
4104 }
4105
4106 schedule_work(&tp->reset_task);
4107}
4108
4109
4110static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4111{
4112 u32 base = (u32) mapping & 0xffffffff;
4113
4114 return ((base > 0xffffdcc0) &&
4115 (base + len + 8 < base));
4116}
4117
4118
4119static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4120 int len)
4121{
4122#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4123 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4124 return (((u64) mapping + len) > DMA_40BIT_MASK);
4125 return 0;
4126#else
4127 return 0;
4128#endif
4129}
4130
4131static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4132
4133
4134static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4135 u32 last_plus_one, u32 *start,
4136 u32 base_flags, u32 mss)
4137{
4138 struct sk_buff *new_skb;
4139 dma_addr_t new_addr = 0;
4140 u32 entry = *start;
4141 int i, ret = 0;
4142
4143 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4144 new_skb = skb_copy(skb, GFP_ATOMIC);
4145 else {
4146 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4147
4148 new_skb = skb_copy_expand(skb,
4149 skb_headroom(skb) + more_headroom,
4150 skb_tailroom(skb), GFP_ATOMIC);
4151 }
4152
4153 if (!new_skb) {
4154 ret = -1;
4155 } else {
4156
4157 entry = *start;
4158 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4159 PCI_DMA_TODEVICE);
4160
4161
4162
4163 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4164 ret = -1;
4165 dev_kfree_skb(new_skb);
4166 new_skb = NULL;
4167 } else {
4168 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4169 base_flags, 1 | (mss << 1));
4170 *start = NEXT_TX(entry);
4171 }
4172 }
4173
4174
4175 i = 0;
4176 while (entry != last_plus_one) {
4177 int len;
4178
4179 if (i == 0)
4180 len = skb_headlen(skb);
4181 else
4182 len = skb_shinfo(skb)->frags[i-1].size;
4183 pci_unmap_single(tp->pdev,
4184 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4185 len, PCI_DMA_TODEVICE);
4186 if (i == 0) {
4187 tp->tx_buffers[entry].skb = new_skb;
4188 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4189 } else {
4190 tp->tx_buffers[entry].skb = NULL;
4191 }
4192 entry = NEXT_TX(entry);
4193 i++;
4194 }
4195
4196 dev_kfree_skb(skb);
4197
4198 return ret;
4199}
4200
4201static void tg3_set_txd(struct tg3 *tp, int entry,
4202 dma_addr_t mapping, int len, u32 flags,
4203 u32 mss_and_is_end)
4204{
4205 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4206 int is_end = (mss_and_is_end & 0x1);
4207 u32 mss = (mss_and_is_end >> 1);
4208 u32 vlan_tag = 0;
4209
4210 if (is_end)
4211 flags |= TXD_FLAG_END;
4212 if (flags & TXD_FLAG_VLAN) {
4213 vlan_tag = flags >> 16;
4214 flags &= 0xffff;
4215 }
4216 vlan_tag |= (mss << TXD_MSS_SHIFT);
4217
4218 txd->addr_hi = ((u64) mapping >> 32);
4219 txd->addr_lo = ((u64) mapping & 0xffffffff);
4220 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4221 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4222}
4223
4224
4225
4226
4227static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4228{
4229 struct tg3 *tp = netdev_priv(dev);
4230 dma_addr_t mapping;
4231 u32 len, entry, base_flags, mss;
4232
4233 len = skb_headlen(skb);
4234
4235
4236
4237
4238
4239
4240 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4241 if (!netif_queue_stopped(dev)) {
4242 netif_stop_queue(dev);
4243
4244
4245 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4246 "queue awake!\n", dev->name);
4247 }
4248 return NETDEV_TX_BUSY;
4249 }
4250
4251 entry = tp->tx_prod;
4252 base_flags = 0;
4253 mss = 0;
4254 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4255 int tcp_opt_len, ip_tcp_len;
4256
4257 if (skb_header_cloned(skb) &&
4258 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4259 dev_kfree_skb(skb);
4260 goto out_unlock;
4261 }
4262
4263 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4264 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4265 else {
4266 struct iphdr *iph = ip_hdr(skb);
4267
4268 tcp_opt_len = tcp_optlen(skb);
4269 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4270
4271 iph->check = 0;
4272 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4273 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4274 }
4275
4276 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4277 TXD_FLAG_CPU_POST_DMA);
4278
4279 tcp_hdr(skb)->check = 0;
4280
4281 }
4282 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4283 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4284#if TG3_VLAN_TAG_USED
4285 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4286 base_flags |= (TXD_FLAG_VLAN |
4287 (vlan_tx_tag_get(skb) << 16));
4288#endif
4289
4290
4291 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4292
4293 tp->tx_buffers[entry].skb = skb;
4294 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4295
4296 tg3_set_txd(tp, entry, mapping, len, base_flags,
4297 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4298
4299 entry = NEXT_TX(entry);
4300
4301
4302 if (skb_shinfo(skb)->nr_frags > 0) {
4303 unsigned int i, last;
4304
4305 last = skb_shinfo(skb)->nr_frags - 1;
4306 for (i = 0; i <= last; i++) {
4307 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4308
4309 len = frag->size;
4310 mapping = pci_map_page(tp->pdev,
4311 frag->page,
4312 frag->page_offset,
4313 len, PCI_DMA_TODEVICE);
4314
4315 tp->tx_buffers[entry].skb = NULL;
4316 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4317
4318 tg3_set_txd(tp, entry, mapping, len,
4319 base_flags, (i == last) | (mss << 1));
4320
4321 entry = NEXT_TX(entry);
4322 }
4323 }
4324
4325
4326 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4327
4328 tp->tx_prod = entry;
4329 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4330 netif_stop_queue(dev);
4331 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4332 netif_wake_queue(tp->dev);
4333 }
4334
4335out_unlock:
4336 mmiowb();
4337
4338 dev->trans_start = jiffies;
4339
4340 return NETDEV_TX_OK;
4341}
4342
4343static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4344
4345
4346
4347
4348static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4349{
4350 struct sk_buff *segs, *nskb;
4351
4352
4353 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4354 netif_stop_queue(tp->dev);
4355 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4356 return NETDEV_TX_BUSY;
4357
4358 netif_wake_queue(tp->dev);
4359 }
4360
4361 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4362 if (unlikely(IS_ERR(segs)))
4363 goto tg3_tso_bug_end;
4364
4365 do {
4366 nskb = segs;
4367 segs = segs->next;
4368 nskb->next = NULL;
4369 tg3_start_xmit_dma_bug(nskb, tp->dev);
4370 } while (segs);
4371
4372tg3_tso_bug_end:
4373 dev_kfree_skb(skb);
4374
4375 return NETDEV_TX_OK;
4376}
4377
4378
4379
4380
4381static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4382{
4383 struct tg3 *tp = netdev_priv(dev);
4384 dma_addr_t mapping;
4385 u32 len, entry, base_flags, mss;
4386 int would_hit_hwbug;
4387
4388 len = skb_headlen(skb);
4389
4390
4391
4392
4393
4394
4395 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4396 if (!netif_queue_stopped(dev)) {
4397 netif_stop_queue(dev);
4398
4399
4400 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4401 "queue awake!\n", dev->name);
4402 }
4403 return NETDEV_TX_BUSY;
4404 }
4405
4406 entry = tp->tx_prod;
4407 base_flags = 0;
4408 if (skb->ip_summed == CHECKSUM_PARTIAL)
4409 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4410 mss = 0;
4411 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4412 struct iphdr *iph;
4413 int tcp_opt_len, ip_tcp_len, hdr_len;
4414
4415 if (skb_header_cloned(skb) &&
4416 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4417 dev_kfree_skb(skb);
4418 goto out_unlock;
4419 }
4420
4421 tcp_opt_len = tcp_optlen(skb);
4422 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4423
4424 hdr_len = ip_tcp_len + tcp_opt_len;
4425 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4426 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4427 return (tg3_tso_bug(tp, skb));
4428
4429 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4430 TXD_FLAG_CPU_POST_DMA);
4431
4432 iph = ip_hdr(skb);
4433 iph->check = 0;
4434 iph->tot_len = htons(mss + hdr_len);
4435 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4436 tcp_hdr(skb)->check = 0;
4437 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4438 } else
4439 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4440 iph->daddr, 0,
4441 IPPROTO_TCP,
4442 0);
4443
4444 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4445 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4446 if (tcp_opt_len || iph->ihl > 5) {
4447 int tsflags;
4448
4449 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4450 mss |= (tsflags << 11);
4451 }
4452 } else {
4453 if (tcp_opt_len || iph->ihl > 5) {
4454 int tsflags;
4455
4456 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4457 base_flags |= tsflags << 12;
4458 }
4459 }
4460 }
4461#if TG3_VLAN_TAG_USED
4462 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4463 base_flags |= (TXD_FLAG_VLAN |
4464 (vlan_tx_tag_get(skb) << 16));
4465#endif
4466
4467
4468 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4469
4470 tp->tx_buffers[entry].skb = skb;
4471 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4472
4473 would_hit_hwbug = 0;
4474
4475 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4476 would_hit_hwbug = 1;
4477 else if (tg3_4g_overflow_test(mapping, len))
4478 would_hit_hwbug = 1;
4479
4480 tg3_set_txd(tp, entry, mapping, len, base_flags,
4481 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4482
4483 entry = NEXT_TX(entry);
4484
4485
4486 if (skb_shinfo(skb)->nr_frags > 0) {
4487 unsigned int i, last;
4488
4489 last = skb_shinfo(skb)->nr_frags - 1;
4490 for (i = 0; i <= last; i++) {
4491 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4492
4493 len = frag->size;
4494 mapping = pci_map_page(tp->pdev,
4495 frag->page,
4496 frag->page_offset,
4497 len, PCI_DMA_TODEVICE);
4498
4499 tp->tx_buffers[entry].skb = NULL;
4500 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4501
4502 if (tg3_4g_overflow_test(mapping, len))
4503 would_hit_hwbug = 1;
4504
4505 if (tg3_40bit_overflow_test(tp, mapping, len))
4506 would_hit_hwbug = 1;
4507
4508 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4509 tg3_set_txd(tp, entry, mapping, len,
4510 base_flags, (i == last)|(mss << 1));
4511 else
4512 tg3_set_txd(tp, entry, mapping, len,
4513 base_flags, (i == last));
4514
4515 entry = NEXT_TX(entry);
4516 }
4517 }
4518
4519 if (would_hit_hwbug) {
4520 u32 last_plus_one = entry;
4521 u32 start;
4522
4523 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4524 start &= (TG3_TX_RING_SIZE - 1);
4525
4526
4527
4528
4529 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4530 &start, base_flags, mss))
4531 goto out_unlock;
4532
4533 entry = start;
4534 }
4535
4536
4537 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4538
4539 tp->tx_prod = entry;
4540 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4541 netif_stop_queue(dev);
4542 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4543 netif_wake_queue(tp->dev);
4544 }
4545
4546out_unlock:
4547 mmiowb();
4548
4549 dev->trans_start = jiffies;
4550
4551 return NETDEV_TX_OK;
4552}
4553
4554static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4555 int new_mtu)
4556{
4557 dev->mtu = new_mtu;
4558
4559 if (new_mtu > ETH_DATA_LEN) {
4560 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4561 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4562 ethtool_op_set_tso(dev, 0);
4563 }
4564 else
4565 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4566 } else {
4567 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4568 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4569 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4570 }
4571}
4572
4573static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4574{
4575 struct tg3 *tp = netdev_priv(dev);
4576 int err;
4577
4578 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4579 return -EINVAL;
4580
4581 if (!netif_running(dev)) {
4582
4583
4584
4585 tg3_set_mtu(dev, tp, new_mtu);
4586 return 0;
4587 }
4588
4589 tg3_netif_stop(tp);
4590
4591 tg3_full_lock(tp, 1);
4592
4593 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4594
4595 tg3_set_mtu(dev, tp, new_mtu);
4596
4597 err = tg3_restart_hw(tp, 0);
4598
4599 if (!err)
4600 tg3_netif_start(tp);
4601
4602 tg3_full_unlock(tp);
4603
4604 return err;
4605}
4606
4607
4608
4609
4610
4611
4612
4613
4614static void tg3_free_rings(struct tg3 *tp)
4615{
4616 struct ring_info *rxp;
4617 int i;
4618
4619 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4620 rxp = &tp->rx_std_buffers[i];
4621
4622 if (rxp->skb == NULL)
4623 continue;
4624 pci_unmap_single(tp->pdev,
4625 pci_unmap_addr(rxp, mapping),
4626 tp->rx_pkt_buf_sz - tp->rx_offset,
4627 PCI_DMA_FROMDEVICE);
4628 dev_kfree_skb_any(rxp->skb);
4629 rxp->skb = NULL;
4630 }
4631
4632 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4633 rxp = &tp->rx_jumbo_buffers[i];
4634
4635 if (rxp->skb == NULL)
4636 continue;
4637 pci_unmap_single(tp->pdev,
4638 pci_unmap_addr(rxp, mapping),
4639 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4640 PCI_DMA_FROMDEVICE);
4641 dev_kfree_skb_any(rxp->skb);
4642 rxp->skb = NULL;
4643 }
4644
4645 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4646 struct tx_ring_info *txp;
4647 struct sk_buff *skb;
4648 int j;
4649
4650 txp = &tp->tx_buffers[i];
4651 skb = txp->skb;
4652
4653 if (skb == NULL) {
4654 i++;
4655 continue;
4656 }
4657
4658 pci_unmap_single(tp->pdev,
4659 pci_unmap_addr(txp, mapping),
4660 skb_headlen(skb),
4661 PCI_DMA_TODEVICE);
4662 txp->skb = NULL;
4663
4664 i++;
4665
4666 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4667 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4668 pci_unmap_page(tp->pdev,
4669 pci_unmap_addr(txp, mapping),
4670 skb_shinfo(skb)->frags[j].size,
4671 PCI_DMA_TODEVICE);
4672 i++;
4673 }
4674
4675 dev_kfree_skb_any(skb);
4676 }
4677}
4678
4679
4680
4681
4682
4683
4684
4685
4686static int tg3_init_rings(struct tg3 *tp)
4687{
4688 u32 i;
4689
4690
4691 tg3_free_rings(tp);
4692
4693
4694 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4695 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4696 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4697 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4698
4699 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4700 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4701 (tp->dev->mtu > ETH_DATA_LEN))
4702 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4703
4704
4705
4706
4707
4708 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4709 struct tg3_rx_buffer_desc *rxd;
4710
4711 rxd = &tp->rx_std[i];
4712 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4713 << RXD_LEN_SHIFT;
4714 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4715 rxd->opaque = (RXD_OPAQUE_RING_STD |
4716 (i << RXD_OPAQUE_INDEX_SHIFT));
4717 }
4718
4719 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4720 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4721 struct tg3_rx_buffer_desc *rxd;
4722
4723 rxd = &tp->rx_jumbo[i];
4724 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4725 << RXD_LEN_SHIFT;
4726 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4727 RXD_FLAG_JUMBO;
4728 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4729 (i << RXD_OPAQUE_INDEX_SHIFT));
4730 }
4731 }
4732
4733
4734 for (i = 0; i < tp->rx_pending; i++) {
4735 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4736 printk(KERN_WARNING PFX
4737 "%s: Using a smaller RX standard ring, "
4738 "only %d out of %d buffers were allocated "
4739 "successfully.\n",
4740 tp->dev->name, i, tp->rx_pending);
4741 if (i == 0)
4742 return -ENOMEM;
4743 tp->rx_pending = i;
4744 break;
4745 }
4746 }
4747
4748 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4749 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4750 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4751 -1, i) < 0) {
4752 printk(KERN_WARNING PFX
4753 "%s: Using a smaller RX jumbo ring, "
4754 "only %d out of %d buffers were "
4755 "allocated successfully.\n",
4756 tp->dev->name, i, tp->rx_jumbo_pending);
4757 if (i == 0) {
4758 tg3_free_rings(tp);
4759 return -ENOMEM;
4760 }
4761 tp->rx_jumbo_pending = i;
4762 break;
4763 }
4764 }
4765 }
4766 return 0;
4767}
4768
4769
4770
4771
4772
4773static void tg3_free_consistent(struct tg3 *tp)
4774{
4775 kfree(tp->rx_std_buffers);
4776 tp->rx_std_buffers = NULL;
4777 if (tp->rx_std) {
4778 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4779 tp->rx_std, tp->rx_std_mapping);
4780 tp->rx_std = NULL;
4781 }
4782 if (tp->rx_jumbo) {
4783 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4784 tp->rx_jumbo, tp->rx_jumbo_mapping);
4785 tp->rx_jumbo = NULL;
4786 }
4787 if (tp->rx_rcb) {
4788 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4789 tp->rx_rcb, tp->rx_rcb_mapping);
4790 tp->rx_rcb = NULL;
4791 }
4792 if (tp->tx_ring) {
4793 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4794 tp->tx_ring, tp->tx_desc_mapping);
4795 tp->tx_ring = NULL;
4796 }
4797 if (tp->hw_status) {
4798 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4799 tp->hw_status, tp->status_mapping);
4800 tp->hw_status = NULL;
4801 }
4802 if (tp->hw_stats) {
4803 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4804 tp->hw_stats, tp->stats_mapping);
4805 tp->hw_stats = NULL;
4806 }
4807}
4808
4809
4810
4811
4812
4813static int tg3_alloc_consistent(struct tg3 *tp)
4814{
4815 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4816 (TG3_RX_RING_SIZE +
4817 TG3_RX_JUMBO_RING_SIZE)) +
4818 (sizeof(struct tx_ring_info) *
4819 TG3_TX_RING_SIZE),
4820 GFP_KERNEL);
4821 if (!tp->rx_std_buffers)
4822 return -ENOMEM;
4823
4824 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4825 tp->tx_buffers = (struct tx_ring_info *)
4826 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4827
4828 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4829 &tp->rx_std_mapping);
4830 if (!tp->rx_std)
4831 goto err_out;
4832
4833 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4834 &tp->rx_jumbo_mapping);
4835
4836 if (!tp->rx_jumbo)
4837 goto err_out;
4838
4839 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4840 &tp->rx_rcb_mapping);
4841 if (!tp->rx_rcb)
4842 goto err_out;
4843
4844 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4845 &tp->tx_desc_mapping);
4846 if (!tp->tx_ring)
4847 goto err_out;
4848
4849 tp->hw_status = pci_alloc_consistent(tp->pdev,
4850 TG3_HW_STATUS_SIZE,
4851 &tp->status_mapping);
4852 if (!tp->hw_status)
4853 goto err_out;
4854
4855 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4856 sizeof(struct tg3_hw_stats),
4857 &tp->stats_mapping);
4858 if (!tp->hw_stats)
4859 goto err_out;
4860
4861 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4862 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4863
4864 return 0;
4865
4866err_out:
4867 tg3_free_consistent(tp);
4868 return -ENOMEM;
4869}
4870
4871#define MAX_WAIT_CNT 1000
4872
4873
4874
4875
4876static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4877{
4878 unsigned int i;
4879 u32 val;
4880
4881 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4882 switch (ofs) {
4883 case RCVLSC_MODE:
4884 case DMAC_MODE:
4885 case MBFREE_MODE:
4886 case BUFMGR_MODE:
4887 case MEMARB_MODE:
4888
4889
4890
4891 return 0;
4892
4893 default:
4894 break;
4895 };
4896 }
4897
4898 val = tr32(ofs);
4899 val &= ~enable_bit;
4900 tw32_f(ofs, val);
4901
4902 for (i = 0; i < MAX_WAIT_CNT; i++) {
4903 udelay(100);
4904 val = tr32(ofs);
4905 if ((val & enable_bit) == 0)
4906 break;
4907 }
4908
4909 if (i == MAX_WAIT_CNT && !silent) {
4910 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4911 "ofs=%lx enable_bit=%x\n",
4912 ofs, enable_bit);
4913 return -ENODEV;
4914 }
4915
4916 return 0;
4917}
4918
4919
4920static int tg3_abort_hw(struct tg3 *tp, int silent)
4921{
4922 int i, err;
4923
4924 tg3_disable_ints(tp);
4925
4926 tp->rx_mode &= ~RX_MODE_ENABLE;
4927 tw32_f(MAC_RX_MODE, tp->rx_mode);
4928 udelay(10);
4929
4930 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4931 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4932 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4933 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4934 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4935 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4936
4937 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4938 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4939 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4940 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4941 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4942 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4943 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4944
4945 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4946 tw32_f(MAC_MODE, tp->mac_mode);
4947 udelay(40);
4948
4949 tp->tx_mode &= ~TX_MODE_ENABLE;
4950 tw32_f(MAC_TX_MODE, tp->tx_mode);
4951
4952 for (i = 0; i < MAX_WAIT_CNT; i++) {
4953 udelay(100);
4954 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4955 break;
4956 }
4957 if (i >= MAX_WAIT_CNT) {
4958 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4959 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4960 tp->dev->name, tr32(MAC_TX_MODE));
4961 err |= -ENODEV;
4962 }
4963
4964 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4965 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4966 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4967
4968 tw32(FTQ_RESET, 0xffffffff);
4969 tw32(FTQ_RESET, 0x00000000);
4970
4971 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4972 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4973
4974 if (tp->hw_status)
4975 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4976 if (tp->hw_stats)
4977 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4978
4979 return err;
4980}
4981
4982
4983static int tg3_nvram_lock(struct tg3 *tp)
4984{
4985 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4986 int i;
4987
4988 if (tp->nvram_lock_cnt == 0) {
4989 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4990 for (i = 0; i < 8000; i++) {
4991 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4992 break;
4993 udelay(20);
4994 }
4995 if (i == 8000) {
4996 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4997 return -ENODEV;
4998 }
4999 }
5000 tp->nvram_lock_cnt++;
5001 }
5002 return 0;
5003}
5004
5005
5006static void tg3_nvram_unlock(struct tg3 *tp)
5007{
5008 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5009 if (tp->nvram_lock_cnt > 0)
5010 tp->nvram_lock_cnt--;
5011 if (tp->nvram_lock_cnt == 0)
5012 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5013 }
5014}
5015
5016
5017static void tg3_enable_nvram_access(struct tg3 *tp)
5018{
5019 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5020 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5021 u32 nvaccess = tr32(NVRAM_ACCESS);
5022
5023 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5024 }
5025}
5026
5027
5028static void tg3_disable_nvram_access(struct tg3 *tp)
5029{
5030 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5031 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5032 u32 nvaccess = tr32(NVRAM_ACCESS);
5033
5034 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5035 }
5036}
5037
5038static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5039{
5040 int i;
5041 u32 apedata;
5042
5043 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5044 if (apedata != APE_SEG_SIG_MAGIC)
5045 return;
5046
5047 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5048 if (apedata != APE_FW_STATUS_READY)
5049 return;
5050
5051
5052 for (i = 0; i < 10; i++) {
5053 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5054 return;
5055
5056 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5057
5058 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5059 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5060 event | APE_EVENT_STATUS_EVENT_PENDING);
5061
5062 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5063
5064 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5065 break;
5066
5067 udelay(100);
5068 }
5069
5070 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5071 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5072}
5073
5074static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5075{
5076 u32 event;
5077 u32 apedata;
5078
5079 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5080 return;
5081
5082 switch (kind) {
5083 case RESET_KIND_INIT:
5084 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5085 APE_HOST_SEG_SIG_MAGIC);
5086 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5087 APE_HOST_SEG_LEN_MAGIC);
5088 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5089 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5090 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5091 APE_HOST_DRIVER_ID_MAGIC);
5092 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5093 APE_HOST_BEHAV_NO_PHYLOCK);
5094
5095 event = APE_EVENT_STATUS_STATE_START;
5096 break;
5097 case RESET_KIND_SHUTDOWN:
5098 event = APE_EVENT_STATUS_STATE_UNLOAD;
5099 break;
5100 case RESET_KIND_SUSPEND:
5101 event = APE_EVENT_STATUS_STATE_SUSPEND;
5102 break;
5103 default:
5104 return;
5105 }
5106
5107 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5108
5109 tg3_ape_send_event(tp, event);
5110}
5111
5112
5113static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5114{
5115 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5116 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5117
5118 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5119 switch (kind) {
5120 case RESET_KIND_INIT:
5121 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5122 DRV_STATE_START);
5123 break;
5124
5125 case RESET_KIND_SHUTDOWN:
5126 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5127 DRV_STATE_UNLOAD);
5128 break;
5129
5130 case RESET_KIND_SUSPEND:
5131 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5132 DRV_STATE_SUSPEND);
5133 break;
5134
5135 default:
5136 break;
5137 };
5138 }
5139
5140 if (kind == RESET_KIND_INIT ||
5141 kind == RESET_KIND_SUSPEND)
5142 tg3_ape_driver_state_change(tp, kind);
5143}
5144
5145
5146static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5147{
5148 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5149 switch (kind) {
5150 case RESET_KIND_INIT:
5151 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5152 DRV_STATE_START_DONE);
5153 break;
5154
5155 case RESET_KIND_SHUTDOWN:
5156 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5157 DRV_STATE_UNLOAD_DONE);
5158 break;
5159
5160 default:
5161 break;
5162 };
5163 }
5164
5165 if (kind == RESET_KIND_SHUTDOWN)
5166 tg3_ape_driver_state_change(tp, kind);
5167}
5168
5169
5170static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5171{
5172 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5173 switch (kind) {
5174 case RESET_KIND_INIT:
5175 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5176 DRV_STATE_START);
5177 break;
5178
5179 case RESET_KIND_SHUTDOWN:
5180 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5181 DRV_STATE_UNLOAD);
5182 break;
5183
5184 case RESET_KIND_SUSPEND:
5185 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5186 DRV_STATE_SUSPEND);
5187 break;
5188
5189 default:
5190 break;
5191 };
5192 }
5193}
5194
5195static int tg3_poll_fw(struct tg3 *tp)
5196{
5197 int i;
5198 u32 val;
5199
5200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5201
5202 for (i = 0; i < 200; i++) {
5203 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5204 return 0;
5205 udelay(100);
5206 }
5207 return -ENODEV;
5208 }
5209
5210
5211 for (i = 0; i < 100000; i++) {
5212 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5213 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5214 break;
5215 udelay(10);
5216 }
5217
5218
5219
5220
5221
5222
5223 if (i >= 100000 &&
5224 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5225 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5226
5227 printk(KERN_INFO PFX "%s: No firmware running.\n",
5228 tp->dev->name);
5229 }
5230
5231 return 0;
5232}
5233
5234
5235static void tg3_save_pci_state(struct tg3 *tp)
5236{
5237 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5238}
5239
5240
5241static void tg3_restore_pci_state(struct tg3 *tp)
5242{
5243 u32 val;
5244
5245
5246 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5247 tp->misc_host_ctrl);
5248
5249
5250 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5251 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5252 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5253 val |= PCISTATE_RETRY_SAME_DMA;
5254
5255 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5256 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5257 PCISTATE_ALLOW_APE_SHMEM_WR;
5258 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5259
5260 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5261
5262 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5263 pcie_set_readrq(tp->pdev, 4096);
5264 else {
5265 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5266 tp->pci_cacheline_sz);
5267 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5268 tp->pci_lat_timer);
5269 }
5270
5271
5272 if (tp->pcix_cap) {
5273 u16 pcix_cmd;
5274
5275 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5276 &pcix_cmd);
5277 pcix_cmd &= ~PCI_X_CMD_ERO;
5278 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5279 pcix_cmd);
5280 }
5281
5282 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5283
5284
5285
5286
5287 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5288 u16 ctrl;
5289
5290 pci_read_config_word(tp->pdev,
5291 tp->msi_cap + PCI_MSI_FLAGS,
5292 &ctrl);
5293 pci_write_config_word(tp->pdev,
5294 tp->msi_cap + PCI_MSI_FLAGS,
5295 ctrl | PCI_MSI_FLAGS_ENABLE);
5296 val = tr32(MSGINT_MODE);
5297 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5298 }
5299 }
5300}
5301
5302static void tg3_stop_fw(struct tg3 *);
5303
5304
5305static int tg3_chip_reset(struct tg3 *tp)
5306{
5307 u32 val;
5308 void (*write_op)(struct tg3 *, u32, u32);
5309 int err;
5310
5311 tg3_nvram_lock(tp);
5312
5313
5314
5315
5316 tp->nvram_lock_cnt = 0;
5317
5318
5319
5320
5321
5322 tg3_save_pci_state(tp);
