LXR linux/drivers/mtd/maps/sc520cdp.c

   1/* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform
   2 *
   3 * Copyright (C) 2001 Sysgo Real-Time Solutions GmbH
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  18 *
  19 * $Id: sc520cdp.c,v 1.23 2005/11/17 08:20:27 dwmw2 Exp $
  20 *
  21 *
  22 * The SC520CDP is an evaluation board for the Elan SC520 processor available
  23 * from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
  24 * and up to 512 KiB of 8-bit DIL Flash ROM.
  25 * For details see http://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
  26 */
  27
  28#include <linux/module.h>
  29#include <linux/types.h>
  30#include <linux/kernel.h>
  31#include <linux/init.h>
  32#include <asm/io.h>
  33#include <linux/mtd/mtd.h>
  34#include <linux/mtd/map.h>
  35#include <linux/mtd/concat.h>
  36
  37/*
  38** The Embedded Systems BIOS decodes the first FLASH starting at
  39** 0x8400000. This is a *terrible* place for it because accessing
  40** the flash at this location causes the A22 address line to be high
  41** (that's what 0x8400000 binary's ought to be). But this is the highest
  42** order address line on the raw flash devices themselves!!
  43** This causes the top HALF of the flash to be accessed first. Beyond
  44** the physical limits of the flash, the flash chip aliases over (to
  45** 0x880000 which causes the bottom half to be accessed. This splits the
  46** flash into two and inverts it! If you then try to access this from another
  47** program that does NOT do this insanity, then you *will* access the
  48** first half of the flash, but not find what you expect there. That
  49** stuff is in the *second* half! Similarly, the address used by the
  50** BIOS for the second FLASH bank is also quite a bad choice.
  51** If REPROGRAM_PAR is defined below (the default), then this driver will
  52** choose more useful addresses for the FLASH banks by reprogramming the
  53** responsible PARxx registers in the SC520's MMCR region. This will
  54** cause the settings to be incompatible with the BIOS's settings, which
  55** shouldn't be a problem since you are running Linux, (i.e. the BIOS is
  56** not much use anyway). However, if you need to be compatible with
  57** the BIOS for some reason, just undefine REPROGRAM_PAR.
  58*/
  59#define REPROGRAM_PAR
  60
  61
  62
  63#ifdef REPROGRAM_PAR
  64
  65/* These are the addresses we want.. */
  66#define WINDOW_ADDR_0   0x08800000
  67#define WINDOW_ADDR_1   0x09000000
  68#define WINDOW_ADDR_2   0x09800000
  69
  70/* .. and these are the addresses the BIOS gives us */
  71#define WINDOW_ADDR_0_BIOS      0x08400000
  72#define WINDOW_ADDR_1_BIOS      0x08c00000
  73#define WINDOW_ADDR_2_BIOS      0x09400000
  74
  75#else
  76
  77#define WINDOW_ADDR_0   0x08400000
  78#define WINDOW_ADDR_1   0x08C00000
  79#define WINDOW_ADDR_2   0x09400000
  80
  81#endif
  82
  83#define WINDOW_SIZE_0   0x00800000
  84#define WINDOW_SIZE_1   0x00800000
  85#define WINDOW_SIZE_2   0x00080000
  86
  87
  88static struct map_info sc520cdp_map[] = {
  89        {
  90                .name = "SC520CDP Flash Bank #0",
  91                .size = WINDOW_SIZE_0,
  92                .bankwidth = 4,
  93                .phys = WINDOW_ADDR_0
  94        },
  95        {
  96                .name = "SC520CDP Flash Bank #1",
  97                .size = WINDOW_SIZE_1,
  98                .bankwidth = 4,
  99                .phys = WINDOW_ADDR_1
 100        },
 101        {
 102                .name = "SC520CDP DIL Flash",
 103                .size = WINDOW_SIZE_2,
 104                .bankwidth = 1,
 105                .phys = WINDOW_ADDR_2
 106        },
 107};
 108
 109#define NUM_FLASH_BANKS ARRAY_SIZE(sc520cdp_map)
 110
 111static struct mtd_info *mymtd[NUM_FLASH_BANKS];
 112static struct mtd_info *merged_mtd;
 113
 114#ifdef REPROGRAM_PAR
 115
 116/*
 117** The SC520 MMCR (memory mapped control register) region resides
 118** at 0xFFFEF000. The 16 Programmable Address Region (PAR) registers
 119** are at offset 0x88 in the MMCR:
 120*/
 121#define SC520_MMCR_BASE         0xFFFEF000
 122#define SC520_MMCR_EXTENT       0x1000
 123#define SC520_PAR(x)            ((0x88/sizeof(unsigned long)) + (x))
 124#define NUM_SC520_PAR           16      /* total number of PAR registers */
 125
 126/*
 127** The highest three bits in a PAR register determine what target
 128** device is controlled by this PAR. Here, only ROMCS? and BOOTCS
 129** devices are of interest.
 130*/
 131#define SC520_PAR_BOOTCS        (0x4<<29)
 132#define SC520_PAR_ROMCS0        (0x5<<29)
 133#define SC520_PAR_ROMCS1        (0x6<<29)
 134#define SC520_PAR_TRGDEV        (0x7<<29)
 135
 136/*
 137** Bits 28 thru 26 determine some attributes for the
 138** region controlled by the PAR. (We only use non-cacheable)
 139*/
 140#define SC520_PAR_WRPROT        (1<<26) /* write protected       */
 141#define SC520_PAR_NOCACHE       (1<<27) /* non-cacheable         */
 142#define SC520_PAR_NOEXEC        (1<<28) /* code execution denied */
 143
 144
 145/*
 146** Bit 25 determines the granularity: 4K or 64K
 147*/
 148#define SC520_PAR_PG_SIZ4       (0<<25)
 149#define SC520_PAR_PG_SIZ64      (1<<25)
 150
 151/*
 152** Build a value to be written into a PAR register.
 153** We only need ROM entries, 64K page size:
 154*/
 155#define SC520_PAR_ENTRY(trgdev, address, size) \
 156        ((trgdev) | SC520_PAR_NOCACHE | SC520_PAR_PG_SIZ64 | \
 157        (address) >> 16 | (((size) >> 16) - 1) << 14)
 158
 159struct sc520_par_table
 160{
 161        unsigned long trgdev;
 162        unsigned long new_par;
 163        unsigned long default_address;
 164};
 165
 166static const struct sc520_par_table par_table[NUM_FLASH_BANKS] =
 167{
 168        {       /* Flash Bank #0: selected by ROMCS0 */
 169                SC520_PAR_ROMCS0,
 170                SC520_PAR_ENTRY(SC520_PAR_ROMCS0, WINDOW_ADDR_0, WINDOW_SIZE_0),
 171                WINDOW_ADDR_0_BIOS
 172        },
 173        {       /* Flash Bank #1: selected by ROMCS1 */
 174                SC520_PAR_ROMCS1,
 175                SC520_PAR_ENTRY(SC520_PAR_ROMCS1, WINDOW_ADDR_1, WINDOW_SIZE_1),
 176                WINDOW_ADDR_1_BIOS
 177        },
 178        {       /* DIL (BIOS) Flash: selected by BOOTCS */
 179                SC520_PAR_BOOTCS,
 180                SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2),
 181                WINDOW_ADDR_2_BIOS
 182        }
 183};
 184
 185
 186static void sc520cdp_setup_par(void)
 187{
 188        volatile unsigned long __iomem *mmcr;
 189        unsigned long mmcr_val;
 190        int i, j;
 191
 192        /* map in SC520's MMCR area */
 193        mmcr = ioremap_nocache(SC520_MMCR_BASE, SC520_MMCR_EXTENT);
 194        if(!mmcr) { /* ioremap_nocache failed: skip the PAR reprogramming */
 195                /* force physical address fields to BIOS defaults: */
 196                for(i = 0; i < NUM_FLASH_BANKS; i++)
 197                        sc520cdp_map[i].phys = par_table[i].default_address;
 198                return;
 199        }
 200
 201        /*
 202        ** Find the PARxx registers that are reponsible for activating
 203        ** ROMCS0, ROMCS1 and BOOTCS. Reprogram each of these with a
 204        ** new value from the table.
 205        */
 206        for(i = 0; i < NUM_FLASH_BANKS; i++) {          /* for each par_table entry  */
 207                for(j = 0; j < NUM_SC520_PAR; j++) {    /* for each PAR register     */
 208                        mmcr_val = mmcr[SC520_PAR(j)];
 209                        /* if target device field matches, reprogram the PAR */
 210                        if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev)
 211                        {
 212                                mmcr[SC520_PAR(j)] = par_table[i].new_par;
 213                                break;
 214                        }
 215                }
 216                if(j == NUM_SC520_PAR)
 217                {       /* no matching PAR found: try default BIOS address */
 218                        printk(KERN_NOTICE "Could not find PAR responsible for %s\n",
 219                                sc520cdp_map[i].name);
 220                        printk(KERN_NOTICE "Trying default address 0x%lx\n",
 221                                par_table[i].default_address);
 222                        sc520cdp_map[i].phys = par_table[i].default_address;
 223                }
 224        }
 225        iounmap(mmcr);
 226}
 227#endif
 228
 229
 230static int __init init_sc520cdp(void)
 231{
 232        int i, devices_found = 0;
 233
 234#ifdef REPROGRAM_PAR
 235        /* reprogram PAR registers so flash appears at the desired addresses */
 236        sc520cdp_setup_par();
 237#endif
 238
 239        for (i = 0; i < NUM_FLASH_BANKS; i++) {
 240                printk(KERN_NOTICE "SC520 CDP flash device: 0x%Lx at 0x%Lx\n",
 241                        (unsigned long long)sc520cdp_map[i].size,
 242                        (unsigned long long)sc520cdp_map[i].phys);
 243
 244                sc520cdp_map[i].virt = ioremap_nocache(sc520cdp_map[i].phys, sc520cdp_map[i].size);
 245
 246                if (!sc520cdp_map[i].virt) {
 247                        printk("Failed to ioremap_nocache\n");
 248                        return -EIO;
 249                }
 250
 251                simple_map_init(&sc520cdp_map[i]);
 252
 253                mymtd[i] = do_map_probe("cfi_probe", &sc520cdp_map[i]);
 254                if(!mymtd[i])
 255                        mymtd[i] = do_map_probe("jedec_probe", &sc520cdp_map[i]);
 256                if(!mymtd[i])
 257                        mymtd[i] = do_map_probe("map_rom", &sc520cdp_map[i]);
 258
 259                if (mymtd[i]) {
 260                        mymtd[i]->owner = THIS_MODULE;
 261                        ++devices_found;
 262                }
 263                else {
 264                        iounmap(sc520cdp_map[i].virt);
 265                }
 266        }
 267        if(devices_found >= 2) {
 268                /* Combine the two flash banks into a single MTD device & register it: */
 269                merged_mtd = mtd_concat_create(mymtd, 2, "SC520CDP Flash Banks #0 and #1");
 270                if(merged_mtd)
 271                        add_mtd_device(merged_mtd);
 272        }
 273        if(devices_found == 3) /* register the third (DIL-Flash) device */
 274                add_mtd_device(mymtd[2]);
 275        return(devices_found ? 0 : -ENXIO);
 276}
 277
 278static void __exit cleanup_sc520cdp(void)
 279{
 280        int i;
 281
 282        if (merged_mtd) {
 283                del_mtd_device(merged_mtd);
 284                mtd_concat_destroy(merged_mtd);
 285        }
 286        if (mymtd[2])
 287                del_mtd_device(mymtd[2]);
 288
 289        for (i = 0; i < NUM_FLASH_BANKS; i++) {
 290                if (mymtd[i])
 291                        map_destroy(mymtd[i]);
 292                if (sc520cdp_map[i].virt) {
 293                        iounmap(sc520cdp_map[i].virt);
 294                        sc520cdp_map[i].virt = NULL;
 295                }
 296        }
 297}
 298
 299module_init(init_sc520cdp);
 300module_exit(cleanup_sc520cdp);
 301
 302MODULE_LICENSE("GPL");
 303MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
 304MODULE_DESCRIPTION("MTD map driver for AMD SC520 Customer Development Platform");
 305