1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Adapted for Power Macintosh by Paul Mackerras. 7 * Low-level exception handlers and MMU support 8 * rewritten by Paul Mackerras. 9 * Copyright (C) 1996 Paul Mackerras. 10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains the system call entry code, context switch 13 * code, and exception/interrupt return code for PowerPC. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 */ 20 21#include <linux/errno.h> 22#include <asm/unistd.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/thread_info.h> 27#include <asm/ppc_asm.h> 28#include <asm/asm-offsets.h> 29#include <asm/cputable.h> 30#include <asm/firmware.h> 31#include <asm/bug.h> 32 33/* 34 * System calls. 35 */ 36 .section ".toc","aw" 37.SYS_CALL_TABLE: 38 .tc .sys_call_table[TC],.sys_call_table 39 40/* This value is used to mark exception frames on the stack. */ 41exception_marker: 42 .tc ID_72656773_68657265[TC],0x7265677368657265 43 44 .section ".text" 45 .align 7 46 47#undef SHOW_SYSCALLS 48 49 .globl system_call_common 50system_call_common: 51 andi. r10,r12,MSR_PR 52 mr r10,r1 53 addi r1,r1,-INT_FRAME_SIZE 54 beq- 1f 55 ld r1,PACAKSAVE(r13) 561: std r10,0(r1) 57 crclr so 58 std r11,_NIP(r1) 59 std r12,_MSR(r1) 60 std r0,GPR0(r1) 61 std r10,GPR1(r1) 62 ACCOUNT_CPU_USER_ENTRY(r10, r11) 63 std r2,GPR2(r1) 64 std r3,GPR3(r1) 65 std r4,GPR4(r1) 66 std r5,GPR5(r1) 67 std r6,GPR6(r1) 68 std r7,GPR7(r1) 69 std r8,GPR8(r1) 70 li r11,0 71 std r11,GPR9(r1) 72 std r11,GPR10(r1) 73 std r11,GPR11(r1) 74 std r11,GPR12(r1) 75 std r9,GPR13(r1) 76 mfcr r9 77 mflr r10 78 li r11,0xc01 79 std r9,_CCR(r1) 80 std r10,_LINK(r1) 81 std r11,_TRAP(r1) 82 mfxer r9 83 mfctr r10 84 std r9,_XER(r1) 85 std r10,_CTR(r1) 86 std r3,ORIG_GPR3(r1) 87 ld r2,PACATOC(r13) 88 addi r9,r1,STACK_FRAME_OVERHEAD 89 ld r11,exception_marker@toc(r2) 90 std r11,-16(r9) /* "regshere" marker */ 91 li r10,1 92 stb r10,PACASOFTIRQEN(r13) 93 stb r10,PACAHARDIRQEN(r13) 94 std r10,SOFTE(r1) 95#ifdef CONFIG_PPC_ISERIES 96BEGIN_FW_FTR_SECTION 97 /* Hack for handling interrupts when soft-enabling on iSeries */ 98 cmpdi cr1,r0,0x5555 /* syscall 0x5555 */ 99 andi. r10,r12,MSR_PR /* from kernel */ 100 crand 4*cr0+eq,4*cr1+eq,4*cr0+eq 101 bne 2f 102 b hardware_interrupt_entry 1032: 104END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 105#endif 106 mfmsr r11 107 ori r11,r11,MSR_EE 108 mtmsrd r11,1 109 110#ifdef SHOW_SYSCALLS 111 bl .do_show_syscall 112 REST_GPR(0,r1) 113 REST_4GPRS(3,r1) 114 REST_2GPRS(7,r1) 115 addi r9,r1,STACK_FRAME_OVERHEAD 116#endif 117 clrrdi r11,r1,THREAD_SHIFT 118 ld r10,TI_FLAGS(r11) 119 andi. r11,r10,_TIF_SYSCALL_T_OR_A 120 bne- syscall_dotrace 121syscall_dotrace_cont: 122 cmpldi 0,r0,NR_syscalls 123 bge- syscall_enosys 124 125system_call: /* label this so stack traces look sane */ 126/* 127 * Need to vector to 32 Bit or default sys_call_table here, 128 * based on caller's run-mode / personality. 129 */ 130 ld r11,.SYS_CALL_TABLE@toc(2) 131 andi. r10,r10,_TIF_32BIT 132 beq 15f 133 addi r11,r11,8 /* use 32-bit syscall entries */ 134 clrldi r3,r3,32 135 clrldi r4,r4,32 136 clrldi r5,r5,32 137 clrldi r6,r6,32 138 clrldi r7,r7,32 139 clrldi r8,r8,32 14015: 141 slwi r0,r0,4 142 ldx r10,r11,r0 /* Fetch system call handler [ptr] */ 143 mtctr r10 144 bctrl /* Call handler */ 145 146syscall_exit: 147 std r3,RESULT(r1) 148#ifdef SHOW_SYSCALLS 149 bl .do_show_syscall_exit 150 ld r3,RESULT(r1) 151#endif 152 clrrdi r12,r1,THREAD_SHIFT 153 154 /* disable interrupts so current_thread_info()->flags can't change, 155 and so that we don't get interrupted after loading SRR0/1. */ 156 ld r8,_MSR(r1) 157 andi. r10,r8,MSR_RI 158 beq- unrecov_restore 159 mfmsr r10 160 rldicl r10,r10,48,1 161 rotldi r10,r10,16 162 mtmsrd r10,1 163 ld r9,TI_FLAGS(r12) 164 li r11,-_LAST_ERRNO 165 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) 166 bne- syscall_exit_work 167 cmpld r3,r11 168 ld r5,_CCR(r1) 169 bge- syscall_error 170syscall_error_cont: 171 ld r7,_NIP(r1) 172 stdcx. r0,0,r1 /* to clear the reservation */ 173 andi. r6,r8,MSR_PR 174 ld r4,_LINK(r1) 175 /* 176 * Clear RI before restoring r13. If we are returning to 177 * userspace and we take an exception after restoring r13, 178 * we end up corrupting the userspace r13 value. 179 */ 180 li r12,MSR_RI 181 andc r11,r10,r12 182 mtmsrd r11,1 /* clear MSR.RI */ 183 beq- 1f 184 ACCOUNT_CPU_USER_EXIT(r11, r12) 185 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */ 1861: ld r2,GPR2(r1) 187 ld r1,GPR1(r1) 188 mtlr r4 189 mtcr r5 190 mtspr SPRN_SRR0,r7 191 mtspr SPRN_SRR1,r8 192 rfid 193 b . /* prevent speculative execution */ 194 195syscall_error: 196 oris r5,r5,0x1000 /* Set SO bit in CR */ 197 neg r3,r3 198 std r5,_CCR(r1) 199 b syscall_error_cont 200 201/* Traced system call support */ 202syscall_dotrace: 203 bl .save_nvgprs 204 addi r3,r1,STACK_FRAME_OVERHEAD 205 bl .do_syscall_trace_enter 206 ld r0,GPR0(r1) /* Restore original registers */ 207 ld r3,GPR3(r1) 208 ld r4,GPR4(r1) 209 ld r5,GPR5(r1) 210 ld r6,GPR6(r1) 211 ld r7,GPR7(r1) 212 ld r8,GPR8(r1) 213 addi r9,r1,STACK_FRAME_OVERHEAD 214 clrrdi r10,r1,THREAD_SHIFT 215 ld r10,TI_FLAGS(r10) 216 b syscall_dotrace_cont 217 218syscall_enosys: 219 li r3,-ENOSYS 220 b syscall_exit 221 222syscall_exit_work: 223 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr. 224 If TIF_NOERROR is set, just save r3 as it is. */ 225 226 andi. r0,r9,_TIF_RESTOREALL 227 beq+ 0f 228 REST_NVGPRS(r1) 229 b 2f 2300: cmpld r3,r11 /* r10 is -LAST_ERRNO */ 231 blt+ 1f 232 andi. r0,r9,_TIF_NOERROR 233 bne- 1f 234 ld r5,_CCR(r1) 235 neg r3,r3 236 oris r5,r5,0x1000 /* Set SO bit in CR */ 237 std r5,_CCR(r1) 2381: std r3,GPR3(r1) 2392: andi. r0,r9,(_TIF_PERSYSCALL_MASK) 240 beq 4f 241 242 /* Clear per-syscall TIF flags if any are set. */ 243 244 li r11,_TIF_PERSYSCALL_MASK 245 addi r12,r12,TI_FLAGS 2463: ldarx r10,0,r12 247 andc r10,r10,r11 248 stdcx. r10,0,r12 249 bne- 3b 250 subi r12,r12,TI_FLAGS 251 2524: /* Anything else left to do? */ 253 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) 254 beq .ret_from_except_lite 255 256 /* Re-enable interrupts */ 257 mfmsr r10 258 ori r10,r10,MSR_EE 259 mtmsrd r10,1 260 261 bl .save_nvgprs 262 addi r3,r1,STACK_FRAME_OVERHEAD 263 bl .do_syscall_trace_leave 264 b .ret_from_except 265 266/* Save non-volatile GPRs, if not already saved. */ 267_GLOBAL(save_nvgprs) 268 ld r11,_TRAP(r1) 269 andi. r0,r11,1 270 beqlr- 271 SAVE_NVGPRS(r1) 272 clrrdi r0,r11,1 273 std r0,_TRAP(r1) 274 blr 275 276 277/* 278 * The sigsuspend and rt_sigsuspend system calls can call do_signal 279 * and thus put the process into the stopped state where we might 280 * want to examine its user state with ptrace. Therefore we need 281 * to save all the nonvolatile registers (r14 - r31) before calling 282 * the C code. Similarly, fork, vfork and clone need the full 283 * register state on the stack so that it can be copied to the child. 284 */ 285 286_GLOBAL(ppc_fork) 287 bl .save_nvgprs 288 bl .sys_fork 289 b syscall_exit 290 291_GLOBAL(ppc_vfork) 292 bl .save_nvgprs 293 bl .sys_vfork 294 b syscall_exit 295 296_GLOBAL(ppc_clone) 297 bl .save_nvgprs 298 bl .sys_clone 299 b syscall_exit 300 301_GLOBAL(ppc32_swapcontext) 302 bl .save_nvgprs 303 bl .compat_sys_swapcontext 304 b syscall_exit 305 306_GLOBAL(ppc64_swapcontext) 307 bl .save_nvgprs 308 bl .sys_swapcontext 309 b syscall_exit 310 311_GLOBAL(ret_from_fork) 312 bl .schedule_tail 313 REST_NVGPRS(r1) 314 li r3,0 315 b syscall_exit 316 317/* 318 * This routine switches between two different tasks. The process 319 * state of one is saved on its kernel stack. Then the state 320 * of the other is restored from its kernel stack. The memory 321 * management hardware is updated to the second process's state. 322 * Finally, we can return to the second process, via ret_from_except. 323 * On entry, r3 points to the THREAD for the current task, r4 324 * points to the THREAD for the new task. 325 * 326 * Note: there are two ways to get to the "going out" portion 327 * of this code; either by coming in via the entry (_switch) 328 * or via "fork" which must set up an environment equivalent 329 * to the "_switch" path. If you change this you'll have to change 330 * the fork code also. 331 * 332 * The code which creates the new task context is in 'copy_thread' 333 * in arch/powerpc/kernel/process.c 334 */ 335 .align 7 336_GLOBAL(_switch) 337 mflr r0 338 std r0,16(r1) 339 stdu r1,-SWITCH_FRAME_SIZE(r1) 340 /* r3-r13 are caller saved -- Cort */ 341 SAVE_8GPRS(14, r1) 342 SAVE_10GPRS(22, r1) 343 mflr r20 /* Return to switch caller */ 344 mfmsr r22 345 li r0, MSR_FP 346#ifdef CONFIG_ALTIVEC 347BEGIN_FTR_SECTION 348 oris r0,r0,MSR_VEC@h /* Disable altivec */ 349 mfspr r24,SPRN_VRSAVE /* save vrsave register value */ 350 std r24,THREAD_VRSAVE(r3) 351END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 352#endif /* CONFIG_ALTIVEC */ 353 and. r0,r0,r22 354 beq+ 1f 355 andc r22,r22,r0 356 mtmsrd r22 357 isync 3581: std r20,_NIP(r1) 359 mfcr r23 360 std r23,_CCR(r1) 361 std r1,KSP(r3) /* Set old stack pointer */ 362 363#ifdef CONFIG_SMP 364 /* We need a sync somewhere here to make sure that if the 365 * previous task gets rescheduled on another CPU, it sees all 366 * stores it has performed on this one. 367 */ 368 sync 369#endif /* CONFIG_SMP */ 370 371 addi r6,r4,-THREAD /* Convert THREAD to 'current' */ 372 std r6,PACACURRENT(r13) /* Set new 'current' */ 373 374 ld r8,KSP(r4) /* new stack pointer */ 375BEGIN_FTR_SECTION 376 b 2f 377END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 378BEGIN_FTR_SECTION 379 clrrdi r6,r8,28 /* get its ESID */ 380 clrrdi r9,r1,28 /* get current sp ESID */ 381END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT) 382BEGIN_FTR_SECTION 383 clrrdi r6,r8,40 /* get its 1T ESID */ 384 clrrdi r9,r1,40 /* get current sp 1T ESID */ 385END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 386 clrldi. r0,r6,2 /* is new ESID c00000000? */ 387 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ 388 cror eq,4*cr1+eq,eq 389 beq 2f /* if yes, don't slbie it */ 390 391 /* Bolt in the new stack SLB entry */ 392 ld r7,KSP_VSID(r4) /* Get new stack's VSID */ 393 oris r0,r6,(SLB_ESID_V)@h 394 ori r0,r0,(SLB_NUM_BOLTED-1)@l 395BEGIN_FTR_SECTION 396 li r9,MMU_SEGSIZE_1T /* insert B field */ 397 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h 398 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0 399END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 400 401 /* Update the last bolted SLB. No write barriers are needed 402 * here, provided we only update the current CPU's SLB shadow 403 * buffer. 404 */ 405 ld r9,PACA_SLBSHADOWPTR(r13) 406 li r12,0 407 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ 408 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */ 409 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */ 410 411 /* No need to check for CPU_FTR_NO_SLBIE_B here, since when 412 * we have 1TB segments, the only CPUs known to have the errata 413 * only support less than 1TB of system memory and we'll never 414 * actually hit this code path. 415 */ 416 417 slbie r6 418 slbie r6 /* Workaround POWER5 < DD2.1 issue */ 419 slbmte r7,r0 420 isync 421 4222: 423 clrrdi r7,r8,THREAD_SHIFT /* base of new stack */ 424 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE 425 because we don't need to leave the 288-byte ABI gap at the 426 top of the kernel stack. */ 427 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE 428 429 mr r1,r8 /* start using new stack pointer */ 430 std r7,PACAKSAVE(r13) 431 432 ld r6,_CCR(r1) 433 mtcrf 0xFF,r6 434 435#ifdef CONFIG_ALTIVEC 436BEGIN_FTR_SECTION 437 ld r0,THREAD_VRSAVE(r4) 438 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ 439END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 440#endif /* CONFIG_ALTIVEC */ 441 442 /* r3-r13 are destroyed -- Cort */ 443 REST_8GPRS(14, r1) 444 REST_10GPRS(22, r1) 445 446 /* convert old thread to its task_struct for return value */ 447 addi r3,r3,-THREAD 448 ld r7,_NIP(r1) /* Return to _switch caller in new task */ 449 mtlr r7 450 addi r1,r1,SWITCH_FRAME_SIZE 451 blr 452 453 .align 7 454_GLOBAL(ret_from_except) 455 ld r11,_TRAP(r1) 456 andi. r0,r11,1 457 bne .ret_from_except_lite 458 REST_NVGPRS(r1) 459 460_GLOBAL(ret_from_except_lite) 461 /* 462 * Disable interrupts so that current_thread_info()->flags 463 * can't change between when we test it and when we return 464 * from the interrupt. 465 */ 466 mfmsr r10 /* Get current interrupt state */ 467 rldicl r9,r10,48,1 /* clear MSR_EE */ 468 rotldi r9,r9,16 469 mtmsrd r9,1 /* Update machine state */ 470 471#ifdef CONFIG_PREEMPT 472 clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */ 473 li r0,_TIF_NEED_RESCHED /* bits to check */ 474 ld r3,_MSR(r1) 475 ld r4,TI_FLAGS(r9) 476 /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */ 477 rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING 478 and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */ 479 bne do_work 480 481#else /* !CONFIG_PREEMPT */ 482 ld r3,_MSR(r1) /* Returning to user mode? */ 483 andi. r3,r3,MSR_PR 484 beq restore /* if not, just restore regs and return */ 485 486 /* Check current_thread_info()->flags */ 487 clrrdi r9,r1,THREAD_SHIFT 488 ld r4,TI_FLAGS(r9) 489 andi. r0,r4,_TIF_USER_WORK_MASK 490 bne do_work 491#endif 492 493restore: 494 ld r5,SOFTE(r1) 495#ifdef CONFIG_PPC_ISERIES 496BEGIN_FW_FTR_SECTION 497 cmpdi 0,r5,0 498 beq 4f 499 /* Check for pending interrupts (iSeries) */ 500 ld r3,PACALPPACAPTR(r13) 501 ld r3,LPPACAANYINT(r3) 502 cmpdi r3,0 503 beq+ 4f /* skip do_IRQ if no interrupts */ 504 505 li r3,0 506 stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */ 507 ori r10,r10,MSR_EE 508 mtmsrd r10 /* hard-enable again */ 509 addi r3,r1,STACK_FRAME_OVERHEAD 510 bl .do_IRQ 511 b .ret_from_except_lite /* loop back and handle more */ 5124: 513END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 514#endif 515 stb r5,PACASOFTIRQEN(r13) 516 517 /* extract EE bit and use it to restore paca->hard_enabled */ 518 ld r3,_MSR(r1) 519 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */ 520 stb r4,PACAHARDIRQEN(r13) 521 522 ld r4,_CTR(r1) 523 ld r0,_LINK(r1) 524 mtctr r4 525 mtlr r0 526 ld r4,_XER(r1) 527 mtspr SPRN_XER,r4 528 529 REST_8GPRS(5, r1) 530 531 andi. r0,r3,MSR_RI 532 beq- unrecov_restore 533 534 stdcx. r0,0,r1 /* to clear the reservation */ 535 536 /* 537 * Clear RI before restoring r13. If we are returning to 538 * userspace and we take an exception after restoring r13, 539 * we end up corrupting the userspace r13 value. 540 */ 541 mfmsr r4 542 andc r4,r4,r0 /* r0 contains MSR_RI here */ 543 mtmsrd r4,1 544 545 /* 546 * r13 is our per cpu area, only restore it if we are returning to 547 * userspace 548 */ 549 andi. r0,r3,MSR_PR 550 beq 1f 551 ACCOUNT_CPU_USER_EXIT(r2, r4) 552 REST_GPR(13, r1) 5531: 554 mtspr SPRN_SRR1,r3 555 556 ld r2,_CCR(r1) 557 mtcrf 0xFF,r2 558 ld r2,_NIP(r1) 559 mtspr SPRN_SRR0,r2 560 561 ld r0,GPR0(r1) 562 ld r2,GPR2(r1) 563 ld r3,GPR3(r1) 564 ld r4,GPR4(r1) 565 ld r1,GPR1(r1) 566 567 rfid 568 b . /* prevent speculative execution */ 569 570do_work: 571#ifdef CONFIG_PREEMPT 572 andi. r0,r3,MSR_PR /* Returning to user mode? */ 573 bne user_work 574 /* Check that preempt_count() == 0 and interrupts are enabled */ 575 lwz r8,TI_PREEMPT(r9) 576 cmpwi cr1,r8,0 577 ld r0,SOFTE(r1) 578 cmpdi r0,0 579 crandc eq,cr1*4+eq,eq 580 bne restore 581 /* here we are preempting the current task */ 5821: 583 li r0,1 584 stb r0,PACASOFTIRQEN(r13) 585 stb r0,PACAHARDIRQEN(r13) 586 ori r10,r10,MSR_EE 587 mtmsrd r10,1 /* reenable interrupts */ 588 bl .preempt_schedule 589 mfmsr r10 590 clrrdi r9,r1,THREAD_SHIFT 591 rldicl r10,r10,48,1 /* disable interrupts again */ 592 rotldi r10,r10,16 593 mtmsrd r10,1 594 ld r4,TI_FLAGS(r9) 595 andi. r0,r4,_TIF_NEED_RESCHED 596 bne 1b 597 b restore 598 599user_work: 600#endif 601 /* Enable interrupts */ 602 ori r10,r10,MSR_EE 603 mtmsrd r10,1 604 605 andi. r0,r4,_TIF_NEED_RESCHED 606 beq 1f 607 bl .schedule 608 b .ret_from_except_lite 609 6101: bl .save_nvgprs 611 li r3,0 612 addi r4,r1,STACK_FRAME_OVERHEAD 613 bl .do_signal 614 b .ret_from_except 615 616unrecov_restore: 617 addi r3,r1,STACK_FRAME_OVERHEAD 618 bl .unrecoverable_exception 619 b unrecov_restore 620 621#ifdef CONFIG_PPC_RTAS 622/* 623 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be 624 * called with the MMU off. 625 * 626 * In addition, we need to be in 32b mode, at least for now. 627 * 628 * Note: r3 is an input parameter to rtas, so don't trash it... 629 */ 630_GLOBAL(enter_rtas) 631 mflr r0 632 std r0,16(r1) 633 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */ 634 635 /* Because RTAS is running in 32b mode, it clobbers the high order half 636 * of all registers that it saves. We therefore save those registers 637 * RTAS might touch to the stack. (r0, r3-r13 are caller saved) 638 */ 639 SAVE_GPR(2, r1) /* Save the TOC */ 640 SAVE_GPR(13, r1) /* Save paca */ 641 SAVE_8GPRS(14, r1) /* Save the non-volatiles */ 642 SAVE_10GPRS(22, r1) /* ditto */ 643 644 mfcr r4 645 std r4,_CCR(r1) 646 mfctr r5 647 std r5,_CTR(r1) 648 mfspr r6,SPRN_XER 649 std r6,_XER(r1) 650 mfdar r7 651 std r7,_DAR(r1) 652 mfdsisr r8 653 std r8,_DSISR(r1) 654 mfsrr0 r9 655 std r9,_SRR0(r1) 656 mfsrr1 r10 657 std r10,_SRR1(r1) 658 659 /* Temporary workaround to clear CR until RTAS can be modified to 660 * ignore all bits. 661 */ 662 li r0,0 663 mtcr r0 664 665#ifdef CONFIG_BUG 666 /* There is no way it is acceptable to get here with interrupts enabled, 667 * check it with the asm equivalent of WARN_ON 668 */ 669 lbz r0,PACASOFTIRQEN(r13) 6701: tdnei r0,0 671 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING 672#endif 673 674 /* Hard-disable interrupts */ 675 mfmsr r6 676 rldicl r7,r6,48,1 677 rotldi r7,r7,16 678 mtmsrd r7,1 679 680 /* Unfortunately, the stack pointer and the MSR are also clobbered, 681 * so they are saved in the PACA which allows us to restore 682 * our original state after RTAS returns. 683 */ 684 std r1,PACAR1(r13) 685 std r6,PACASAVEDMSR(r13) 686 687 /* Setup our real return addr */ 688 LOAD_REG_ADDR(r4,.rtas_return_loc) 689 clrldi r4,r4,2 /* convert to realmode address */ 690 mtlr r4 691 692 li r0,0 693 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI 694 andc r0,r6,r0 695 696 li r9,1 697 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) 698 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP 699 andc r6,r0,r9 700 ori r6,r6,MSR_RI 701 sync /* disable interrupts so SRR0/1 */ 702 mtmsrd r0 /* don't get trashed */ 703 704 LOAD_REG_ADDR(r4, rtas) 705 ld r5,RTASENTRY(r4) /* get the rtas->entry value */ 706 ld r4,RTASBASE(r4) /* get the rtas->base value */ 707 708 mtspr SPRN_SRR0,r5 709 mtspr SPRN_SRR1,r6 710 rfid 711 b . /* prevent speculative execution */ 712 713_STATIC(rtas_return_loc) 714 /* relocation is off at this point */ 715 mfspr r4,SPRN_SPRG3 /* Get PACA */ 716 clrldi r4,r4,2 /* convert to realmode address */ 717 718 mfmsr r6 719 li r0,MSR_RI 720 andc r6,r6,r0 721 sync 722 mtmsrd r6 723 724 ld r1,PACAR1(r4) /* Restore our SP */ 725 LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs) 726 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ 727 728 mtspr SPRN_SRR0,r3 729 mtspr SPRN_SRR1,r4 730 rfid 731 b . /* prevent speculative execution */ 732 733_STATIC(rtas_restore_regs) 734 /* relocation is on at this point */ 735 REST_GPR(2, r1) /* Restore the TOC */ 736 REST_GPR(13, r1) /* Restore paca */ 737 REST_8GPRS(14, r1) /* Restore the non-volatiles */ 738 REST_10GPRS(22, r1) /* ditto */ 739 740 mfspr r13,SPRN_SPRG3 741 742 ld r4,_CCR(r1) 743 mtcr r4 744 ld r5,_CTR(r1) 745 mtctr r5 746 ld r6,_XER(r1) 747 mtspr SPRN_XER,r6 748 ld r7,_DAR(r1) 749 mtdar r7 750 ld r8,_DSISR(r1) 751 mtdsisr r8 752 ld r9,_SRR0(r1) 753 mtsrr0 r9 754 ld r10,_SRR1(r1) 755 mtsrr1 r10 756 757 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */ 758 ld r0,16(r1) /* get return address */ 759 760 mtlr r0 761 blr /* return to caller */ 762 763#endif /* CONFIG_PPC_RTAS */ 764 765_GLOBAL(enter_prom) 766 mflr r0 767 std r0,16(r1) 768 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */ 769 770 /* Because PROM is running in 32b mode, it clobbers the high order half 771 * of all registers that it saves. We therefore save those registers 772 * PROM might touch to the stack. (r0, r3-r13 are caller saved) 773 */ 774 SAVE_8GPRS(2, r1) 775 SAVE_GPR(13, r1) 776 SAVE_8GPRS(14, r1) 777 SAVE_10GPRS(22, r1) 778 mfcr r4 779 std r4,_CCR(r1) 780 mfctr r5 781 std r5,_CTR(r1) 782 mfspr r6,SPRN_XER 783 std r6,_XER(r1) 784 mfdar r7 785 std r7,_DAR(r1) 786 mfdsisr r8 787 std r8,_DSISR(r1) 788 mfsrr0 r9 789 std r9,_SRR0(r1) 790 mfsrr1 r10 791 std r10,_SRR1(r1) 792 mfmsr r11 793 std r11,_MSR(r1) 794 795 /* Get the PROM entrypoint */ 796 ld r0,GPR4(r1) 797 mtlr r0 798 799 /* Switch MSR to 32 bits mode 800 */ 801 mfmsr r11 802 li r12,1 803 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) 804 andc r11,r11,r12 805 li r12,1 806 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) 807 andc r11,r11,r12 808 mtmsrd r11 809 isync 810 811 /* Restore arguments & enter PROM here... */ 812 ld r3,GPR3(r1) 813 blrl 814 815 /* Just make sure that r1 top 32 bits didn't get 816 * corrupt by OF 817 */ 818 rldicl r1,r1,0,32 819 820 /* Restore the MSR (back to 64 bits) */ 821 ld r0,_MSR(r1) 822 mtmsrd r0 823 isync 824 825 /* Restore other registers */ 826 REST_GPR(2, r1) 827 REST_GPR(13, r1) 828 REST_8GPRS(14, r1) 829 REST_10GPRS(22, r1) 830 ld r4,_CCR(r1) 831 mtcr r4 832 ld r5,_CTR(r1) 833 mtctr r5 834 ld r6,_XER(r1) 835 mtspr SPRN_XER,r6 836 ld r7,_DAR(r1) 837 mtdar r7 838 ld r8,_DSISR(r1) 839 mtdsisr r8 840 ld r9,_SRR0(r1) 841 mtsrr0 r9 842 ld r10,_SRR1(r1) 843 mtsrr1 r10 844 845 addi r1,r1,PROM_FRAME_SIZE 846 ld r0,16(r1) 847 mtlr r0 848 blr 849