LXR linux/arch/mips/sibyte/sb1250/irq.c

   1/*
   2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * as published by the Free Software Foundation; either version 2
   7 * of the License, or (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software
  16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17 */
  18#include <linux/kernel.h>
  19#include <linux/init.h>
  20#include <linux/linkage.h>
  21#include <linux/interrupt.h>
  22#include <linux/spinlock.h>
  23#include <linux/smp.h>
  24#include <linux/mm.h>
  25#include <linux/slab.h>
  26#include <linux/kernel_stat.h>
  27
  28#include <asm/errno.h>
  29#include <asm/signal.h>
  30#include <asm/system.h>
  31#include <asm/time.h>
  32#include <asm/io.h>
  33
  34#include <asm/sibyte/sb1250_regs.h>
  35#include <asm/sibyte/sb1250_int.h>
  36#include <asm/sibyte/sb1250_uart.h>
  37#include <asm/sibyte/sb1250_scd.h>
  38#include <asm/sibyte/sb1250.h>
  39
  40/*
  41 * These are the routines that handle all the low level interrupt stuff.
  42 * Actions handled here are: initialization of the interrupt map, requesting of
  43 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  44 * for interrupt lines
  45 */
  46
  47
  48static void end_sb1250_irq(unsigned int irq);
  49static void enable_sb1250_irq(unsigned int irq);
  50static void disable_sb1250_irq(unsigned int irq);
  51static void ack_sb1250_irq(unsigned int irq);
  52#ifdef CONFIG_SMP
  53static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
  54#endif
  55
  56#ifdef CONFIG_SIBYTE_HAS_LDT
  57extern unsigned long ldt_eoi_space;
  58#endif
  59
  60#ifdef CONFIG_KGDB
  61static int kgdb_irq;
  62
  63/* Default to UART1 */
  64int kgdb_port = 1;
  65#ifdef CONFIG_SERIAL_SB1250_DUART
  66extern char sb1250_duart_present[];
  67#endif
  68#endif
  69
  70static struct irq_chip sb1250_irq_type = {
  71        .name = "SB1250-IMR",
  72        .ack = ack_sb1250_irq,
  73        .mask = disable_sb1250_irq,
  74        .mask_ack = ack_sb1250_irq,
  75        .unmask = enable_sb1250_irq,
  76        .end = end_sb1250_irq,
  77#ifdef CONFIG_SMP
  78        .set_affinity = sb1250_set_affinity
  79#endif
  80};
  81
  82/* Store the CPU id (not the logical number) */
  83int sb1250_irq_owner[SB1250_NR_IRQS];
  84
  85DEFINE_SPINLOCK(sb1250_imr_lock);
  86
  87void sb1250_mask_irq(int cpu, int irq)
  88{
  89        unsigned long flags;
  90        u64 cur_ints;
  91
  92        spin_lock_irqsave(&sb1250_imr_lock, flags);
  93        cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  94                                        R_IMR_INTERRUPT_MASK));
  95        cur_ints |= (((u64) 1) << irq);
  96        ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
  97                                        R_IMR_INTERRUPT_MASK));
  98        spin_unlock_irqrestore(&sb1250_imr_lock, flags);
  99}
 100
 101void sb1250_unmask_irq(int cpu, int irq)
 102{
 103        unsigned long flags;
 104        u64 cur_ints;
 105
 106        spin_lock_irqsave(&sb1250_imr_lock, flags);
 107        cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 108                                        R_IMR_INTERRUPT_MASK));
 109        cur_ints &= ~(((u64) 1) << irq);
 110        ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 111                                        R_IMR_INTERRUPT_MASK));
 112        spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 113}
 114
 115#ifdef CONFIG_SMP
 116static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
 117{
 118        int i = 0, old_cpu, cpu, int_on;
 119        u64 cur_ints;
 120        struct irq_desc *desc = irq_desc + irq;
 121        unsigned long flags;
 122
 123        i = first_cpu(mask);
 124
 125        if (cpus_weight(mask) > 1) {
 126                printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 127                return;
 128        }
 129
 130        /* Convert logical CPU to physical CPU */
 131        cpu = cpu_logical_map(i);
 132
 133        /* Protect against other affinity changers and IMR manipulation */
 134        spin_lock_irqsave(&desc->lock, flags);
 135        spin_lock(&sb1250_imr_lock);
 136
 137        /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 138        old_cpu = sb1250_irq_owner[irq];
 139        cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
 140                                        R_IMR_INTERRUPT_MASK));
 141        int_on = !(cur_ints & (((u64) 1) << irq));
 142        if (int_on) {
 143                /* If it was on, mask it */
 144                cur_ints |= (((u64) 1) << irq);
 145                ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
 146                                        R_IMR_INTERRUPT_MASK));
 147        }
 148        sb1250_irq_owner[irq] = cpu;
 149        if (int_on) {
 150                /* unmask for the new CPU */
 151                cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 152                                        R_IMR_INTERRUPT_MASK));
 153                cur_ints &= ~(((u64) 1) << irq);
 154                ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 155                                        R_IMR_INTERRUPT_MASK));
 156        }
 157        spin_unlock(&sb1250_imr_lock);
 158        spin_unlock_irqrestore(&desc->lock, flags);
 159}
 160#endif
 161
 162/*****************************************************************************/
 163
 164static void disable_sb1250_irq(unsigned int irq)
 165{
 166        sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 167}
 168
 169static void enable_sb1250_irq(unsigned int irq)
 170{
 171        sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 172}
 173
 174
 175static void ack_sb1250_irq(unsigned int irq)
 176{
 177#ifdef CONFIG_SIBYTE_HAS_LDT
 178        u64 pending;
 179
 180        /*
 181         * If the interrupt was an HT interrupt, now is the time to
 182         * clear it.  NOTE: we assume the HT bridge was set up to
 183         * deliver the interrupts to all CPUs (which makes affinity
 184         * changing easier for us)
 185         */
 186        pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 187                                                    R_IMR_LDT_INTERRUPT)));
 188        pending &= ((u64)1 << (irq));
 189        if (pending) {
 190                int i;
 191                for (i=0; i<NR_CPUS; i++) {
 192                        int cpu;
 193#ifdef CONFIG_SMP
 194                        cpu = cpu_logical_map(i);
 195#else
 196                        cpu = i;
 197#endif
 198                        /*
 199                         * Clear for all CPUs so an affinity switch
 200                         * doesn't find an old status
 201                         */
 202                        __raw_writeq(pending,
 203                                     IOADDR(A_IMR_REGISTER(cpu,
 204                                                R_IMR_LDT_INTERRUPT_CLR)));
 205                }
 206
 207                /*
 208                 * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 209                 * Pass 2, the LDT world may be edge-triggered, but
 210                 * this EOI shouldn't hurt.  If they are
 211                 * level-sensitive, the EOI is required.
 212                 */
 213                *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 214        }
 215#endif
 216        sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 217}
 218
 219
 220static void end_sb1250_irq(unsigned int irq)
 221{
 222        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 223                sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 224        }
 225}
 226
 227
 228void __init init_sb1250_irqs(void)
 229{
 230        int i;
 231
 232        for (i = 0; i < SB1250_NR_IRQS; i++) {
 233                set_irq_chip(i, &sb1250_irq_type);
 234                sb1250_irq_owner[i] = 0;
 235        }
 236}
 237
 238
 239/*
 240 *  arch_init_irq is called early in the boot sequence from init/main.c via
 241 *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 242 *  installing the handler that will be responsible for dispatching interrupts
 243 *  to the "right" place.
 244 */
 245/*
 246 * For now, map all interrupts to IP[2].  We could save
 247 * some cycles by parceling out system interrupts to different
 248 * IP lines, but keep it simple for bringup.  We'll also direct
 249 * all interrupts to a single CPU; we should probably route
 250 * PCI and LDT to one cpu and everything else to the other
 251 * to balance the load a bit.
 252 *
 253 * On the second cpu, everything is set to IP5, which is
 254 * ignored, EXCEPT the mailbox interrupt.  That one is
 255 * set to IP[2] so it is handled.  This is needed so we
 256 * can do cross-cpu function calls, as requred by SMP
 257 */
 258
 259#define IMR_IP2_VAL     K_INT_MAP_I0
 260#define IMR_IP3_VAL     K_INT_MAP_I1
 261#define IMR_IP4_VAL     K_INT_MAP_I2
 262#define IMR_IP5_VAL     K_INT_MAP_I3
 263#define IMR_IP6_VAL     K_INT_MAP_I4
 264
 265void __init arch_init_irq(void)
 266{
 267
 268        unsigned int i;
 269        u64 tmp;
 270        unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 271                STATUSF_IP1 | STATUSF_IP0;
 272
 273        /* Default everything to IP2 */
 274        for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 275                __raw_writeq(IMR_IP2_VAL,
 276                             IOADDR(A_IMR_REGISTER(0,
 277                                                   R_IMR_INTERRUPT_MAP_BASE) +
 278                                    (i << 3)));
 279                __raw_writeq(IMR_IP2_VAL,
 280                             IOADDR(A_IMR_REGISTER(1,
 281                                                   R_IMR_INTERRUPT_MAP_BASE) +
 282                                    (i << 3)));
 283        }
 284
 285        init_sb1250_irqs();
 286
 287        /*
 288         * Map the high 16 bits of the mailbox registers to IP[3], for
 289         * inter-cpu messages
 290         */
 291        /* Was I1 */
 292        __raw_writeq(IMR_IP3_VAL,
 293                     IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 294                            (K_INT_MBOX_0 << 3)));
 295        __raw_writeq(IMR_IP3_VAL,
 296                     IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 297                            (K_INT_MBOX_0 << 3)));
 298
 299        /* Clear the mailboxes.  The firmware may leave them dirty */
 300        __raw_writeq(0xffffffffffffffffULL,
 301                     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 302        __raw_writeq(0xffffffffffffffffULL,
 303                     IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 304
 305        /* Mask everything except the mailbox registers for both cpus */
 306        tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 307        __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 308        __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 309
 310        /*
 311         * Note that the timer interrupts are also mapped, but this is
 312         * done in sb1250_time_init().  Also, the profiling driver
 313         * does its own management of IP7.
 314         */
 315
 316#ifdef CONFIG_KGDB
 317        imask |= STATUSF_IP6;
 318#endif
 319        /* Enable necessary IPs, disable the rest */
 320        change_c0_status(ST0_IM, imask);
 321
 322#ifdef CONFIG_KGDB
 323        if (kgdb_flag) {
 324                kgdb_irq = K_INT_UART_0 + kgdb_port;
 325
 326#ifdef CONFIG_SERIAL_SB1250_DUART
 327                sb1250_duart_present[kgdb_port] = 0;
 328#endif
 329                /* Setup uart 1 settings, mapper */
 330                __raw_writeq(M_DUART_IMR_BRK,
 331                             IOADDR(A_DUART_IMRREG(kgdb_port)));
 332
 333                __raw_writeq(IMR_IP6_VAL,
 334                             IOADDR(A_IMR_REGISTER(0,
 335                                                   R_IMR_INTERRUPT_MAP_BASE) +
 336                                    (kgdb_irq << 3)));
 337                sb1250_unmask_irq(0, kgdb_irq);
 338        }
 339#endif
 340}
 341
 342#ifdef CONFIG_KGDB
 343
 344#include <linux/delay.h>
 345
 346#define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
 347#define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
 348
 349static void sb1250_kgdb_interrupt(void)
 350{
 351        /*
 352         * Clear break-change status (allow some time for the remote
 353         * host to stop the break, since we would see another
 354         * interrupt on the end-of-break too)
 355         */
 356        kstat_this_cpu.irqs[kgdb_irq]++;
 357        mdelay(500);
 358        duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
 359                                M_DUART_RX_EN | M_DUART_TX_EN);
 360        set_async_breakpoint(&get_irq_regs()->cp0_epc);
 361}
 362
 363#endif  /* CONFIG_KGDB */
 364
 365extern void sb1250_mailbox_interrupt(void);
 366
 367static inline void dispatch_ip2(void)
 368{
 369        unsigned int cpu = smp_processor_id();
 370        unsigned long long mask;
 371
 372        /*
 373         * Default...we've hit an IP[2] interrupt, which means we've got to
 374         * check the 1250 interrupt registers to figure out what to do.  Need
 375         * to detect which CPU we're on, now that smp_affinity is supported.
 376         */
 377        mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
 378                                  R_IMR_INTERRUPT_STATUS_BASE)));
 379        if (mask)
 380                do_IRQ(fls64(mask) - 1);
 381}
 382
 383asmlinkage void plat_irq_dispatch(void)
 384{
 385        unsigned int cpu = smp_processor_id();
 386        unsigned int pending;
 387
 388        /*
 389         * What a pain. We have to be really careful saving the upper 32 bits
 390         * of any * register across function calls if we don't want them
 391         * trashed--since were running in -o32, the calling routing never saves
 392         * the full 64 bits of a register across a function call.  Being the
 393         * interrupt handler, we're guaranteed that interrupts are disabled
 394         * during this code so we don't have to worry about random interrupts
 395         * blasting the high 32 bits.
 396         */
 397
 398        pending = read_c0_cause() & read_c0_status() & ST0_IM;
 399
 400        if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
 401                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 402        else if (pending & CAUSEF_IP4)
 403                do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
 404
 405#ifdef CONFIG_SMP
 406        else if (pending & CAUSEF_IP3)
 407                sb1250_mailbox_interrupt();
 408#endif
 409
 410#ifdef CONFIG_KGDB
 411        else if (pending & CAUSEF_IP6)                  /* KGDB (uart 1) */
 412                sb1250_kgdb_interrupt();
 413#endif
 414
 415        else if (pending & CAUSEF_IP2)
 416                dispatch_ip2();
 417        else
 418                spurious_interrupt();
 419}
 420