LXR linux/arch/alpha/lib/memset.S

   1/*
   2 * linux/arch/alpha/lib/memset.S
   3 *
   4 * This is an efficient (and small) implementation of the C library "memset()"
   5 * function for the alpha.
   6 *
   7 *      (C) Copyright 1996 Linus Torvalds
   8 *
   9 * This routine is "moral-ware": you are free to use it any way you wish, and
  10 * the only obligation I put on you is a moral one: if you make any improvements
  11 * to the routine, please send me your improvements for me to use similarly.
  12 *
  13 * The scheduling comments are according to the EV5 documentation (and done by 
  14 * hand, so they might well be incorrect, please do tell me about it..)
  15 */
  16
  17        .set noat
  18        .set noreorder
  19.text
  20        .globl memset
  21        .globl __memset
  22        .globl __memsetw
  23        .globl __constant_c_memset
  24        .ent __memset
  25.align 5
  26__memset:
  27        .frame $30,0,$26,0
  28        .prologue 0
  29
  30        and $17,255,$1          /* E1 */
  31        insbl $17,1,$17         /* .. E0 */
  32        bis $17,$1,$17          /* E0 (p-c latency, next cycle) */
  33        sll $17,16,$1           /* E1 (p-c latency, next cycle) */
  34
  35        bis $17,$1,$17          /* E0 (p-c latency, next cycle) */
  36        sll $17,32,$1           /* E1 (p-c latency, next cycle) */
  37        bis $17,$1,$17          /* E0 (p-c latency, next cycle) */
  38        ldq_u $31,0($30)        /* .. E1 */
  39
  40.align 5
  41__constant_c_memset:
  42        addq $18,$16,$6         /* E0 */
  43        bis $16,$16,$0          /* .. E1 */
  44        xor $16,$6,$1           /* E0 */
  45        ble $18,end             /* .. E1 */
  46
  47        bic $1,7,$1             /* E0 */
  48        beq $1,within_one_quad  /* .. E1 (note EV5 zero-latency forwarding) */
  49        and $16,7,$3            /* E0 */
  50        beq $3,aligned          /* .. E1 (note EV5 zero-latency forwarding) */
  51
  52        ldq_u $4,0($16)         /* E0 */
  53        bis $16,$16,$5          /* .. E1 */
  54        insql $17,$16,$2        /* E0 */
  55        subq $3,8,$3            /* .. E1 */
  56
  57        addq $18,$3,$18         /* E0   $18 is new count ($3 is negative) */
  58        mskql $4,$16,$4         /* .. E1 (and possible load stall) */
  59        subq $16,$3,$16         /* E0   $16 is new aligned destination */
  60        bis $2,$4,$1            /* .. E1 */
  61
  62        bis $31,$31,$31         /* E0 */
  63        ldq_u $31,0($30)        /* .. E1 */
  64        stq_u $1,0($5)          /* E0 */
  65        bis $31,$31,$31         /* .. E1 */
  66
  67.align 4
  68aligned:
  69        sra $18,3,$3            /* E0 */
  70        and $18,7,$18           /* .. E1 */
  71        bis $16,$16,$5          /* E0 */
  72        beq $3,no_quad          /* .. E1 */
  73
  74.align 3
  75loop:
  76        stq $17,0($5)           /* E0 */
  77        subq $3,1,$3            /* .. E1 */
  78        addq $5,8,$5            /* E0 */
  79        bne $3,loop             /* .. E1 */
  80
  81no_quad:
  82        bis $31,$31,$31         /* E0 */
  83        beq $18,end             /* .. E1 */
  84        ldq $7,0($5)            /* E0 */
  85        mskqh $7,$6,$2          /* .. E1 (and load stall) */
  86
  87        insqh $17,$6,$4         /* E0 */
  88        bis $2,$4,$1            /* .. E1 */
  89        stq $1,0($5)            /* E0 */
  90        ret $31,($26),1         /* .. E1 */
  91
  92.align 3
  93within_one_quad:
  94        ldq_u $1,0($16)         /* E0 */
  95        insql $17,$16,$2        /* E1 */
  96        mskql $1,$16,$4         /* E0 (after load stall) */
  97        bis $2,$4,$2            /* E0 */
  98
  99        mskql $2,$6,$4          /* E0 */
 100        mskqh $1,$6,$2          /* .. E1 */
 101        bis $2,$4,$1            /* E0 */
 102        stq_u $1,0($16)         /* E0 */
 103
 104end:
 105        ret $31,($26),1         /* E1 */
 106        .end __memset
 107
 108        .align 5
 109        .ent __memsetw
 110__memsetw:
 111        .prologue 0
 112
 113        inswl $17,0,$1          /* E0 */
 114        inswl $17,2,$2          /* E0 */
 115        inswl $17,4,$3          /* E0 */
 116        or $1,$2,$1             /* .. E1 */
 117        inswl $17,6,$4          /* E0 */
 118        or $1,$3,$1             /* .. E1 */
 119        or $1,$4,$17            /* E0 */
 120        br __constant_c_memset  /* .. E1 */
 121
 122        .end __memsetw
 123
 124memset = __memset
 125