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146#include <linux/module.h>
147#include <linux/kernel.h>
148#include <linux/string.h>
149#include <linux/errno.h>
150#include <linux/ioport.h>
151#include <linux/slab.h>
152#include <linux/interrupt.h>
153#include <linux/delay.h>
154#include <linux/init.h>
155#include <linux/crc32.h>
156#include <linux/netdevice.h>
157#include <linux/etherdevice.h>
158#include <linux/skbuff.h>
159#include <linux/ethtool.h>
160#include <linux/time.h>
161#include <linux/types.h>
162#include <linux/unistd.h>
163#include <linux/ctype.h>
164#include <linux/bitops.h>
165
166#include <asm/io.h>
167#include <asm/dma.h>
168#include <asm/uaccess.h>
169
170#include "ewrk3.h"
171
172#define DRV_NAME "ewrk3"
173#define DRV_VERSION "0.48"
174
175static char version[] __initdata =
176DRV_NAME ":v" DRV_VERSION " 2002/10/18 davies@maniac.ultranet.com\n";
177
178#ifdef EWRK3_DEBUG
179static int ewrk3_debug = EWRK3_DEBUG;
180#else
181static int ewrk3_debug = 1;
182#endif
183
184#define EWRK3_NDA 0xffe0
185
186#define PROBE_LENGTH 32
187#define ETH_PROM_SIG 0xAA5500FFUL
188
189#ifndef EWRK3_SIGNATURE
190#define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
191#define EWRK3_STRLEN 8
192#endif
193
194#ifndef EWRK3_RAM_BASE_ADDRESSES
195#define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
196#endif
197
198
199
200
201#define EWRK3_IO_BASE 0x100
202#define EWRK3_IOP_INC 0x20
203#define EWRK3_TOTAL_SIZE 0x20
204
205#ifndef MAX_NUM_EWRK3S
206#define MAX_NUM_EWRK3S 21
207#endif
208
209#ifndef EWRK3_EISA_IO_PORTS
210#define EWRK3_EISA_IO_PORTS 0x0c00
211#endif
212
213#ifndef MAX_EISA_SLOTS
214#define MAX_EISA_SLOTS 16
215#define EISA_SLOT_INC 0x1000
216#endif
217
218#define QUEUE_PKT_TIMEOUT (1*HZ)
219
220
221
222
223#define IO_ONLY 0x00
224#define SHMEM_2K 0x800
225#define SHMEM_32K 0x8000
226#define SHMEM_64K 0x10000
227
228
229
230
231#define ENABLE_IRQs { \
232 icr |= lp->irq_mask;\
233 outb(icr, EWRK3_ICR); \
234}
235
236#define DISABLE_IRQs { \
237 icr = inb(EWRK3_ICR);\
238 icr &= ~lp->irq_mask;\
239 outb(icr, EWRK3_ICR); \
240}
241
242
243
244
245#define START_EWRK3 { \
246 csr = inb(EWRK3_CSR);\
247 csr &= ~(CSR_TXD|CSR_RXD);\
248 outb(csr, EWRK3_CSR); \
249}
250
251#define STOP_EWRK3 { \
252 csr = (CSR_TXD|CSR_RXD);\
253 outb(csr, EWRK3_CSR); \
254}
255
256
257
258
259#define EWRK3_PKT_STAT_SZ 16
260#define EWRK3_PKT_BIN_SZ 128
261
262
263struct ewrk3_stats {
264 u32 bins[EWRK3_PKT_STAT_SZ];
265 u32 unicast;
266 u32 multicast;
267 u32 broadcast;
268 u32 excessive_collisions;
269 u32 tx_underruns;
270 u32 excessive_underruns;
271};
272
273struct ewrk3_private {
274 char adapter_name[80];
275 u_long shmem_base;
276 void __iomem *shmem;
277 u_long shmem_length;
278 struct ewrk3_stats pktStats;
279 u_char irq_mask;
280 u_char mPage;
281 u_char lemac;
282 u_char hard_strapped;
283 u_char txc;
284 void __iomem *mctbl;
285 u_char led_mask;
286 spinlock_t hw_lock;
287};
288
289
290
291
292#define FORCE_2K_MODE { \
293 shmem_length = SHMEM_2K;\
294 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
295}
296
297
298
299
300static int ewrk3_open(struct net_device *dev);
301static int ewrk3_queue_pkt(struct sk_buff *skb, struct net_device *dev);
302static irqreturn_t ewrk3_interrupt(int irq, void *dev_id);
303static int ewrk3_close(struct net_device *dev);
304static void set_multicast_list(struct net_device *dev);
305static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
306static const struct ethtool_ops ethtool_ops_203;
307static const struct ethtool_ops ethtool_ops;
308
309
310
311
312static int ewrk3_hw_init(struct net_device *dev, u_long iobase);
313static void ewrk3_init(struct net_device *dev);
314static int ewrk3_rx(struct net_device *dev);
315static int ewrk3_tx(struct net_device *dev);
316static void ewrk3_timeout(struct net_device *dev);
317
318static void EthwrkSignature(char *name, char *eeprom_image);
319static int DevicePresent(u_long iobase);
320static void SetMulticastFilter(struct net_device *dev);
321static int EISA_signature(char *name, s32 eisa_id);
322
323static int Read_EEPROM(u_long iobase, u_char eaddr);
324static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
325static u_char get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType);
326
327static int ewrk3_probe1(struct net_device *dev, u_long iobase, int irq);
328static int isa_probe(struct net_device *dev, u_long iobase);
329static int eisa_probe(struct net_device *dev, u_long iobase);
330
331static u_char irq[MAX_NUM_EWRK3S+1] = {5, 0, 10, 3, 11, 9, 15, 12};
332
333static char name[EWRK3_STRLEN + 1];
334static int num_ewrks3s;
335
336
337
338
339#define INIT_EWRK3 {\
340 outb(EEPROM_INIT, EWRK3_IOPR);\
341 mdelay(1);\
342}
343
344#ifndef MODULE
345struct net_device * __init ewrk3_probe(int unit)
346{
347 struct net_device *dev = alloc_etherdev(sizeof(struct ewrk3_private));
348 int err;
349
350 if (!dev)
351 return ERR_PTR(-ENOMEM);
352
353 if (unit >= 0) {
354 sprintf(dev->name, "eth%d", unit);
355 netdev_boot_setup_check(dev);
356 }
357
358 err = ewrk3_probe1(dev, dev->base_addr, dev->irq);
359 if (err)
360 goto out;
361 return dev;
362out:
363 free_netdev(dev);
364 return ERR_PTR(err);
365
366}
367#endif
368
369static int __init ewrk3_probe1(struct net_device *dev, u_long iobase, int irq)
370{
371 int err;
372
373 dev->base_addr = iobase;
374 dev->irq = irq;
375
376
377 err = isa_probe(dev, iobase);
378 if (err != 0)
379 err = eisa_probe(dev, iobase);
380
381 if (err)
382 return err;
383
384 err = register_netdev(dev);
385 if (err)
386 release_region(dev->base_addr, EWRK3_TOTAL_SIZE);
387
388 return err;
389}
390
391static int __init
392ewrk3_hw_init(struct net_device *dev, u_long iobase)
393{
394 struct ewrk3_private *lp;
395 int i, status = 0;
396 u_long mem_start, shmem_length;
397 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
398 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
399 DECLARE_MAC_BUF(mac);
400
401
402
403
404
405 if (iobase > 0x400)
406 eisa_cr = inb(EISA_CR);
407 INIT_EWRK3;
408
409 nicsr = inb(EWRK3_CSR);
410
411 icr = inb(EWRK3_ICR);
412 icr &= 0x70;
413 outb(icr, EWRK3_ICR);
414
415 if (nicsr != (CSR_TXD | CSR_RXD))
416 return -ENXIO;
417
418
419 for (chksum = 0, i = 0; i < EEPROM_MAX; i += 2) {
420 union {
421 short val;
422 char c[2];
423 } tmp;
424
425 tmp.val = (short) Read_EEPROM(iobase, (i >> 1));
426 eeprom_image[i] = tmp.c[0];
427 eeprom_image[i + 1] = tmp.c[1];
428 chksum += eeprom_image[i] + eeprom_image[i + 1];
429 }
430
431 if (chksum != 0) {
432 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
433 return -ENXIO;
434 }
435
436 EthwrkSignature(name, eeprom_image);
437 if (*name == '\0')
438 return -ENXIO;
439
440 dev->base_addr = iobase;
441
442 if (iobase > 0x400) {
443 outb(eisa_cr, EISA_CR);
444 }
445 lemac = eeprom_image[EEPROM_CHIPVER];
446 cmr = inb(EWRK3_CMR);
447
448 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
449 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
450 printk("%s: %s at %#4lx", dev->name, name, iobase);
451 hard_strapped = 1;
452 } else if ((iobase & 0x0fff) == EWRK3_EISA_IO_PORTS) {
453
454 printk("%s: %s at %#4lx (EISA slot %ld)",
455 dev->name, name, iobase, ((iobase >> 12) & 0x0f));
456 } else {
457 printk("%s: %s at %#4lx", dev->name, name, iobase);
458 }
459
460 printk(", h/w address ");
461 if (lemac != LeMAC2)
462 DevicePresent(iobase);
463 status = get_hw_addr(dev, eeprom_image, lemac);
464 printk("%s\n", print_mac(mac, dev->dev_addr));
465
466 if (status) {
467 printk(" which has an EEPROM CRC error.\n");
468 return -ENXIO;
469 }
470
471 if (lemac == LeMAC2) {
472 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
473 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD)
474 cmr |= CMR_RA;
475 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND)
476 cmr |= CMR_WB;
477 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL)
478 cmr |= CMR_POLARITY;
479 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK)
480 cmr |= CMR_LINK;
481 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA)
482 cmr |= CMR_0WS;
483 }
484 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM)
485 cmr |= CMR_DRAM;
486 outb(cmr, EWRK3_CMR);
487
488 cr = inb(EWRK3_CR);
489 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
490 if (cr & SETUP_APD)
491 cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
492 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
493 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
494 outb(cr, EWRK3_CR);
495
496
497
498
499
500 mem_start = inb(EWRK3_MBR);
501 shmem_length = 0;
502 if (mem_start != 0) {
503 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
504 mem_start *= SHMEM_64K;
505 shmem_length = SHMEM_64K;
506 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
507 mem_start *= SHMEM_32K;
508 shmem_length = SHMEM_32K;
509 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
510 mem_start = mem_start * SHMEM_2K + 0x80000;
511 shmem_length = SHMEM_2K;
512 } else {
513 return -ENXIO;
514 }
515 }
516
517
518
519
520
521
522 if (hard_strapped) {
523 printk(" is hard strapped.\n");
524 } else if (mem_start) {
525 printk(" has a %dk RAM window", (int) (shmem_length >> 10));
526 printk(" at 0x%.5lx", mem_start);
527 } else {
528 printk(" is in I/O only mode");
529 }
530
531 lp = netdev_priv(dev);
532 lp->shmem_base = mem_start;
533 lp->shmem = ioremap(mem_start, shmem_length);
534 if (!lp->shmem)
535 return -ENOMEM;
536 lp->shmem_length = shmem_length;
537 lp->lemac = lemac;
538 lp->hard_strapped = hard_strapped;
539 lp->led_mask = CR_LED;
540 spin_lock_init(&lp->hw_lock);
541
542 lp->mPage = 64;
543 if (cmr & CMR_DRAM)
544 lp->mPage <<= 1;
545
546 sprintf(lp->adapter_name, "%s (%s)", name, dev->name);
547
548 lp->irq_mask = ICR_TNEM | ICR_TXDM | ICR_RNEM | ICR_RXDM;
549
550 if (!hard_strapped) {
551
552
553
554 icr |= ICR_IE;
555 outb(icr, EWRK3_ICR);
556
557
558 dev->dma = 0;
559
560
561
562 if (dev->irq < 2) {
563#ifndef MODULE
564 u_char irqnum;
565 unsigned long irq_mask;
566
567
568 irq_mask = probe_irq_on();
569
570
571
572
573 icr |= ICR_TNEM;
574 outb(1, EWRK3_TDQ);
575 outb(icr, EWRK3_ICR);
576
577 irqnum = irq[((icr & IRQ_SEL) >> 4)];
578
579 mdelay(20);
580 dev->irq = probe_irq_off(irq_mask);
581 if ((dev->irq) && (irqnum == dev->irq)) {
582 printk(" and uses IRQ%d.\n", dev->irq);
583 } else {
584 if (!dev->irq) {
585 printk(" and failed to detect IRQ line.\n");
586 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
587 printk(" and an illegal IRQ line detected.\n");
588 } else {
589 printk(", but incorrect IRQ line detected.\n");
590 }
591 iounmap(lp->shmem);
592 return -ENXIO;
593 }
594
595 DISABLE_IRQs;
596
597#endif
598 } else {
599 printk(" and requires IRQ%d.\n", dev->irq);
600 }
601 }
602
603 if (ewrk3_debug > 1) {
604 printk(version);
605 }
606
607 dev->open = ewrk3_open;
608 dev->hard_start_xmit = ewrk3_queue_pkt;
609 dev->stop = ewrk3_close;
610 dev->set_multicast_list = set_multicast_list;
611 dev->do_ioctl = ewrk3_ioctl;
612 if (lp->adapter_name[4] == '3')
613 SET_ETHTOOL_OPS(dev, ðtool_ops_203);
614 else
615 SET_ETHTOOL_OPS(dev, ðtool_ops);
616 dev->tx_timeout = ewrk3_timeout;
617 dev->watchdog_timeo = QUEUE_PKT_TIMEOUT;
618
619 dev->mem_start = 0;
620
621 return 0;
622}
623
624
625static int ewrk3_open(struct net_device *dev)
626{
627 struct ewrk3_private *lp = netdev_priv(dev);
628 u_long iobase = dev->base_addr;
629 int status = 0;
630 u_char icr, csr;
631
632
633
634
635 STOP_EWRK3;
636
637 if (!lp->hard_strapped) {
638 if (request_irq(dev->irq, (void *) ewrk3_interrupt, 0, "ewrk3", dev)) {
639 printk("ewrk3_open(): Requested IRQ%d is busy\n", dev->irq);
640 status = -EAGAIN;
641 } else {
642
643
644
645
646 ewrk3_init(dev);
647
648 if (ewrk3_debug > 1) {
649 DECLARE_MAC_BUF(mac);
650 printk("%s: ewrk3 open with irq %d\n", dev->name, dev->irq);
651 printk(" physical address: %s\n",
652 print_mac(mac, dev->dev_addr));
653 if (lp->shmem_length == 0) {
654 printk(" no shared memory, I/O only mode\n");
655 } else {
656 printk(" start of shared memory: 0x%08lx\n", lp->shmem_base);
657 printk(" window length: 0x%04lx\n", lp->shmem_length);
658 }
659 printk(" # of DRAMS: %d\n", ((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
660 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
661 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
662 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
663 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
664 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
665 }
666 netif_start_queue(dev);
667
668
669
670 icr = inb(EWRK3_ICR);
671 ENABLE_IRQs;
672
673 }
674 } else {
675 printk(KERN_ERR "%s: ewrk3 available for hard strapped set up only.\n", dev->name);
676 printk(KERN_ERR " Run the 'ewrk3setup' utility or remove the hard straps.\n");
677 return -EINVAL;
678 }
679
680 return status;
681}
682
683
684
685
686static void ewrk3_init(struct net_device *dev)
687{
688 struct ewrk3_private *lp = netdev_priv(dev);
689 u_char csr, page;
690 u_long iobase = dev->base_addr;
691 int i;
692
693
694
695
696 set_multicast_list(dev);
697
698
699
700
701
702 for (i=0; i<ETH_ALEN; i++)
703 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
704
705
706
707
708 while (inb(EWRK3_TQ));
709 while (inb(EWRK3_TDQ));
710 while (inb(EWRK3_RQ));
711 while (inb(EWRK3_FMQ));
712
713
714
715
716 for (page = 1; page < lp->mPage; page++) {
717 outb(page, EWRK3_FMQ);
718 }
719
720 START_EWRK3;
721}
722
723
724
725
726
727static void ewrk3_timeout(struct net_device *dev)
728{
729 struct ewrk3_private *lp = netdev_priv(dev);
730 u_char icr, csr;
731 u_long iobase = dev->base_addr;
732
733 if (!lp->hard_strapped)
734 {
735 printk(KERN_WARNING"%s: transmit timed/locked out, status %04x, resetting.\n",
736 dev->name, inb(EWRK3_CSR));
737
738
739
740
741 DISABLE_IRQs;
742
743
744
745
746 STOP_EWRK3;
747
748 ewrk3_init(dev);
749
750
751
752
753 ENABLE_IRQs;
754
755 dev->trans_start = jiffies;
756 netif_wake_queue(dev);
757 }
758}
759
760
761
762
763static int ewrk3_queue_pkt (struct sk_buff *skb, struct net_device *dev)
764{
765 struct ewrk3_private *lp = netdev_priv(dev);
766 u_long iobase = dev->base_addr;
767 void __iomem *buf = NULL;
768 u_char icr;
769 u_char page;
770
771 spin_lock_irq (&lp->hw_lock);
772 DISABLE_IRQs;
773
774
775 if (inb (EWRK3_FMQC) == 0) {
776 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): No free resources...\n",
777 dev->name);
778 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",
779 dev->name, inb (EWRK3_CSR), inb (EWRK3_ICR),
780 inb (EWRK3_FMQC));
781 goto err_out;
782 }
783
784
785
786
787 if ((page = inb (EWRK3_FMQ)) >= lp->mPage) {
788 printk ("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
789 (u_char) page);
790 goto err_out;
791 }
792
793
794
795
796
797 if (lp->shmem_length == IO_ONLY) {
798 outb (page, EWRK3_IOPR);
799 } else if (lp->shmem_length == SHMEM_2K) {
800 buf = lp->shmem;
801 outb (page, EWRK3_MPR);
802 } else if (lp->shmem_length == SHMEM_32K) {
803 buf = (((short) page << 11) & 0x7800) + lp->shmem;
804 outb ((page >> 4), EWRK3_MPR);
805 } else if (lp->shmem_length == SHMEM_64K) {
806 buf = (((short) page << 11) & 0xf800) + lp->shmem;
807 outb ((page >> 5), EWRK3_MPR);
808 } else {
809 printk (KERN_ERR "%s: Oops - your private data area is hosed!\n",
810 dev->name);
811 BUG ();
812 }
813
814
815
816
817
818 if (lp->shmem_length == IO_ONLY) {
819 int i;
820 u_char *p = skb->data;
821 outb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
822 outb ((char) (skb->len & 0xff), EWRK3_DATA);
823 outb ((char) ((skb->len >> 8) & 0xff), EWRK3_DATA);
824 outb ((char) 0x04, EWRK3_DATA);
825 for (i = 0; i < skb->len; i++) {
826 outb (*p++, EWRK3_DATA);
827 }
828 outb (page, EWRK3_TQ);
829 } else {
830 writeb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), buf);
831 buf += 1;
832 writeb ((char) (skb->len & 0xff), buf);
833 buf += 1;
834 if (lp->txc) {
835 writeb(((skb->len >> 8) & 0xff) | XCT, buf);
836 buf += 1;
837 writeb (0x04, buf);
838 buf += 1;
839 writeb (0x00, (buf + skb->len));
840 memcpy_toio (buf, skb->data, PRELOAD);
841 outb (page, EWRK3_TQ);
842 memcpy_toio (buf + PRELOAD,
843 skb->data + PRELOAD,
844 skb->len - PRELOAD);
845 writeb (0xff, (buf + skb->len));
846 } else {
847 writeb ((skb->len >> 8) & 0xff, buf);
848 buf += 1;
849 writeb (0x04, buf);
850 buf += 1;
851 memcpy_toio (buf, skb->data, skb->len);
852 outb (page, EWRK3_TQ);
853 }
854 }
855
856 ENABLE_IRQs;
857 spin_unlock_irq (&lp->hw_lock);
858
859 dev->stats.tx_bytes += skb->len;
860 dev->trans_start = jiffies;
861 dev_kfree_skb (skb);
862
863
864 if (inb (EWRK3_FMQC) == 0)
865 netif_stop_queue (dev);
866
867 return 0;
868
869err_out:
870 ENABLE_IRQs;
871 spin_unlock_irq (&lp->hw_lock);
872 return 1;
873}
874
875
876
877
878static irqreturn_t ewrk3_interrupt(int irq, void *dev_id)
879{
880 struct net_device *dev = dev_id;
881 struct ewrk3_private *lp;
882 u_long iobase;
883 u_char icr, cr, csr;
884
885 lp = netdev_priv(dev);
886 iobase = dev->base_addr;
887
888
889 csr = inb(EWRK3_CSR);
890
891
892
893
894 spin_lock(&lp->hw_lock);
895 DISABLE_IRQs;
896
897 cr = inb(EWRK3_CR);
898 cr |= lp->led_mask;
899 outb(cr, EWRK3_CR);
900
901 if (csr & CSR_RNE)
902 ewrk3_rx(dev);
903
904 if (csr & CSR_TNE)
905 ewrk3_tx(dev);
906
907
908
909
910
911
912
913 if (inb(EWRK3_FMQC)) {
914 lp->irq_mask |= ICR_TXDM | ICR_RXDM;
915 csr &= ~(CSR_TXD | CSR_RXD);
916 outb(csr, EWRK3_CSR);
917 netif_wake_queue(dev);
918 } else {
919 lp->irq_mask &= ~(ICR_TXDM | ICR_RXDM);
920 }
921
922
923 cr &= ~(lp->led_mask);
924 outb(cr, EWRK3_CR);
925 ENABLE_IRQs;
926 spin_unlock(&lp->hw_lock);
927 return IRQ_HANDLED;
928}
929
930
931static int ewrk3_rx(struct net_device *dev)
932{
933 struct ewrk3_private *lp = netdev_priv(dev);
934 u_long iobase = dev->base_addr;
935 int i, status = 0;
936 u_char page;
937 void __iomem *buf = NULL;
938
939 while (inb(EWRK3_RQC) && !status) {
940 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
941
942
943
944 if (lp->shmem_length == IO_ONLY) {
945 outb(page, EWRK3_IOPR);
946 } else if (lp->shmem_length == SHMEM_2K) {
947 buf = lp->shmem;
948 outb(page, EWRK3_MPR);
949 } else if (lp->shmem_length == SHMEM_32K) {
950 buf = (((short) page << 11) & 0x7800) + lp->shmem;
951 outb((page >> 4), EWRK3_MPR);
952 } else if (lp->shmem_length == SHMEM_64K) {
953 buf = (((short) page << 11) & 0xf800) + lp->shmem;
954 outb((page >> 5), EWRK3_MPR);
955 } else {
956 status = -1;
957 printk("%s: Oops - your private data area is hosed!\n", dev->name);
958 }
959
960 if (!status) {
961 char rx_status;
962 int pkt_len;
963
964 if (lp->shmem_length == IO_ONLY) {
965 rx_status = inb(EWRK3_DATA);
966 pkt_len = inb(EWRK3_DATA);
967 pkt_len |= ((u_short) inb(EWRK3_DATA) << 8);
968 } else {
969 rx_status = readb(buf);
970 buf += 1;
971 pkt_len = readw(buf);
972 buf += 3;
973 }
974
975 if (!(rx_status & R_ROK)) {
976 dev->stats.rx_errors++;
977 if (rx_status & R_DBE)
978 dev->stats.rx_frame_errors++;
979 if (rx_status & R_CRC)
980 dev->stats.rx_crc_errors++;
981 if (rx_status & R_PLL)
982 dev->stats.rx_fifo_errors++;
983 } else {
984 struct sk_buff *skb;
985
986 if ((skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
987 unsigned char *p;
988 skb_reserve(skb, 2);
989 p = skb_put(skb, pkt_len);
990
991 if (lp->shmem_length == IO_ONLY) {
992 *p = inb(EWRK3_DATA);
993 for (i = 0; i < pkt_len; i++) {
994 *p++ = inb(EWRK3_DATA);
995 }
996 } else {
997 memcpy_fromio(p, buf, pkt_len);
998 }
999
1000 for (i = 1; i < EWRK3_PKT_STAT_SZ - 1; i++) {
1001 if (pkt_len < i * EWRK3_PKT_BIN_SZ) {
1002 lp->pktStats.bins[i]++;
1003 i = EWRK3_PKT_STAT_SZ;
1004 }
1005 }
1006 p = skb->data;
1007 if (p[0] & 0x01) {
1008 if ((*(s16 *) & p[0] == -1) && (*(s16 *) & p[2] == -1) && (*(s16 *) & p[4] == -1)) {
1009 lp->pktStats.broadcast++;
1010 } else {
1011 lp->pktStats.multicast++;
1012 }
1013 } else if ((*(s16 *) & p[0] == *(s16 *) & dev->dev_addr[0]) &&
1014 (*(s16 *) & p[2] == *(s16 *) & dev->dev_addr[2]) &&
1015 (*(s16 *) & p[4] == *(s16 *) & dev->dev_addr[4])) {
1016 lp->pktStats.unicast++;
1017 }
1018 lp->pktStats.bins[0]++;
1019 if (lp->pktStats.bins[0] == 0) {
1020 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1021 }
1022
1023
1024
1025
1026 skb->protocol = eth_type_trans(skb, dev);
1027 netif_rx(skb);
1028
1029
1030
1031
1032 dev->last_rx = jiffies;
1033 dev->stats.rx_packets++;
1034 dev->stats.rx_bytes += pkt_len;
1035 } else {
1036 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1037 dev->stats.rx_dropped++;
1038 break;
1039 }
1040 }
1041 }
1042
1043
1044
1045 outb(page, EWRK3_FMQ);
1046 } else {
1047 printk("ewrk3_rx(): Illegal page number, page %d\n", page);
1048 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n", inb(EWRK3_CSR), inb(EWRK3_ICR), inb(EWRK3_FMQC));
1049 }
1050 }
1051 return status;
1052}
1053
1054
1055
1056
1057
1058static int ewrk3_tx(struct net_device *dev)
1059{
1060 struct ewrk3_private *lp = netdev_priv(dev);
1061 u_long iobase = dev->base_addr;
1062 u_char tx_status;
1063
1064 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1065 if (tx_status & T_VSTS) {
1066 if (tx_status & T_TXE) {
1067 dev->stats.tx_errors++;
1068 if (tx_status & T_NCL)
1069 dev->stats.tx_carrier_errors++;
1070 if (tx_status & T_LCL)
1071 dev->stats.tx_window_errors++;
1072 if (tx_status & T_CTU) {
1073 if ((tx_status & T_COLL) ^ T_XUR) {
1074 lp->pktStats.tx_underruns++;
1075 } else {
1076 lp->pktStats.excessive_underruns++;
1077 }
1078 } else if (tx_status & T_COLL) {
1079 if ((tx_status & T_COLL) ^ T_XCOLL) {
1080 dev->stats.collisions++;
1081 } else {
1082 lp->pktStats.excessive_collisions++;
1083 }
1084 }
1085 } else {
1086 dev->stats.tx_packets++;
1087 }
1088 }
1089 }
1090
1091 return 0;
1092}
1093
1094static int ewrk3_close(struct net_device *dev)
1095{
1096 struct ewrk3_private *lp = netdev_priv(dev);
1097 u_long iobase = dev->base_addr;
1098 u_char icr, csr;
1099
1100 netif_stop_queue(dev);
1101
1102 if (ewrk3_debug > 1) {
1103 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1104 dev->name, inb(EWRK3_CSR));
1105 }
1106
1107
1108
1109 DISABLE_IRQs;
1110
1111 STOP_EWRK3;
1112
1113
1114
1115
1116
1117
1118
1119 while (inb(EWRK3_TQ));
1120 while (inb(EWRK3_TDQ));
1121 while (inb(EWRK3_RQ));
1122
1123 if (!lp->hard_strapped) {
1124 free_irq(dev->irq, dev);
1125 }
1126 return 0;
1127}
1128
1129
1130
1131
1132static void set_multicast_list(struct net_device *dev)
1133{
1134 struct ewrk3_private *lp = netdev_priv(dev);
1135 u_long iobase = dev->base_addr;
1136 u_char csr;
1137
1138 csr = inb(EWRK3_CSR);
1139
1140 if (lp->shmem_length == IO_ONLY) {
1141 lp->mctbl = NULL;
1142 } else {
1143 lp->mctbl = lp->shmem + PAGE0_HTE;
1144 }
1145
1146 csr &= ~(CSR_PME | CSR_MCE);
1147 if (dev->flags & IFF_PROMISC) {
1148 csr |= CSR_PME;
1149 outb(csr, EWRK3_CSR);
1150 } else {
1151 SetMulticastFilter(dev);
1152 csr |= CSR_MCE;
1153 outb(csr, EWRK3_CSR);
1154 }
1155}
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165static void SetMulticastFilter(struct net_device *dev)
1166{
1167 struct ewrk3_private *lp = netdev_priv(dev);
1168 struct dev_mc_list *dmi = dev->mc_list;
1169 u_long iobase = dev->base_addr;
1170 int i;
1171 char *addrs, bit, byte;
1172 short __iomem *p = lp->mctbl;
1173 u16 hashcode;
1174 u32 crc;
1175
1176 spin_lock_irq(&lp->hw_lock);
1177
1178 if (lp->shmem_length == IO_ONLY) {
1179 outb(0, EWRK3_IOPR);
1180 outw(PAGE0_HTE, EWRK3_PIR1);
1181 } else {
1182 outb(0, EWRK3_MPR);
1183 }
1184
1185 if (dev->flags & IFF_ALLMULTI) {
1186 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1187 if (lp->shmem_length == IO_ONLY) {
1188 outb(0xff, EWRK3_DATA);
1189 } else {
1190 writew(0xffff, p);
1191 p++;
1192 i++;
1193 }
1194 }
1195 } else {
1196
1197 if (lp->shmem_length == IO_ONLY) {
1198 for (i = 0; i < (HASH_TABLE_LEN >> 4) - 1; i++) {
1199 outb(0x00, EWRK3_DATA);
1200 }
1201 outb(0x80, EWRK3_DATA);
1202 i++;
1203 for (; i < (HASH_TABLE_LEN >> 3); i++) {
1204 outb(0x00, EWRK3_DATA);
1205 }
1206 } else {
1207 memset_io(lp->mctbl, 0, HASH_TABLE_LEN >> 3);
1208 writeb(0x80, lp->mctbl + (HASH_TABLE_LEN >> 4) - 1);
1209 }
1210
1211
1212 for (i = 0; i < dev->mc_count; i++) {
1213 addrs = dmi->dmi_addr;
1214 dmi = dmi->next;
1215 if ((*addrs & 0x01) == 1) {
1216 crc = ether_crc_le(ETH_ALEN, addrs);
1217 hashcode = crc & ((1 << 9) - 1);
1218
1219 byte = hashcode >> 3;
1220 bit = 1 << (hashcode & 0x07);
1221
1222 if (lp->shmem_length == IO_ONLY) {
1223 u_char tmp;
1224
1225 outw(PAGE0_HTE + byte, EWRK3_PIR1);
1226 tmp = inb(EWRK3_DATA);
1227 tmp |= bit;
1228 outw(PAGE0_HTE + byte, EWRK3_PIR1);
1229 outb(tmp, EWRK3_DATA);
1230 } else {
1231 writeb(readb(lp->mctbl + byte) | bit, lp->mctbl + byte);
1232 }
1233 }
1234 }
1235 }
1236
1237 spin_unlock_irq(&lp->hw_lock);
1238}
1239
1240
1241
1242
1243static int __init isa_probe(struct net_device *dev, u_long ioaddr)
1244{
1245 int i = num_ewrks3s, maxSlots;
1246 int ret = -ENODEV;
1247
1248 u_long iobase;
1249
1250 if (ioaddr >= 0x400)
1251 goto out;
1252
1253 if (ioaddr == 0) {
1254 iobase = EWRK3_IO_BASE;
1255 maxSlots = 24;
1256 } else {
1257 iobase = ioaddr;
1258 maxSlots = i + 1;
1259 }
1260
1261 for (; (i < maxSlots) && (dev != NULL);
1262 iobase += EWRK3_IOP_INC, i++)
1263 {
1264 if (request_region(iobase, EWRK3_TOTAL_SIZE, DRV_NAME)) {
1265 if (DevicePresent(iobase) == 0) {
1266 int irq = dev->irq;
1267 ret = ewrk3_hw_init(dev, iobase);
1268 if (!ret)
1269 break;
1270 dev->irq = irq;
1271 }
1272 release_region(iobase, EWRK3_TOTAL_SIZE);
1273 }
1274 }
1275 out:
1276
1277 return ret;
1278}
1279
1280
1281
1282
1283
1284static int __init eisa_probe(struct net_device *dev, u_long ioaddr)
1285{
1286 int i, maxSlots;
1287 u_long iobase;
1288 int ret = -ENODEV;
1289
1290 if (ioaddr < 0x1000)
1291 goto out;
1292
1293 iobase = ioaddr;
1294 i = (ioaddr >> 12);
1295 maxSlots = i + 1;
1296
1297 for (i = 1; (i < maxSlots) && (dev != NULL); i++, iobase += EISA_SLOT_INC) {
1298 if (EISA_signature(name, EISA_ID) == 0) {
1299 if (request_region(iobase, EWRK3_TOTAL_SIZE, DRV_NAME) &&
1300 DevicePresent(iobase) == 0) {
1301 int irq = dev->irq;
1302 ret = ewrk3_hw_init(dev, iobase);
1303 if (!ret)
1304 break;
1305 dev->irq = irq;
1306 }
1307 release_region(iobase, EWRK3_TOTAL_SIZE);
1308 }
1309 }
1310
1311 out:
1312 return ret;
1313}
1314
1315
1316
1317
1318
1319static int Read_EEPROM(u_long iobase, u_char eaddr)
1320{
1321 int i;
1322
1323 outb((eaddr & 0x3f), EWRK3_PIR1);
1324 outb(EEPROM_RD, EWRK3_IOPR);
1325 for (i = 0; i < 5000; i++)
1326 inb(EWRK3_CSR);
1327
1328 return inw(EWRK3_EPROM1);
1329}
1330
1331
1332
1333
1334static int Write_EEPROM(short data, u_long iobase, u_char eaddr)
1335{
1336 int i;
1337
1338 outb(EEPROM_WR_EN, EWRK3_IOPR);
1339 for (i = 0; i < 5000; i++)
1340 inb(EWRK3_CSR);
1341 outw(data, EWRK3_EPROM1);
1342 outb((eaddr & 0x3f), EWRK3_PIR1);
1343 outb(EEPROM_WR, EWRK3_IOPR);
1344 for (i = 0; i < 75000; i++)
1345 inb(EWRK3_CSR);
1346 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1347 for (i = 0; i < 5000; i++)
1348 inb(EWRK3_CSR);
1349
1350 return 0;
1351}
1352
1353
1354
1355
1356static void __init EthwrkSignature(char *name, char *eeprom_image)
1357{
1358 int i;
1359 char *signatures[] = EWRK3_SIGNATURE;
1360
1361 for (i=0; *signatures[i] != '\0'; i++)
1362 if( !strncmp(eeprom_image+EEPROM_PNAME7, signatures[i], strlen(signatures[i])) )
1363 break;
1364
1365 if (*signatures[i] != '\0') {
1366 memcpy(name, eeprom_image+EEPROM_PNAME7, EWRK3_STRLEN);
1367 name[EWRK3_STRLEN] = '\0';
1368 } else
1369 name[0] = '\0';
1370
1371 return;
1372}
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386static int __init DevicePresent(u_long iobase)
1387{
1388 union {
1389 struct {
1390 u32 a;
1391 u32 b;
1392 } llsig;
1393 char Sig[sizeof(u32) << 1];
1394 }
1395 dev;
1396 short sigLength;
1397 char data;
1398 int i, j, status = 0;
1399
1400 dev.llsig.a = ETH_PROM_SIG;
1401 dev.llsig.b = ETH_PROM_SIG;
1402 sigLength = sizeof(u32) << 1;
1403
1404 for (i = 0, j = 0; j < sigLength && i < PROBE_LENGTH + sigLength - 1; i++) {
1405 data = inb(EWRK3_APROM);
1406 if (dev.Sig[j] == data) {
1407 j++;
1408 } else {
1409 if (data == dev.Sig[0]) {
1410 j = 1;
1411 } else {
1412 j = 0;
1413 }
1414 }
1415 }
1416
1417 if (j != sigLength) {
1418 status = -ENODEV;
1419 }
1420 return status;
1421}
1422
1423static u_char __init get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType)
1424{
1425 int i, j, k;
1426 u_short chksum;
1427 u_char crc, lfsr, sd, status = 0;
1428 u_long iobase = dev->base_addr;
1429 u16 tmp;
1430
1431 if (chipType == LeMAC2) {
1432 for (crc = 0x6a, j = 0; j < ETH_ALEN; j++) {
1433 sd = dev->dev_addr[j] = eeprom_image[EEPROM_PADDR0 + j];
1434 outb(dev->dev_addr[j], EWRK3_PAR0 + j);
1435 for (k = 0; k < 8; k++, sd >>= 1) {
1436 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1437 crc = (crc >> 1) + lfsr;
1438 }
1439 }
1440 if (crc != eeprom_image[EEPROM_PA_CRC])
1441 status = -1;
1442 } else {
1443 for (i = 0, k = 0; i < ETH_ALEN;) {
1444 k <<= 1;
1445 if (k > 0xffff)
1446 k -= 0xffff;
1447
1448 k += (u_char) (tmp = inb(EWRK3_APROM));
1449 dev->dev_addr[i] = (u_char) tmp;
1450 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1451 i++;
1452 k += (u_short) ((tmp = inb(EWRK3_APROM)) << 8);
1453 dev->dev_addr[i] = (u_char) tmp;
1454 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1455 i++;
1456
1457 if (k > 0xffff)
1458 k -= 0xffff;
1459 }
1460 if (k == 0xffff)
1461 k = 0;
1462 chksum = inb(EWRK3_APROM);
1463 chksum |= (inb(EWRK3_APROM) << 8);
1464 if (k != chksum)
1465 status = -1;
1466 }
1467
1468 return status;
1469}
1470
1471
1472
1473
1474static int __init EISA_signature(char *name, s32 eisa_id)
1475{
1476 u_long i;
1477 char *signatures[] = EWRK3_SIGNATURE;
1478 char ManCode[EWRK3_STRLEN];
1479 union {
1480 s32 ID;
1481 char Id[4];
1482 } Eisa;
1483 int status = 0;
1484
1485 *name = '\0';
1486 for (i = 0; i < 4; i++) {
1487 Eisa.Id[i] = inb(eisa_id + i);
1488 }
1489
1490 ManCode[0] = (((Eisa.Id[0] >> 2) & 0x1f) + 0x40);
1491 ManCode[1] = (((Eisa.Id[1] & 0xe0) >> 5) + ((Eisa.Id[0] & 0x03) << 3) + 0x40);
1492 ManCode[2] = (((Eisa.Id[2] >> 4) & 0x0f) + 0x30);
1493 ManCode[3] = ((Eisa.Id[2] & 0x0f) + 0x30);
1494 ManCode[4] = (((Eisa.Id[3] >> 4) & 0x0f) + 0x30);
1495 ManCode[5] = '\0';
1496
1497 for (i = 0; (*signatures[i] != '\0') && (*name == '\0'); i++) {
1498 if (strstr(ManCode, signatures[i]) != NULL) {
1499 strcpy(name, ManCode);
1500 status = 1;
1501 }
1502 }
1503
1504 return status;
1505}
1506
1507static void ewrk3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1508{
1509 int fwrev = Read_EEPROM(dev->base_addr, EEPROM_REVLVL);
1510
1511 strcpy(info->driver, DRV_NAME);
1512 strcpy(info->version, DRV_VERSION);
1513 sprintf(info->fw_version, "%d", fwrev);
1514 strcpy(info->bus_info, "N/A");
1515 info->eedump_len = EEPROM_MAX;
1516}
1517
1518static int ewrk3_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1519{
1520 struct ewrk3_private *lp = netdev_priv(dev);
1521 unsigned long iobase = dev->base_addr;
1522 u8 cr = inb(EWRK3_CR);
1523
1524 switch (lp->adapter_name[4]) {
1525 case '3':
1526 ecmd->supported = SUPPORTED_BNC;
1527 ecmd->port = PORT_BNC;
1528 break;
1529
1530 case '4':
1531 ecmd->supported = SUPPORTED_TP;
1532 ecmd->port = PORT_TP;
1533 break;
1534
1535 case '5':
1536 ecmd->supported = SUPPORTED_TP | SUPPORTED_BNC | SUPPORTED_AUI;
1537 ecmd->autoneg = !(cr & CR_APD);
1538
1539
1540
1541
1542 if (!ecmd->autoneg)
1543 ecmd->port = (cr & CR_PSEL) ? PORT_BNC : PORT_TP;
1544 break;
1545 }
1546
1547 ecmd->supported |= SUPPORTED_10baseT_Half;
1548 ecmd->speed = SPEED_10;
1549 ecmd->duplex = DUPLEX_HALF;
1550 return 0;
1551}
1552
1553static int ewrk3_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1554{
1555 struct ewrk3_private *lp = netdev_priv(dev);
1556 unsigned long iobase = dev->base_addr;
1557 unsigned long flags;
1558 u8 cr;
1559
1560
1561 if (lp->adapter_name[4] != '5')
1562 return -EOPNOTSUPP;
1563
1564
1565 if (ecmd->speed != SPEED_10)
1566 return -EINVAL;
1567 if (ecmd->port != PORT_TP && ecmd->port != PORT_BNC)
1568 return -EINVAL;
1569 if (ecmd->transceiver != XCVR_INTERNAL)
1570 return -EINVAL;
1571 if (ecmd->duplex != DUPLEX_HALF)
1572 return -EINVAL;
1573 if (ecmd->phy_address != 0)
1574 return -EINVAL;
1575
1576 spin_lock_irqsave(&lp->hw_lock, flags);
1577 cr = inb(EWRK3_CR);
1578
1579
1580
1581 if (ecmd->autoneg) {
1582 cr &= ~CR_APD;
1583 } else {
1584 cr |= CR_APD;
1585 if (ecmd->port == PORT_TP)
1586 cr &= ~CR_PSEL;
1587 else
1588 cr |= CR_PSEL;
1589 }
1590
1591
1592 outb(cr, EWRK3_CR);
1593 spin_unlock_irqrestore(&lp->hw_lock, flags);
1594 return 0;
1595}
1596
1597static u32 ewrk3_get_link(struct net_device *dev)
1598{
1599 unsigned long iobase = dev->base_addr;
1600 u8 cmr = inb(EWRK3_CMR);
1601
1602
1603
1604 return !(cmr & CMR_LINK);
1605}
1606
1607static int ewrk3_phys_id(struct net_device *dev, u32 data)
1608{
1609 struct ewrk3_private *lp = netdev_priv(dev);
1610 unsigned long iobase = dev->base_addr;
1611 unsigned long flags;
1612 u8 cr;
1613 int count;
1614
1615
1616 count = data << 2;
1617
1618 spin_lock_irqsave(&lp->hw_lock, flags);
1619
1620
1621 if (lp->led_mask == 0) {
1622 spin_unlock_irqrestore(&lp->hw_lock, flags);
1623 return -EBUSY;
1624 }
1625
1626
1627 lp->led_mask = 0;
1628
1629 while (count--) {
1630
1631 cr = inb(EWRK3_CR);
1632 outb(cr ^ CR_LED, EWRK3_CR);
1633
1634
1635 spin_unlock_irqrestore(&lp->hw_lock, flags);
1636 msleep(250);
1637 spin_lock_irqsave(&lp->hw_lock, flags);
1638
1639
1640 if (signal_pending(current))
1641 break;
1642 }
1643
1644 lp->led_mask = CR_LED;
1645 cr = inb(EWRK3_CR);
1646 outb(cr & ~CR_LED, EWRK3_CR);
1647 spin_unlock_irqrestore(&lp->hw_lock, flags);
1648 return signal_pending(current) ? -ERESTARTSYS : 0;
1649}
1650
1651static const struct ethtool_ops ethtool_ops_203 = {
1652 .get_drvinfo = ewrk3_get_drvinfo,
1653 .get_settings = ewrk3_get_settings,
1654 .set_settings = ewrk3_set_settings,
1655 .phys_id = ewrk3_phys_id,
1656};
1657
1658static const struct ethtool_ops ethtool_ops = {
1659 .get_drvinfo = ewrk3_get_drvinfo,
1660 .get_settings = ewrk3_get_settings,
1661 .set_settings = ewrk3_set_settings,
1662 .get_link = ewrk3_get_link,
1663 .phys_id = ewrk3_phys_id,
1664};
1665
1666
1667
1668
1669
1670static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1671{
1672 struct ewrk3_private *lp = netdev_priv(dev);
1673 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_ifru;
1674 u_long iobase = dev->base_addr;
1675 int i, j, status = 0;
1676 u_char csr;
1677 unsigned long flags;
1678 union ewrk3_addr {
1679 u_char addr[HASH_TABLE_LEN * ETH_ALEN];
1680 u_short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1681 };
1682
1683 union ewrk3_addr *tmp;
1684
1685
1686 if (cmd != EWRK3IOCTL)
1687 return -EOPNOTSUPP;
1688
1689 tmp = kmalloc(sizeof(union ewrk3_addr), GFP_KERNEL);
1690 if(tmp==NULL)
1691 return -ENOMEM;
1692
1693 switch (ioc->cmd) {
1694 case EWRK3_GET_HWADDR:
1695 for (i = 0; i < ETH_ALEN; i++) {
1696 tmp->addr[i] = dev->dev_addr[i];
1697 }
1698 ioc->len = ETH_ALEN;
1699 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1700 status = -EFAULT;
1701 break;
1702
1703 case EWRK3_SET_HWADDR:
1704 if (capable(CAP_NET_ADMIN)) {
1705 spin_lock_irqsave(&lp->hw_lock, flags);
1706 csr = inb(EWRK3_CSR);
1707 csr |= (CSR_TXD | CSR_RXD);
1708 outb(csr, EWRK3_CSR);
1709 spin_unlock_irqrestore(&lp->hw_lock, flags);
1710
1711 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN)) {
1712 status = -EFAULT;
1713 break;
1714 }
1715 spin_lock_irqsave(&lp->hw_lock, flags);
1716 for (i = 0; i < ETH_ALEN; i++) {
1717 dev->dev_addr[i] = tmp->addr[i];
1718 outb(tmp->addr[i], EWRK3_PAR0 + i);
1719 }
1720
1721 csr = inb(EWRK3_CSR);
1722 csr &= ~(CSR_TXD | CSR_RXD);
1723 outb(csr, EWRK3_CSR);
1724 spin_unlock_irqrestore(&lp->hw_lock, flags);
1725 } else {
1726 status = -EPERM;
1727 }
1728
1729 break;
1730 case EWRK3_SET_PROM:
1731 if (capable(CAP_NET_ADMIN)) {
1732 spin_lock_irqsave(&lp->hw_lock, flags);
1733 csr = inb(EWRK3_CSR);
1734 csr |= CSR_PME;
1735 csr &= ~CSR_MCE;
1736 outb(csr, EWRK3_CSR);
1737 spin_unlock_irqrestore(&lp->hw_lock, flags);
1738 } else {
1739 status = -EPERM;
1740 }
1741
1742 break;
1743 case EWRK3_CLR_PROM:
1744 if (capable(CAP_NET_ADMIN)) {
1745 spin_lock_irqsave(&lp->hw_lock, flags);
1746 csr = inb(EWRK3_CSR);
1747 csr &= ~CSR_PME;
1748 outb(csr, EWRK3_CSR);
1749 spin_unlock_irqrestore(&lp->hw_lock, flags);
1750 } else {
1751 status = -EPERM;
1752 }
1753
1754 break;
1755 case EWRK3_GET_MCA:
1756 spin_lock_irqsave(&lp->hw_lock, flags);
1757 if (lp->shmem_length == IO_ONLY) {
1758 outb(0, EWRK3_IOPR);
1759 outw(PAGE0_HTE, EWRK3_PIR1);
1760 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1761 tmp->addr[i] = inb(EWRK3_DATA);
1762 }
1763 } else {
1764 outb(0, EWRK3_MPR);
1765 memcpy_fromio(tmp->addr, lp->shmem + PAGE0_HTE, (HASH_TABLE_LEN >> 3));
1766 }
1767 spin_unlock_irqrestore(&lp->hw_lock, flags);
1768
1769 ioc->len = (HASH_TABLE_LEN >> 3);
1770 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1771 status = -EFAULT;
1772
1773 break;
1774 case EWRK3_SET_MCA:
1775 if (capable(CAP_NET_ADMIN)) {
1776 if (ioc->len > 1024)
1777 {
1778 status = -EINVAL;
1779 break;
1780 }
1781 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN * ioc->len)) {
1782 status = -EFAULT;
1783 break;
1784 }
1785 set_multicast_list(dev);
1786 } else {
1787 status = -EPERM;
1788 }
1789
1790 break;
1791 case EWRK3_CLR_MCA:
1792 if (capable(CAP_NET_ADMIN)) {
1793 set_multicast_list(dev);
1794 } else {
1795 status = -EPERM;
1796 }
1797
1798 break;
1799 case EWRK3_MCA_EN:
1800 if (capable(CAP_NET_ADMIN)) {
1801 spin_lock_irqsave(&lp->hw_lock, flags);
1802 csr = inb(EWRK3_CSR);
1803 csr |= CSR_MCE;
1804 csr &= ~CSR_PME;
1805 outb(csr, EWRK3_CSR);
1806 spin_unlock_irqrestore(&lp->hw_lock, flags);
1807 } else {
1808 status = -EPERM;
1809 }
1810
1811 break;
1812 case EWRK3_GET_STATS: {
1813 struct ewrk3_stats *tmp_stats =
1814 kmalloc(sizeof(lp->pktStats), GFP_KERNEL);
1815 if (!tmp_stats) {
1816 status = -ENOMEM;
1817 break;
1818 }
1819
1820 spin_lock_irqsave(&lp->hw_lock, flags);
1821 memcpy(tmp_stats, &lp->pktStats, sizeof(lp->pktStats));
1822 spin_unlock_irqrestore(&lp->hw_lock, flags);
1823
1824 ioc->len = sizeof(lp->pktStats);
1825 if (copy_to_user(ioc->data, tmp_stats, sizeof(lp->pktStats)))
1826 status = -EFAULT;
1827 kfree(tmp_stats);
1828 break;
1829 }
1830 case EWRK3_CLR_STATS:
1831 if (capable(CAP_NET_ADMIN)) {
1832 spin_lock_irqsave(&lp->hw_lock, flags);
1833 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1834 spin_unlock_irqrestore(&lp->hw_lock,flags);
1835 } else {
1836 status = -EPERM;
1837 }
1838
1839 break;
1840 case EWRK3_GET_CSR:
1841 tmp->addr[0] = inb(EWRK3_CSR);
1842 ioc->len = 1;
1843 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1844 status = -EFAULT;
1845 break;
1846 case EWRK3_SET_CSR:
1847 if (capable(CAP_NET_ADMIN)) {
1848 if (copy_from_user(tmp->addr, ioc->data, 1)) {
1849 status = -EFAULT;
1850 break;
1851 }
1852 outb(tmp->addr[0], EWRK3_CSR);
1853 } else {
1854 status = -EPERM;
1855 }
1856
1857 break;
1858 case EWRK3_GET_EEPROM:
1859 if (capable(CAP_NET_ADMIN)) {
1860 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
1861 tmp->val[i] = (short) Read_EEPROM(iobase, i);
1862 }
1863 i = EEPROM_MAX;
1864 tmp->addr[i++] = inb(EWRK3_CMR);
1865 for (j = 0; j < ETH_ALEN; j++) {
1866 tmp->addr[i++] = inb(EWRK3_PAR0 + j);
1867 }
1868 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1869 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1870 status = -EFAULT;
1871 } else {
1872 status = -EPERM;
1873 }
1874
1875 break;
1876 case EWRK3_SET_EEPROM:
1877 if (capable(CAP_NET_ADMIN)) {
1878 if (copy_from_user(tmp->addr, ioc->data, EEPROM_MAX)) {
1879 status = -EFAULT;
1880 break;
1881 }
1882 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
1883 Write_EEPROM(tmp->val[i], iobase, i);
1884 }
1885 } else {
1886 status = -EPERM;
1887 }
1888
1889 break;
1890 case EWRK3_GET_CMR:
1891 tmp->addr[0] = inb(EWRK3_CMR);
1892 ioc->len = 1;
1893 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1894 status = -EFAULT;
1895 break;
1896 case EWRK3_SET_TX_CUT_THRU:
1897 if (capable(CAP_NET_ADMIN)) {
1898 lp->txc = 1;
1899 } else {
1900 status = -EPERM;
1901 }
1902
1903 break;
1904 case EWRK3_CLR_TX_CUT_THRU:
1905 if (capable(CAP_NET_ADMIN)) {
1906 lp->txc = 0;
1907 } else {
1908 status = -EPERM;
1909 }
1910
1911 break;
1912 default:
1913 status = -EOPNOTSUPP;
1914 }
1915 kfree(tmp);
1916 return status;
1917}
1918
1919#ifdef MODULE
1920static struct net_device *ewrk3_devs[MAX_NUM_EWRK3S];
1921static int ndevs;
1922static int io[MAX_NUM_EWRK3S+1] = { 0x300, 0, };
1923
1924
1925module_param_array(io, int, NULL, 0);
1926module_param_array(irq, int, NULL, 0);
1927MODULE_PARM_DESC(io, "EtherWORKS 3 I/O base address(es)");
1928MODULE_PARM_DESC(irq, "EtherWORKS 3 IRQ number(s)");
1929
1930static __exit void ewrk3_exit_module(void)
1931{
1932 int i;
1933
1934 for( i=0; i<ndevs; i++ ) {
1935 struct net_device *dev = ewrk3_devs[i];
1936 struct ewrk3_private *lp = netdev_priv(dev);
1937 ewrk3_devs[i] = NULL;
1938 unregister_netdev(dev);
1939 release_region(dev->base_addr, EWRK3_TOTAL_SIZE);
1940 iounmap(lp->shmem);
1941 free_netdev(dev);
1942 }
1943}
1944
1945static __init int ewrk3_init_module(void)
1946{
1947 int i=0;
1948
1949 while( io[i] && irq[i] ) {
1950 struct net_device *dev
1951 = alloc_etherdev(sizeof(struct ewrk3_private));
1952
1953 if (!dev)
1954 break;
1955
1956 if (ewrk3_probe1(dev, io[i], irq[i]) != 0) {
1957 free_netdev(dev);
1958 break;
1959 }
1960
1961 ewrk3_devs[ndevs++] = dev;
1962 i++;
1963 }
1964
1965 return ndevs ? 0 : -EIO;
1966}
1967
1968
1969
1970module_exit(ewrk3_exit_module);
1971module_init(ewrk3_init_module);
1972#endif
1973MODULE_LICENSE("GPL");
1974
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