linux/drivers/ide/pci/trm290.c
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   1/*
   2 *  linux/drivers/ide/pci/trm290.c              Version 1.05    Dec. 26, 2007
   3 *
   4 *  Copyright (c) 1997-1998  Mark Lord
   5 *  Copyright (c) 2007       MontaVista Software, Inc. <source@mvista.com>
   6 *  May be copied or modified under the terms of the GNU General Public License
   7 *
   8 *  June 22, 2004 - get rid of check_region
   9 *                   - Jesper Juhl
  10 *
  11 */
  12
  13/*
  14 * This module provides support for the bus-master IDE DMA function
  15 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
  16 * including a "Precision Instruments" board.  The TRM290 pre-dates
  17 * the sff-8038 standard (ide-dma.c) by a few months, and differs
  18 * significantly enough to warrant separate routines for some functions,
  19 * while re-using others from ide-dma.c.
  20 *
  21 * EXPERIMENTAL!  It works for me (a sample of one).
  22 *
  23 * Works reliably for me in DMA mode (READs only),
  24 * DMA WRITEs are disabled by default (see #define below);
  25 *
  26 * DMA is not enabled automatically for this chipset,
  27 * but can be turned on manually (with "hdparm -d1") at run time.
  28 *
  29 * I need volunteers with "spare" drives for further testing
  30 * and development, and maybe to help figure out the peculiarities.
  31 * Even knowing the registers (below), some things behave strangely.
  32 */
  33
  34#define TRM290_NO_DMA_WRITES    /* DMA writes seem unreliable sometimes */
  35
  36/*
  37 * TRM-290 PCI-IDE2 Bus Master Chip
  38 * ================================
  39 * The configuration registers are addressed in normal I/O port space
  40 * and are used as follows:
  41 *
  42 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
  43 *
  44 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
  45 *      bit7 must always be written as "1"
  46 *      bits6-2 undefined
  47 *      bit1 1=legacy_compatible_mode, 0=native_pci_mode
  48 *      bit0 1=test_mode, 0=normal(default)
  49 *
  50 * trm290_base+2 when READ: status register (byte, read-only)
  51 *      bits7-2 undefined
  52 *      bit1 channel0 busmaster interrupt status 0=none, 1=asserted
  53 *      bit0 channel0 interrupt status 0=none, 1=asserted
  54 *
  55 * trm290_base+3 Interrupt mask register
  56 *      bits7-5 undefined
  57 *      bit4 legacy_header: 1=present, 0=absent
  58 *      bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
  59 *      bit2 channel1 interrupt status 0=none, 1=asserted (read only)
  60 *      bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
  61 *      bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
  62 *
  63 * trm290_base+1 "CPR" Config Pointer Register (byte)
  64 *      bit7 1=autoincrement CPR bits 2-0 after each access of CDR
  65 *      bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
  66 *      bit5 0=enabled master burst access (default), 1=disable  (write only)
  67 *      bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
  68 *      bit3 0=primary IDE channel, 1=secondary IDE channel
  69 *      bits2-0 register index for accesses through CDR port
  70 *
  71 * trm290_base+0 "CDR" Config Data Register (word)
  72 *      two sets of seven config registers,
  73 *      selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
  74 *      each index defined below:
  75 *
  76 * Index-0 Base address register for command block (word)
  77 *      defaults: 0x1f0 for primary, 0x170 for secondary
  78 *
  79 * Index-1 general config register (byte)
  80 *      bit7 1=DMA enable, 0=DMA disable
  81 *      bit6 1=activate IDE_RESET, 0=no action (default)
  82 *      bit5 1=enable IORDY, 0=disable IORDY (default)
  83 *      bit4 0=16-bit data port(default), 1=8-bit (XT) data port
  84 *      bit3 interrupt polarity: 1=active_low, 0=active_high(default)
  85 *      bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
  86 *      bit1 bus_master_mode(?): 1=enable, 0=disable(default)
  87 *      bit0 enable_io_ports: 1=enable(default), 0=disable
  88 *
  89 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
  90 *      bits7-0 bits7-0 of readahead count
  91 *
  92 * Index-3 read-ahead config register (byte, write only)
  93 *      bit7 1=enable_readahead, 0=disable_readahead(default)
  94 *      bit6 1=clear_FIFO, 0=no_action
  95 *      bit5 undefined
  96 *      bit4 mode4 timing control: 1=enable, 0=disable(default)
  97 *      bit3 undefined
  98 *      bit2 undefined
  99 *      bits1-0 bits9-8 of read-ahead count
 100 *
 101 * Index-4 base address register for control block (word)
 102 *      defaults: 0x3f6 for primary, 0x376 for secondary
 103 *
 104 * Index-5 data port timings (shared by both drives) (byte)
 105 *      standard PCI "clk" (clock) counts, default value = 0xf5
 106 *
 107 *      bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
 108 *      bits5-3 hold time:      000=1clk, 001=2clk, 010=3clk,
 109 *                              011=4clk, 100=5clk, 101=6clk,
 110 *                              110=8clk, 111=12clk
 111 *      bits2-0 active time:    000=2clk, 001=3clk, 010=4clk,
 112 *                              011=5clk, 100=6clk, 101=8clk,
 113 *                              110=12clk, 111=16clk
 114 *
 115 * Index-6 command/control port timings (shared by both drives) (byte)
 116 *      same layout as Index-5, default value = 0xde
 117 *
 118 * Suggested CDR programming for PIO mode0 (600ns):
 119 *      0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde  ; primary
 120 *      0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde  ; secondary
 121 *
 122 * Suggested CDR programming for PIO mode3 (180ns):
 123 *      0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde  ; primary
 124 *      0x0170,0x21,0xff,0x80,0x0376,0x09,0xde  ; secondary
 125 *
 126 * Suggested CDR programming for PIO mode4 (120ns):
 127 *      0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde  ; primary
 128 *      0x0170,0x21,0xff,0x80,0x0376,0x00,0xde  ; secondary
 129 *
 130 */
 131
 132#include <linux/types.h>
 133#include <linux/module.h>
 134#include <linux/kernel.h>
 135#include <linux/mm.h>
 136#include <linux/ioport.h>
 137#include <linux/interrupt.h>
 138#include <linux/blkdev.h>
 139#include <linux/init.h>
 140#include <linux/hdreg.h>
 141#include <linux/pci.h>
 142#include <linux/delay.h>
 143#include <linux/ide.h>
 144
 145#include <asm/io.h>
 146
 147static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
 148{
 149        ide_hwif_t *hwif = HWIF(drive);
 150        u16 reg = 0;
 151        unsigned long flags;
 152
 153        /* select PIO or DMA */
 154        reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
 155
 156        local_irq_save(flags);
 157
 158        if (reg != hwif->select_data) {
 159                hwif->select_data = reg;
 160                /* set PIO/DMA */
 161                outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
 162                outw(reg & 0xff, hwif->config_data);
 163        }
 164
 165        /* enable IRQ if not probing */
 166        if (drive->present) {
 167                reg = inw(hwif->config_data + 3);
 168                reg &= 0x13;
 169                reg &= ~(1 << hwif->channel);
 170                outw(reg, hwif->config_data + 3);
 171        }
 172
 173        local_irq_restore(flags);
 174}
 175
 176static void trm290_selectproc (ide_drive_t *drive)
 177{
 178        trm290_prepare_drive(drive, drive->using_dma);
 179}
 180
 181static void trm290_dma_exec_cmd(ide_drive_t *drive, u8 command)
 182{
 183        BUG_ON(HWGROUP(drive)->handler != NULL);        /* paranoia check */
 184        ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
 185        /* issue cmd to drive */
 186        outb(command, IDE_COMMAND_REG);
 187}
 188
 189static int trm290_dma_setup(ide_drive_t *drive)
 190{
 191        ide_hwif_t *hwif = drive->hwif;
 192        struct request *rq = hwif->hwgroup->rq;
 193        unsigned int count, rw;
 194
 195        if (rq_data_dir(rq)) {
 196#ifdef TRM290_NO_DMA_WRITES
 197                /* always use PIO for writes */
 198                trm290_prepare_drive(drive, 0); /* select PIO xfer */
 199                return 1;
 200#endif
 201                rw = 1;
 202        } else
 203                rw = 2;
 204
 205        if (!(count = ide_build_dmatable(drive, rq))) {
 206                /* try PIO instead of DMA */
 207                trm290_prepare_drive(drive, 0); /* select PIO xfer */
 208                return 1;
 209        }
 210        /* select DMA xfer */
 211        trm290_prepare_drive(drive, 1);
 212        outl(hwif->dmatable_dma | rw, hwif->dma_command);
 213        drive->waiting_for_dma = 1;
 214        /* start DMA */
 215        outw((count * 2) - 1, hwif->dma_status);
 216        return 0;
 217}
 218
 219static void trm290_dma_start(ide_drive_t *drive)
 220{
 221}
 222
 223static int trm290_ide_dma_end (ide_drive_t *drive)
 224{
 225        ide_hwif_t *hwif = HWIF(drive);
 226        u16 status = 0;
 227
 228        drive->waiting_for_dma = 0;
 229        /* purge DMA mappings */
 230        ide_destroy_dmatable(drive);
 231        status = inw(hwif->dma_status);
 232        return (status != 0x00ff);
 233}
 234
 235static int trm290_ide_dma_test_irq (ide_drive_t *drive)
 236{
 237        ide_hwif_t *hwif = HWIF(drive);
 238        u16 status = 0;
 239
 240        status = inw(hwif->dma_status);
 241        return (status == 0x00ff);
 242}
 243
 244static void trm290_dma_host_on(ide_drive_t *drive)
 245{
 246}
 247
 248static void trm290_dma_host_off(ide_drive_t *drive)
 249{
 250}
 251
 252static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
 253{
 254        unsigned int cfgbase = 0;
 255        unsigned long flags;
 256        u8 reg = 0;
 257        struct pci_dev *dev = hwif->pci_dev;
 258
 259        cfgbase = pci_resource_start(dev, 4);
 260        if ((dev->class & 5) && cfgbase) {
 261                hwif->config_data = cfgbase;
 262                printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
 263                        hwif->config_data);
 264        } else {
 265                hwif->config_data = 0x3df0;
 266                printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
 267                        hwif->config_data);
 268        }
 269
 270        local_irq_save(flags);
 271        /* put config reg into first byte of hwif->select_data */
 272        outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
 273        /* select PIO as default */
 274        hwif->select_data = 0x21;
 275        outb(hwif->select_data, hwif->config_data);
 276        /* get IRQ info */
 277        reg = inb(hwif->config_data + 3);
 278        /* mask IRQs for both ports */
 279        reg = (reg & 0x10) | 0x03;
 280        outb(reg, hwif->config_data + 3);
 281        local_irq_restore(flags);
 282
 283        if ((reg & 0x10))
 284                /* legacy mode */
 285                hwif->irq = hwif->channel ? 15 : 14;
 286        else if (!hwif->irq && hwif->mate && hwif->mate->irq)
 287                /* sharing IRQ with mate */
 288                hwif->irq = hwif->mate->irq;
 289
 290        ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
 291
 292        hwif->dma_host_off      = &trm290_dma_host_off;
 293        hwif->dma_host_on       = &trm290_dma_host_on;
 294        hwif->dma_setup         = &trm290_dma_setup;
 295        hwif->dma_exec_cmd      = &trm290_dma_exec_cmd;
 296        hwif->dma_start         = &trm290_dma_start;
 297        hwif->ide_dma_end       = &trm290_ide_dma_end;
 298        hwif->ide_dma_test_irq  = &trm290_ide_dma_test_irq;
 299
 300        hwif->selectproc = &trm290_selectproc;
 301#if 1
 302        {
 303        /*
 304         * My trm290-based card doesn't seem to work with all possible values
 305         * for the control basereg, so this kludge ensures that we use only
 306         * values that are known to work.  Ugh.         -ml
 307         */
 308                u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
 309                static u16 next_offset = 0;
 310                u8 old_mask;
 311
 312                outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
 313                old = inw(hwif->config_data);
 314                old &= ~1;
 315                old_mask = inb(old + 2);
 316                if (old != compat && old_mask == 0xff) {
 317                        /* leave lower 10 bits untouched */
 318                        compat += (next_offset += 0x400);
 319                        hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
 320                        outw(compat | 1, hwif->config_data);
 321                        new = inw(hwif->config_data);
 322                        printk(KERN_INFO "%s: control basereg workaround: "
 323                                "old=0x%04x, new=0x%04x\n",
 324                                hwif->name, old, new & ~1);
 325                }
 326        }
 327#endif
 328}
 329
 330static const struct ide_port_info trm290_chipset __devinitdata = {
 331        .name           = "TRM290",
 332        .init_hwif      = init_hwif_trm290,
 333        .chipset        = ide_trm290,
 334        .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
 335#if 0 /* play it safe for now */
 336                          IDE_HFLAG_TRUST_BIOS_FOR_DMA |
 337#endif
 338                          IDE_HFLAG_NO_AUTODMA |
 339                          IDE_HFLAG_BOOTABLE |
 340                          IDE_HFLAG_NO_LBA48,
 341};
 342
 343static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 344{
 345        return ide_setup_pci_device(dev, &trm290_chipset);
 346}
 347
 348static const struct pci_device_id trm290_pci_tbl[] = {
 349        { PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
 350        { 0, },
 351};
 352MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
 353
 354static struct pci_driver driver = {
 355        .name           = "TRM290_IDE",
 356        .id_table       = trm290_pci_tbl,
 357        .probe          = trm290_init_one,
 358};
 359
 360static int __init trm290_ide_init(void)
 361{
 362        return ide_pci_register_driver(&driver);
 363}
 364
 365module_init(trm290_ide_init);
 366
 367MODULE_AUTHOR("Mark Lord");
 368MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
 369MODULE_LICENSE("GPL");
 370
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