linux/drivers/ide/pci/sl82c105.c
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   1/*
   2 * linux/drivers/ide/pci/sl82c105.c
   3 *
   4 * SL82C105/Winbond 553 IDE driver
   5 *
   6 * Maintainer unknown.
   7 *
   8 * Drive tuning added from Rebel.com's kernel sources
   9 *  -- Russell King (15/11/98) linux@arm.linux.org.uk
  10 * 
  11 * Merge in Russell's HW workarounds, fix various problems
  12 * with the timing registers setup.
  13 *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
  14 *
  15 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
  16 */
  17
  18#include <linux/types.h>
  19#include <linux/module.h>
  20#include <linux/kernel.h>
  21#include <linux/timer.h>
  22#include <linux/mm.h>
  23#include <linux/ioport.h>
  24#include <linux/interrupt.h>
  25#include <linux/blkdev.h>
  26#include <linux/hdreg.h>
  27#include <linux/pci.h>
  28#include <linux/ide.h>
  29
  30#include <asm/io.h>
  31#include <asm/dma.h>
  32
  33#undef DEBUG
  34
  35#ifdef DEBUG
  36#define DBG(arg) printk arg
  37#else
  38#define DBG(fmt,...)
  39#endif
  40/*
  41 * SL82C105 PCI config register 0x40 bits.
  42 */
  43#define CTRL_IDE_IRQB   (1 << 30)
  44#define CTRL_IDE_IRQA   (1 << 28)
  45#define CTRL_LEGIRQ     (1 << 11)
  46#define CTRL_P1F16      (1 << 5)
  47#define CTRL_P1EN       (1 << 4)
  48#define CTRL_P0F16      (1 << 1)
  49#define CTRL_P0EN       (1 << 0)
  50
  51/*
  52 * Convert a PIO mode and cycle time to the required on/off times
  53 * for the interface.  This has protection against runaway timings.
  54 */
  55static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
  56{
  57        unsigned int cmd_on, cmd_off;
  58        u8 iordy = 0;
  59
  60        cmd_on  = (ide_pio_timings[pio].active_time + 29) / 30;
  61        cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
  62
  63        if (cmd_on == 0)
  64                cmd_on = 1;
  65
  66        if (cmd_off == 0)
  67                cmd_off = 1;
  68
  69        if (pio > 2 || ide_dev_has_iordy(drive->id))
  70                iordy = 0x40;
  71
  72        return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
  73}
  74
  75/*
  76 * Configure the chipset for PIO mode.
  77 */
  78static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
  79{
  80        struct pci_dev *dev     = HWIF(drive)->pci_dev;
  81        int reg                 = 0x44 + drive->dn * 4;
  82        u16 drv_ctrl;
  83
  84        drv_ctrl = get_pio_timings(drive, pio);
  85
  86        /*
  87         * Store the PIO timings so that we can restore them
  88         * in case DMA will be turned off...
  89         */
  90        drive->drive_data &= 0xffff0000;
  91        drive->drive_data |= drv_ctrl;
  92
  93        if (!drive->using_dma) {
  94                /*
  95                 * If we are actually using MW DMA, then we can not
  96                 * reprogram the interface drive control register.
  97                 */
  98                pci_write_config_word(dev, reg,  drv_ctrl);
  99                pci_read_config_word (dev, reg, &drv_ctrl);
 100        }
 101
 102        printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
 103                          ide_xfer_verbose(pio + XFER_PIO_0),
 104                          ide_pio_cycle_time(drive, pio), drv_ctrl);
 105}
 106
 107/*
 108 * Configure the chipset for DMA mode.
 109 */
 110static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
 111{
 112        static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
 113        u16 drv_ctrl;
 114
 115        DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
 116             drive->name, ide_xfer_verbose(speed)));
 117
 118        switch (speed) {
 119        case XFER_MW_DMA_2:
 120        case XFER_MW_DMA_1:
 121        case XFER_MW_DMA_0:
 122                drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
 123
 124                /*
 125                 * Store the DMA timings so that we can actually program
 126                 * them when DMA will be turned on...
 127                 */
 128                drive->drive_data &= 0x0000ffff;
 129                drive->drive_data |= (unsigned long)drv_ctrl << 16;
 130
 131                /*
 132                 * If we are already using DMA, we just reprogram
 133                 * the drive control register.
 134                 */
 135                if (drive->using_dma) {
 136                        struct pci_dev *dev     = HWIF(drive)->pci_dev;
 137                        int reg                 = 0x44 + drive->dn * 4;
 138
 139                        pci_write_config_word(dev, reg, drv_ctrl);
 140                }
 141                break;
 142        default:
 143                return;
 144        }
 145}
 146
 147/*
 148 * The SL82C105 holds off all IDE interrupts while in DMA mode until
 149 * all DMA activity is completed.  Sometimes this causes problems (eg,
 150 * when the drive wants to report an error condition).
 151 *
 152 * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
 153 * state machine.  We need to kick this to work around various bugs.
 154 */
 155static inline void sl82c105_reset_host(struct pci_dev *dev)
 156{
 157        u16 val;
 158
 159        pci_read_config_word(dev, 0x7e, &val);
 160        pci_write_config_word(dev, 0x7e, val | (1 << 2));
 161        pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
 162}
 163
 164/*
 165 * If we get an IRQ timeout, it might be that the DMA state machine
 166 * got confused.  Fix from Todd Inglett.  Details from Winbond.
 167 *
 168 * This function is called when the IDE timer expires, the drive
 169 * indicates that it is READY, and we were waiting for DMA to complete.
 170 */
 171static void sl82c105_dma_lost_irq(ide_drive_t *drive)
 172{
 173        ide_hwif_t *hwif        = HWIF(drive);
 174        struct pci_dev *dev     = hwif->pci_dev;
 175        u32 val, mask           = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
 176        u8 dma_cmd;
 177
 178        printk("sl82c105: lost IRQ, resetting host\n");
 179
 180        /*
 181         * Check the raw interrupt from the drive.
 182         */
 183        pci_read_config_dword(dev, 0x40, &val);
 184        if (val & mask)
 185                printk("sl82c105: drive was requesting IRQ, but host lost it\n");
 186
 187        /*
 188         * Was DMA enabled?  If so, disable it - we're resetting the
 189         * host.  The IDE layer will be handling the drive for us.
 190         */
 191        dma_cmd = inb(hwif->dma_command);
 192        if (dma_cmd & 1) {
 193                outb(dma_cmd & ~1, hwif->dma_command);
 194                printk("sl82c105: DMA was enabled\n");
 195        }
 196
 197        sl82c105_reset_host(dev);
 198}
 199
 200/*
 201 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
 202 * Winbond recommend that the DMA state machine is reset prior to
 203 * setting the bus master DMA enable bit.
 204 *
 205 * The generic IDE core will have disabled the BMEN bit before this
 206 * function is called.
 207 */
 208static void sl82c105_dma_start(ide_drive_t *drive)
 209{
 210        ide_hwif_t *hwif        = HWIF(drive);
 211        struct pci_dev *dev     = hwif->pci_dev;
 212
 213        sl82c105_reset_host(dev);
 214        ide_dma_start(drive);
 215}
 216
 217static void sl82c105_dma_timeout(ide_drive_t *drive)
 218{
 219        DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
 220
 221        sl82c105_reset_host(HWIF(drive)->pci_dev);
 222        ide_dma_timeout(drive);
 223}
 224
 225static int sl82c105_ide_dma_on(ide_drive_t *drive)
 226{
 227        struct pci_dev *dev     = HWIF(drive)->pci_dev;
 228        int rc, reg             = 0x44 + drive->dn * 4;
 229
 230        DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
 231
 232        rc = __ide_dma_on(drive);
 233        if (rc == 0) {
 234                pci_write_config_word(dev, reg, drive->drive_data >> 16);
 235
 236                printk(KERN_INFO "%s: DMA enabled\n", drive->name);
 237        }
 238        return rc;
 239}
 240
 241static void sl82c105_dma_off_quietly(ide_drive_t *drive)
 242{
 243        struct pci_dev *dev     = HWIF(drive)->pci_dev;
 244        int reg                 = 0x44 + drive->dn * 4;
 245
 246        DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
 247
 248        pci_write_config_word(dev, reg, drive->drive_data);
 249
 250        ide_dma_off_quietly(drive);
 251}
 252
 253/*
 254 * Ok, that is nasty, but we must make sure the DMA timings
 255 * won't be used for a PIO access. The solution here is
 256 * to make sure the 16 bits mode is diabled on the channel
 257 * when DMA is enabled, thus causing the chip to use PIO0
 258 * timings for those operations.
 259 */
 260static void sl82c105_selectproc(ide_drive_t *drive)
 261{
 262        ide_hwif_t *hwif        = HWIF(drive);
 263        struct pci_dev *dev     = hwif->pci_dev;
 264        u32 val, old, mask;
 265
 266        //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
 267
 268        mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
 269        old = val = (u32)pci_get_drvdata(dev);
 270        if (drive->using_dma)
 271                val &= ~mask;
 272        else
 273                val |= mask;
 274        if (old != val) {
 275                pci_write_config_dword(dev, 0x40, val); 
 276                pci_set_drvdata(dev, (void *)val);
 277        }
 278}
 279
 280/*
 281 * ATA reset will clear the 16 bits mode in the control
 282 * register, we need to update our cache
 283 */
 284static void sl82c105_resetproc(ide_drive_t *drive)
 285{
 286        struct pci_dev *dev = HWIF(drive)->pci_dev;
 287        u32 val;
 288
 289        DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
 290
 291        pci_read_config_dword(dev, 0x40, &val);
 292        pci_set_drvdata(dev, (void *)val);
 293}
 294
 295/*
 296 * Return the revision of the Winbond bridge
 297 * which this function is part of.
 298 */
 299static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
 300{
 301        struct pci_dev *bridge;
 302
 303        /*
 304         * The bridge should be part of the same device, but function 0.
 305         */
 306        bridge = pci_get_bus_and_slot(dev->bus->number,
 307                               PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
 308        if (!bridge)
 309                return -1;
 310
 311        /*
 312         * Make sure it is a Winbond 553 and is an ISA bridge.
 313         */
 314        if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
 315            bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
 316            bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
 317                pci_dev_put(bridge);
 318                return -1;
 319        }
 320        /*
 321         * We need to find function 0's revision, not function 1
 322         */
 323        pci_dev_put(bridge);
 324
 325        return bridge->revision;
 326}
 327
 328/*
 329 * Enable the PCI device
 330 * 
 331 * --BenH: It's arch fixup code that should enable channels that
 332 * have not been enabled by firmware. I decided we can still enable
 333 * channel 0 here at least, but channel 1 has to be enabled by
 334 * firmware or arch code. We still set both to 16 bits mode.
 335 */
 336static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
 337{
 338        u32 val;
 339
 340        DBG(("init_chipset_sl82c105()\n"));
 341
 342        pci_read_config_dword(dev, 0x40, &val);
 343        val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
 344        pci_write_config_dword(dev, 0x40, val);
 345        pci_set_drvdata(dev, (void *)val);
 346
 347        return dev->irq;
 348}
 349
 350/*
 351 * Initialise IDE channel
 352 */
 353static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
 354{
 355        unsigned int rev;
 356
 357        DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
 358
 359        hwif->set_pio_mode      = &sl82c105_set_pio_mode;
 360        hwif->set_dma_mode      = &sl82c105_set_dma_mode;
 361        hwif->selectproc        = &sl82c105_selectproc;
 362        hwif->resetproc         = &sl82c105_resetproc;
 363
 364        if (!hwif->dma_base)
 365                return;
 366
 367        rev = sl82c105_bridge_revision(hwif->pci_dev);
 368        if (rev <= 5) {
 369                /*
 370                 * Never ever EVER under any circumstances enable
 371                 * DMA when the bridge is this old.
 372                 */
 373                printk("    %s: Winbond W83C553 bridge revision %d, "
 374                       "BM-DMA disabled\n", hwif->name, rev);
 375                return;
 376        }
 377
 378        hwif->mwdma_mask = ATA_MWDMA2;
 379
 380        hwif->ide_dma_on                = &sl82c105_ide_dma_on;
 381        hwif->dma_off_quietly           = &sl82c105_dma_off_quietly;
 382        hwif->dma_lost_irq              = &sl82c105_dma_lost_irq;
 383        hwif->dma_start                 = &sl82c105_dma_start;
 384        hwif->dma_timeout               = &sl82c105_dma_timeout;
 385
 386        if (hwif->mate)
 387                hwif->serialized = hwif->mate->serialized = 1;
 388}
 389
 390static const struct ide_port_info sl82c105_chipset __devinitdata = {
 391        .name           = "W82C105",
 392        .init_chipset   = init_chipset_sl82c105,
 393        .init_hwif      = init_hwif_sl82c105,
 394        .enablebits     = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
 395        .host_flags     = IDE_HFLAG_IO_32BIT |
 396                          IDE_HFLAG_UNMASK_IRQS |
 397                          IDE_HFLAG_NO_AUTODMA |
 398                          IDE_HFLAG_BOOTABLE,
 399        .pio_mask       = ATA_PIO5,
 400};
 401
 402static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 403{
 404        return ide_setup_pci_device(dev, &sl82c105_chipset);
 405}
 406
 407static const struct pci_device_id sl82c105_pci_tbl[] = {
 408        { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
 409        { 0, },
 410};
 411MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
 412
 413static struct pci_driver driver = {
 414        .name           = "W82C105_IDE",
 415        .id_table       = sl82c105_pci_tbl,
 416        .probe          = sl82c105_init_one,
 417};
 418
 419static int __init sl82c105_ide_init(void)
 420{
 421        return ide_pci_register_driver(&driver);
 422}
 423
 424module_init(sl82c105_ide_init);
 425
 426MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
 427MODULE_LICENSE("GPL");
 428
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