linux/drivers/ide/pci/sgiioc4.c
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   1/*
   2 * Copyright (c) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms of version 2 of the GNU General Public License
   6 * as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it would be useful, but
   9 * WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  11 *
  12 * You should have received a copy of the GNU General Public
  13 * License along with this program; if not, write the Free Software
  14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  15 *
  16 * For further information regarding this notice, see:
  17 *
  18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
  19 */
  20
  21#include <linux/module.h>
  22#include <linux/types.h>
  23#include <linux/pci.h>
  24#include <linux/delay.h>
  25#include <linux/hdreg.h>
  26#include <linux/init.h>
  27#include <linux/kernel.h>
  28#include <linux/timer.h>
  29#include <linux/mm.h>
  30#include <linux/ioport.h>
  31#include <linux/blkdev.h>
  32#include <linux/scatterlist.h>
  33#include <linux/ioc4.h>
  34#include <asm/io.h>
  35
  36#include <linux/ide.h>
  37
  38#define DRV_NAME "SGIIOC4"
  39
  40/* IOC4 Specific Definitions */
  41#define IOC4_CMD_OFFSET         0x100
  42#define IOC4_CTRL_OFFSET        0x120
  43#define IOC4_DMA_OFFSET         0x140
  44#define IOC4_INTR_OFFSET        0x0
  45
  46#define IOC4_TIMING             0x00
  47#define IOC4_DMA_PTR_L          0x01
  48#define IOC4_DMA_PTR_H          0x02
  49#define IOC4_DMA_ADDR_L         0x03
  50#define IOC4_DMA_ADDR_H         0x04
  51#define IOC4_BC_DEV             0x05
  52#define IOC4_BC_MEM             0x06
  53#define IOC4_DMA_CTRL           0x07
  54#define IOC4_DMA_END_ADDR       0x08
  55
  56/* Bits in the IOC4 Control/Status Register */
  57#define IOC4_S_DMA_START        0x01
  58#define IOC4_S_DMA_STOP         0x02
  59#define IOC4_S_DMA_DIR          0x04
  60#define IOC4_S_DMA_ACTIVE       0x08
  61#define IOC4_S_DMA_ERROR        0x10
  62#define IOC4_ATA_MEMERR         0x02
  63
  64/* Read/Write Directions */
  65#define IOC4_DMA_WRITE          0x04
  66#define IOC4_DMA_READ           0x00
  67
  68/* Interrupt Register Offsets */
  69#define IOC4_INTR_REG           0x03
  70#define IOC4_INTR_SET           0x05
  71#define IOC4_INTR_CLEAR         0x07
  72
  73#define IOC4_IDE_CACHELINE_SIZE 128
  74#define IOC4_CMD_CTL_BLK_SIZE   0x20
  75#define IOC4_SUPPORTED_FIRMWARE_REV 46
  76
  77typedef struct {
  78        u32 timing_reg0;
  79        u32 timing_reg1;
  80        u32 low_mem_ptr;
  81        u32 high_mem_ptr;
  82        u32 low_mem_addr;
  83        u32 high_mem_addr;
  84        u32 dev_byte_count;
  85        u32 mem_byte_count;
  86        u32 status;
  87} ioc4_dma_regs_t;
  88
  89/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
  90/* IOC4 has only 1 IDE channel */
  91#define IOC4_PRD_BYTES       16
  92#define IOC4_PRD_ENTRIES     (PAGE_SIZE /(4*IOC4_PRD_BYTES))
  93
  94
  95static void
  96sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
  97                        unsigned long ctrl_port, unsigned long irq_port)
  98{
  99        unsigned long reg = data_port;
 100        int i;
 101
 102        /* Registers are word (32 bit) aligned */
 103        for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
 104                hw->io_ports[i] = reg + i * 4;
 105
 106        if (ctrl_port)
 107                hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 108
 109        if (irq_port)
 110                hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
 111}
 112
 113static void
 114sgiioc4_maskproc(ide_drive_t * drive, int mask)
 115{
 116        writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 117               (void __iomem *)IDE_CONTROL_REG);
 118}
 119
 120
 121static int
 122sgiioc4_checkirq(ide_hwif_t * hwif)
 123{
 124        unsigned long intr_addr =
 125                hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
 126
 127        if ((u8)readl((void __iomem *)intr_addr) & 0x03)
 128                return 1;
 129
 130        return 0;
 131}
 132
 133static u8 sgiioc4_INB(unsigned long);
 134
 135static int
 136sgiioc4_clearirq(ide_drive_t * drive)
 137{
 138        u32 intr_reg;
 139        ide_hwif_t *hwif = HWIF(drive);
 140        unsigned long other_ir =
 141            hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
 142
 143        /* Code to check for PCI error conditions */
 144        intr_reg = readl((void __iomem *)other_ir);
 145        if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
 146                /*
 147                 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
 148                 * of clearing the interrupt.  The first read should clear it
 149                 * if it is set.  The second read should return a "clear" status
 150                 * if it got cleared.  If not, then spin for a bit trying to
 151                 * clear it.
 152                 */
 153                u8 stat = sgiioc4_INB(IDE_STATUS_REG);
 154                int count = 0;
 155                stat = sgiioc4_INB(IDE_STATUS_REG);
 156                while ((stat & 0x80) && (count++ < 100)) {
 157                        udelay(1);
 158                        stat = sgiioc4_INB(IDE_STATUS_REG);
 159                }
 160
 161                if (intr_reg & 0x02) {
 162                        /* Error when transferring DMA data on PCI bus */
 163                        u32 pci_err_addr_low, pci_err_addr_high,
 164                            pci_stat_cmd_reg;
 165
 166                        pci_err_addr_low =
 167                                readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
 168                        pci_err_addr_high =
 169                                readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
 170                        pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
 171                                              &pci_stat_cmd_reg);
 172                        printk(KERN_ERR
 173                               "%s(%s) : PCI Bus Error when doing DMA:"
 174                                   " status-cmd reg is 0x%x\n",
 175                               __FUNCTION__, drive->name, pci_stat_cmd_reg);
 176                        printk(KERN_ERR
 177                               "%s(%s) : PCI Error Address is 0x%x%x\n",
 178                               __FUNCTION__, drive->name,
 179                               pci_err_addr_high, pci_err_addr_low);
 180                        /* Clear the PCI Error indicator */
 181                        pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
 182                                               0x00000146);
 183                }
 184
 185                /* Clear the Interrupt, Error bits on the IOC4 */
 186                writel(0x03, (void __iomem *)other_ir);
 187
 188                intr_reg = readl((void __iomem *)other_ir);
 189        }
 190
 191        return intr_reg & 3;
 192}
 193
 194static void sgiioc4_ide_dma_start(ide_drive_t * drive)
 195{
 196        ide_hwif_t *hwif = HWIF(drive);
 197        unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
 198        unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
 199        unsigned int temp_reg = reg | IOC4_S_DMA_START;
 200
 201        writel(temp_reg, (void __iomem *)ioc4_dma_addr);
 202}
 203
 204static u32
 205sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
 206{
 207        unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 208        u32     ioc4_dma;
 209        int     count;
 210
 211        count = 0;
 212        ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 213        while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
 214                udelay(1);
 215                ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 216        }
 217        return ioc4_dma;
 218}
 219
 220/* Stops the IOC4 DMA Engine */
 221static int
 222sgiioc4_ide_dma_end(ide_drive_t * drive)
 223{
 224        u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
 225        ide_hwif_t *hwif = HWIF(drive);
 226        unsigned long dma_base = hwif->dma_base;
 227        int dma_stat = 0;
 228        unsigned long *ending_dma = ide_get_hwifdata(hwif);
 229
 230        writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
 231
 232        ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 233
 234        if (ioc4_dma & IOC4_S_DMA_STOP) {
 235                printk(KERN_ERR
 236                       "%s(%s): IOC4 DMA STOP bit is still 1 :"
 237                       "ioc4_dma_reg 0x%x\n",
 238                       __FUNCTION__, drive->name, ioc4_dma);
 239                dma_stat = 1;
 240        }
 241
 242        /*
 243         * The IOC4 will DMA 1's to the ending dma area to indicate that
 244         * previous data DMA is complete.  This is necessary because of relaxed
 245         * ordering between register reads and DMA writes on the Altix.
 246         */
 247        while ((cnt++ < 200) && (!valid)) {
 248                for (num = 0; num < 16; num++) {
 249                        if (ending_dma[num]) {
 250                                valid = 1;
 251                                break;
 252                        }
 253                }
 254                udelay(1);
 255        }
 256        if (!valid) {
 257                printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
 258                       drive->name);
 259                dma_stat = 1;
 260        }
 261
 262        bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
 263        bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
 264
 265        if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
 266                if (bc_dev > bc_mem + 8) {
 267                        printk(KERN_ERR
 268                               "%s(%s): WARNING!! byte_count_dev %d "
 269                               "!= byte_count_mem %d\n",
 270                               __FUNCTION__, drive->name, bc_dev, bc_mem);
 271                }
 272        }
 273
 274        drive->waiting_for_dma = 0;
 275        ide_destroy_dmatable(drive);
 276
 277        return dma_stat;
 278}
 279
 280static int
 281sgiioc4_ide_dma_on(ide_drive_t * drive)
 282{
 283        drive->using_dma = 1;
 284
 285        return 0;
 286}
 287
 288static void sgiioc4_dma_off_quietly(ide_drive_t *drive)
 289{
 290        drive->using_dma = 0;
 291
 292        drive->hwif->dma_host_off(drive);
 293}
 294
 295static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
 296{
 297}
 298
 299/* returns 1 if dma irq issued, 0 otherwise */
 300static int
 301sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
 302{
 303        return sgiioc4_checkirq(HWIF(drive));
 304}
 305
 306static void sgiioc4_dma_host_on(ide_drive_t * drive)
 307{
 308}
 309
 310static void sgiioc4_dma_host_off(ide_drive_t * drive)
 311{
 312        sgiioc4_clearirq(drive);
 313}
 314
 315static void
 316sgiioc4_resetproc(ide_drive_t * drive)
 317{
 318        sgiioc4_ide_dma_end(drive);
 319        sgiioc4_clearirq(drive);
 320}
 321
 322static void
 323sgiioc4_dma_lost_irq(ide_drive_t * drive)
 324{
 325        sgiioc4_resetproc(drive);
 326
 327        ide_dma_lost_irq(drive);
 328}
 329
 330static u8
 331sgiioc4_INB(unsigned long port)
 332{
 333        u8 reg = (u8) readb((void __iomem *) port);
 334
 335        if ((port & 0xFFF) == 0x11C) {  /* Status register of IOC4 */
 336                if (reg & 0x51) {       /* Not busy...check for interrupt */
 337                        unsigned long other_ir = port - 0x110;
 338                        unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
 339
 340                        /* Clear the Interrupt, Error bits on the IOC4 */
 341                        if (intr_reg & 0x03) {
 342                                writel(0x03, (void __iomem *) other_ir);
 343                                intr_reg = (u32) readl((void __iomem *) other_ir);
 344                        }
 345                }
 346        }
 347
 348        return reg;
 349}
 350
 351/* Creates a dma map for the scatter-gather list entries */
 352static int __devinit
 353ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
 354{
 355        void __iomem *virt_dma_base;
 356        int num_ports = sizeof (ioc4_dma_regs_t);
 357        void *pad;
 358
 359        printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
 360               dma_base, dma_base + num_ports - 1);
 361
 362        if (!request_mem_region(dma_base, num_ports, hwif->name)) {
 363                printk(KERN_ERR
 364                       "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
 365                       "ALREADY in use\n",
 366                       __FUNCTION__, hwif->name, (void *) dma_base,
 367                       (void *) dma_base + num_ports - 1);
 368                return -1;
 369        }
 370
 371        virt_dma_base = ioremap(dma_base, num_ports);
 372        if (virt_dma_base == NULL) {
 373                printk(KERN_ERR
 374                       "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
 375                       __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
 376                goto dma_remap_failure;
 377        }
 378        hwif->dma_base = (unsigned long) virt_dma_base;
 379
 380        hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
 381                                          IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 382                                          &hwif->dmatable_dma);
 383
 384        if (!hwif->dmatable_cpu)
 385                goto dma_pci_alloc_failure;
 386
 387        hwif->sg_max_nents = IOC4_PRD_ENTRIES;
 388
 389        pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE,
 390                                   (dma_addr_t *) &(hwif->dma_status));
 391
 392        if (pad) {
 393                ide_set_hwifdata(hwif, pad);
 394                return 0;
 395        }
 396
 397        pci_free_consistent(hwif->pci_dev,
 398                            IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 399                            hwif->dmatable_cpu, hwif->dmatable_dma);
 400        printk(KERN_INFO
 401               "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
 402               __FUNCTION__, hwif->name);
 403        printk(KERN_INFO
 404               "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
 405
 406dma_pci_alloc_failure:
 407        iounmap(virt_dma_base);
 408
 409dma_remap_failure:
 410        release_mem_region(dma_base, num_ports);
 411
 412        return -1;
 413}
 414
 415/* Initializes the IOC4 DMA Engine */
 416static void
 417sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
 418{
 419        u32 ioc4_dma;
 420        ide_hwif_t *hwif = HWIF(drive);
 421        unsigned long dma_base = hwif->dma_base;
 422        unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 423        u32 dma_addr, ending_dma_addr;
 424
 425        ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 426
 427        if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
 428                printk(KERN_WARNING
 429                        "%s(%s):Warning!! DMA from previous transfer was still active\n",
 430                       __FUNCTION__, drive->name);
 431                writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 432                ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 433
 434                if (ioc4_dma & IOC4_S_DMA_STOP)
 435                        printk(KERN_ERR
 436                               "%s(%s) : IOC4 Dma STOP bit is still 1\n",
 437                               __FUNCTION__, drive->name);
 438        }
 439
 440        ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 441        if (ioc4_dma & IOC4_S_DMA_ERROR) {
 442                printk(KERN_WARNING
 443                       "%s(%s) : Warning!! - DMA Error during Previous"
 444                       " transfer | status 0x%x\n",
 445                       __FUNCTION__, drive->name, ioc4_dma);
 446                writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 447                ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 448
 449                if (ioc4_dma & IOC4_S_DMA_STOP)
 450                        printk(KERN_ERR
 451                               "%s(%s) : IOC4 DMA STOP bit is still 1\n",
 452                               __FUNCTION__, drive->name);
 453        }
 454
 455        /* Address of the Scatter Gather List */
 456        dma_addr = cpu_to_le32(hwif->dmatable_dma);
 457        writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
 458
 459        /* Address of the Ending DMA */
 460        memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
 461        ending_dma_addr = cpu_to_le32(hwif->dma_status);
 462        writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
 463
 464        writel(dma_direction, (void __iomem *)ioc4_dma_addr);
 465        drive->waiting_for_dma = 1;
 466}
 467
 468/* IOC4 Scatter Gather list Format                                       */
 469/* 128 Bit entries to support 64 bit addresses in the future             */
 470/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format      */
 471/* --------------------------------------------------------------------- */
 472/* | Upper 32 bits - Zero           |           Lower 32 bits- address | */
 473/* --------------------------------------------------------------------- */
 474/* | Upper 32 bits - Zero           |EOL| 15 unused     | 16 Bit Length| */
 475/* --------------------------------------------------------------------- */
 476/* Creates the scatter gather list, DMA Table */
 477static unsigned int
 478sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
 479{
 480        ide_hwif_t *hwif = HWIF(drive);
 481        unsigned int *table = hwif->dmatable_cpu;
 482        unsigned int count = 0, i = 1;
 483        struct scatterlist *sg;
 484
 485        hwif->sg_nents = i = ide_build_sglist(drive, rq);
 486
 487        if (!i)
 488                return 0;       /* sglist of length Zero */
 489
 490        sg = hwif->sg_table;
 491        while (i && sg_dma_len(sg)) {
 492                dma_addr_t cur_addr;
 493                int cur_len;
 494                cur_addr = sg_dma_address(sg);
 495                cur_len = sg_dma_len(sg);
 496
 497                while (cur_len) {
 498                        if (count++ >= IOC4_PRD_ENTRIES) {
 499                                printk(KERN_WARNING
 500                                       "%s: DMA table too small\n",
 501                                       drive->name);
 502                                goto use_pio_instead;
 503                        } else {
 504                                u32 bcount =
 505                                    0x10000 - (cur_addr & 0xffff);
 506
 507                                if (bcount > cur_len)
 508                                        bcount = cur_len;
 509
 510                                /* put the addr, length in
 511                                 * the IOC4 dma-table format */
 512                                *table = 0x0;
 513                                table++;
 514                                *table = cpu_to_be32(cur_addr);
 515                                table++;
 516                                *table = 0x0;
 517                                table++;
 518
 519                                *table = cpu_to_be32(bcount);
 520                                table++;
 521
 522                                cur_addr += bcount;
 523                                cur_len -= bcount;
 524                        }
 525                }
 526
 527                sg = sg_next(sg);
 528                i--;
 529        }
 530
 531        if (count) {
 532                table--;
 533                *table |= cpu_to_be32(0x80000000);
 534                return count;
 535        }
 536
 537use_pio_instead:
 538        pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
 539                     hwif->sg_dma_direction);
 540
 541        return 0;               /* revert to PIO for this request */
 542}
 543
 544static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
 545{
 546        struct request *rq = HWGROUP(drive)->rq;
 547        unsigned int count = 0;
 548        int ddir;
 549
 550        if (rq_data_dir(rq))
 551                ddir = PCI_DMA_TODEVICE;
 552        else
 553                ddir = PCI_DMA_FROMDEVICE;
 554
 555        if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
 556                /* try PIO instead of DMA */
 557                ide_map_sg(drive, rq);
 558                return 1;
 559        }
 560
 561        if (rq_data_dir(rq))
 562                /* Writes TO the IOC4 FROM Main Memory */
 563                ddir = IOC4_DMA_READ;
 564        else
 565                /* Writes FROM the IOC4 TO Main Memory */
 566                ddir = IOC4_DMA_WRITE;
 567
 568        sgiioc4_configure_for_dma(ddir, drive);
 569
 570        return 0;
 571}
 572
 573static void __devinit
 574ide_init_sgiioc4(ide_hwif_t * hwif)
 575{
 576        hwif->mmio = 1;
 577        hwif->pio_mask = 0x00;
 578        hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */
 579        hwif->set_dma_mode = &sgiioc4_set_dma_mode;
 580        hwif->selectproc = NULL;/* Use the default routine to select drive */
 581        hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
 582        hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
 583        hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
 584                                                clear interrupts */
 585        hwif->intrproc = NULL;  /* Enable or Disable interrupt from drive */
 586        hwif->maskproc = &sgiioc4_maskproc;     /* Mask on/off NIEN register */
 587        hwif->quirkproc = NULL;
 588        hwif->busproc = NULL;
 589
 590        hwif->INB = &sgiioc4_INB;
 591
 592        if (hwif->dma_base == 0)
 593                return;
 594
 595        hwif->mwdma_mask = ATA_MWDMA2_ONLY;
 596
 597        hwif->dma_setup = &sgiioc4_ide_dma_setup;
 598        hwif->dma_start = &sgiioc4_ide_dma_start;
 599        hwif->ide_dma_end = &sgiioc4_ide_dma_end;
 600        hwif->ide_dma_on = &sgiioc4_ide_dma_on;
 601        hwif->dma_off_quietly = &sgiioc4_dma_off_quietly;
 602        hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
 603        hwif->dma_host_on = &sgiioc4_dma_host_on;
 604        hwif->dma_host_off = &sgiioc4_dma_host_off;
 605        hwif->dma_lost_irq = &sgiioc4_dma_lost_irq;
 606        hwif->dma_timeout = &ide_dma_timeout;
 607}
 608
 609static int __devinit
 610sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
 611{
 612        unsigned long cmd_base, dma_base, irqport;
 613        unsigned long bar0, cmd_phys_base, ctl;
 614        void __iomem *virt_base;
 615        ide_hwif_t *hwif;
 616        int h;
 617        u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 618
 619        /*
 620         * Find an empty HWIF; if none available, return -ENOMEM.
 621         */
 622        for (h = 0; h < MAX_HWIFS; ++h) {
 623                hwif = &ide_hwifs[h];
 624                if (hwif->chipset == ide_unknown)
 625                        break;
 626        }
 627        if (h == MAX_HWIFS) {
 628                printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n",
 629                                DRV_NAME);
 630                return -ENOMEM;
 631        }
 632
 633        /*  Get the CmdBlk and CtrlBlk Base Registers */
 634        bar0 = pci_resource_start(dev, 0);
 635        virt_base = ioremap(bar0, pci_resource_len(dev, 0));
 636        if (virt_base == NULL) {
 637                printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
 638                                DRV_NAME, bar0);
 639                return -ENOMEM;
 640        }
 641        cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
 642        ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
 643        irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
 644        dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
 645
 646        cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
 647        if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
 648            hwif->name)) {
 649                printk(KERN_ERR
 650                        "%s : %s -- ERROR, Addresses "
 651                        "0x%p to 0x%p ALREADY in use\n",
 652                       __FUNCTION__, hwif->name, (void *) cmd_phys_base,
 653                       (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
 654                return -ENOMEM;
 655        }
 656
 657        if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
 658                hw_regs_t hw;
 659
 660                /* Initialize the IO registers */
 661                memset(&hw, 0, sizeof(hw));
 662                sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
 663                memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
 664                hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
 665        }
 666
 667        hwif->irq = dev->irq;
 668        hwif->chipset = ide_pci;
 669        hwif->pci_dev = dev;
 670        hwif->channel = 0;      /* Single Channel chip */
 671        hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
 672
 673        /* The IOC4 uses MMIO rather than Port IO. */
 674        default_hwif_mmiops(hwif);
 675
 676        /* Initializing chipset IRQ Registers */
 677        writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
 678
 679        if (dma_base == 0 || ide_dma_sgiioc4(hwif, dma_base))
 680                printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
 681                                 hwif->name, DRV_NAME);
 682
 683        ide_init_sgiioc4(hwif);
 684
 685        idx[0] = hwif->index;
 686
 687        if (ide_device_add(idx))
 688                return -EIO;
 689
 690        return 0;
 691}
 692
 693static unsigned int __devinit
 694pci_init_sgiioc4(struct pci_dev *dev)
 695{
 696        int ret;
 697
 698        printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
 699                         DRV_NAME, pci_name(dev), dev->revision);
 700
 701        if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
 702                printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
 703                                "firmware is obsolete - please upgrade to "
 704                                "revision46 or higher\n",
 705                                DRV_NAME, pci_name(dev));
 706                ret = -EAGAIN;
 707                goto out;
 708        }
 709        ret = sgiioc4_ide_setup_pci_device(dev);
 710out:
 711        return ret;
 712}
 713
 714int
 715ioc4_ide_attach_one(struct ioc4_driver_data *idd)
 716{
 717        /* PCI-RT does not bring out IDE connection.
 718         * Do not attach to this particular IOC4.
 719         */
 720        if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
 721                return 0;
 722
 723        return pci_init_sgiioc4(idd->idd_pdev);
 724}
 725
 726static struct ioc4_submodule ioc4_ide_submodule = {
 727        .is_name = "IOC4_ide",
 728        .is_owner = THIS_MODULE,
 729        .is_probe = ioc4_ide_attach_one,
 730/*      .is_remove = ioc4_ide_remove_one,       */
 731};
 732
 733static int __init ioc4_ide_init(void)
 734{
 735        return ioc4_register_submodule(&ioc4_ide_submodule);
 736}
 737
 738late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
 739
 740MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
 741MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
 742MODULE_LICENSE("GPL");
 743
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