linux/drivers/ide/pci/serverworks.c
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   1/*
   2 * linux/drivers/ide/pci/serverworks.c          Version 0.22    Jun 27 2007
   3 *
   4 * Copyright (C) 1998-2000 Michel Aubry
   5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   8 * Portions copyright (c) 2001 Sun Microsystems
   9 *
  10 *
  11 * RCC/ServerWorks IDE driver for Linux
  12 *
  13 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  14 *         supports UDMA mode 2 (33 MB/s)
  15 *
  16 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  17 *         all revisions support UDMA mode 4 (66 MB/s)
  18 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  19 *
  20 *         *** The CSB5 does not provide ANY register ***
  21 *         *** to detect 80-conductor cable presence. ***
  22 *
  23 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  24 *
  25 *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  26 *   controller same as the CSB6. Single channel ATA100 only.
  27 *
  28 * Documentation:
  29 *      Available under NDA only. Errata info very hard to get.
  30 *
  31 */
  32
  33#include <linux/types.h>
  34#include <linux/module.h>
  35#include <linux/kernel.h>
  36#include <linux/ioport.h>
  37#include <linux/pci.h>
  38#include <linux/hdreg.h>
  39#include <linux/ide.h>
  40#include <linux/init.h>
  41#include <linux/delay.h>
  42
  43#include <asm/io.h>
  44
  45#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  46#define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  47
  48/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  49 * can overrun their FIFOs when used with the CSB5 */
  50static const char *svwks_bad_ata100[] = {
  51        "ST320011A",
  52        "ST340016A",
  53        "ST360021A",
  54        "ST380021A",
  55        NULL
  56};
  57
  58static struct pci_dev *isa_dev;
  59
  60static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  61{
  62        while (*list)
  63                if (!strcmp(*list++, drive->id->model))
  64                        return 1;
  65        return 0;
  66}
  67
  68static u8 svwks_udma_filter(ide_drive_t *drive)
  69{
  70        struct pci_dev *dev     = HWIF(drive)->pci_dev;
  71        u8 mask = 0;
  72
  73        if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  74                return 0x1f;
  75        if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  76                u32 reg = 0;
  77                if (isa_dev)
  78                        pci_read_config_dword(isa_dev, 0x64, &reg);
  79                        
  80                /*
  81                 *      Don't enable UDMA on disk devices for the moment
  82                 */
  83                if(drive->media == ide_disk)
  84                        return 0;
  85                /* Check the OSB4 DMA33 enable bit */
  86                return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  87        } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  88                return 0x07;
  89        } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
  90                u8 btr = 0, mode;
  91                pci_read_config_byte(dev, 0x5A, &btr);
  92                mode = btr & 0x3;
  93
  94                /* If someone decides to do UDMA133 on CSB5 the same
  95                   issue will bite so be inclusive */
  96                if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  97                        mode = 2;
  98
  99                switch(mode) {
 100                case 3:  mask = 0x3f; break;
 101                case 2:  mask = 0x1f; break;
 102                case 1:  mask = 0x07; break;
 103                default: mask = 0x00; break;
 104                }
 105        }
 106        if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 107             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 108            (!(PCI_FUNC(dev->devfn) & 1)))
 109                mask = 0x1f;
 110
 111        return mask;
 112}
 113
 114static u8 svwks_csb_check (struct pci_dev *dev)
 115{
 116        switch (dev->device) {
 117                case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 118                case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 119                case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 120                case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 121                        return 1;
 122                default:
 123                        break;
 124        }
 125        return 0;
 126}
 127
 128static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
 129{
 130        static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 131        static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
 132
 133        struct pci_dev *dev = drive->hwif->pci_dev;
 134
 135        pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
 136
 137        if (svwks_csb_check(dev)) {
 138                u16 csb_pio = 0;
 139
 140                pci_read_config_word(dev, 0x4a, &csb_pio);
 141
 142                csb_pio &= ~(0x0f << (4 * drive->dn));
 143                csb_pio |= (pio << (4 * drive->dn));
 144
 145                pci_write_config_word(dev, 0x4a, csb_pio);
 146        }
 147}
 148
 149static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
 150{
 151        static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 152        static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 153        static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 154
 155        ide_hwif_t *hwif        = HWIF(drive);
 156        struct pci_dev *dev     = hwif->pci_dev;
 157        u8 unit                 = (drive->select.b.unit & 0x01);
 158
 159        u8 ultra_enable  = 0, ultra_timing = 0, dma_timing = 0;
 160
 161        pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 162        pci_read_config_byte(dev, 0x54, &ultra_enable);
 163
 164        ultra_timing    &= ~(0x0F << (4*unit));
 165        ultra_enable    &= ~(0x01 << drive->dn);
 166
 167        switch(speed) {
 168                case XFER_MW_DMA_2:
 169                case XFER_MW_DMA_1:
 170                case XFER_MW_DMA_0:
 171                        dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 172                        break;
 173
 174                case XFER_UDMA_5:
 175                case XFER_UDMA_4:
 176                case XFER_UDMA_3:
 177                case XFER_UDMA_2:
 178                case XFER_UDMA_1:
 179                case XFER_UDMA_0:
 180                        dma_timing   |= dma_modes[2];
 181                        ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 182                        ultra_enable |= (0x01 << drive->dn);
 183                default:
 184                        break;
 185        }
 186
 187        pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 188        pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 189        pci_write_config_byte(dev, 0x54, ultra_enable);
 190}
 191
 192static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 193{
 194        unsigned int reg;
 195        u8 btr;
 196
 197        /* force Master Latency Timer value to 64 PCICLKs */
 198        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 199
 200        /* OSB4 : South Bridge and IDE */
 201        if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 202                isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 203                          PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 204                if (isa_dev) {
 205                        pci_read_config_dword(isa_dev, 0x64, &reg);
 206                        reg &= ~0x00002000; /* disable 600ns interrupt mask */
 207                        if(!(reg & 0x00004000))
 208                                printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 209                        reg |=  0x00004000; /* enable UDMA/33 support */
 210                        pci_write_config_dword(isa_dev, 0x64, reg);
 211                }
 212        }
 213
 214        /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 215        else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 216                 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 217                 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 218
 219                /* Third Channel Test */
 220                if (!(PCI_FUNC(dev->devfn) & 1)) {
 221                        struct pci_dev * findev = NULL;
 222                        u32 reg4c = 0;
 223                        findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 224                                PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 225                        if (findev) {
 226                                pci_read_config_dword(findev, 0x4C, &reg4c);
 227                                reg4c &= ~0x000007FF;
 228                                reg4c |=  0x00000040;
 229                                reg4c |=  0x00000020;
 230                                pci_write_config_dword(findev, 0x4C, reg4c);
 231                                pci_dev_put(findev);
 232                        }
 233                        outb_p(0x06, 0x0c00);
 234                        dev->irq = inb_p(0x0c01);
 235                } else {
 236                        struct pci_dev * findev = NULL;
 237                        u8 reg41 = 0;
 238
 239                        findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 240                                        PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 241                        if (findev) {
 242                                pci_read_config_byte(findev, 0x41, &reg41);
 243                                reg41 &= ~0x40;
 244                                pci_write_config_byte(findev, 0x41, reg41);
 245                                pci_dev_put(findev);
 246                        }
 247                        /*
 248                         * This is a device pin issue on CSB6.
 249                         * Since there will be a future raid mode,
 250                         * early versions of the chipset require the
 251                         * interrupt pin to be set, and it is a compatibility
 252                         * mode issue.
 253                         */
 254                        if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 255                                dev->irq = 0;
 256                }
 257//              pci_read_config_dword(dev, 0x40, &pioreg)
 258//              pci_write_config_dword(dev, 0x40, 0x99999999);
 259//              pci_read_config_dword(dev, 0x44, &dmareg);
 260//              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 261                /* setup the UDMA Control register
 262                 *
 263                 * 1. clear bit 6 to enable DMA
 264                 * 2. enable DMA modes with bits 0-1
 265                 *      00 : legacy
 266                 *      01 : udma2
 267                 *      10 : udma2/udma4
 268                 *      11 : udma2/udma4/udma5
 269                 */
 270                pci_read_config_byte(dev, 0x5A, &btr);
 271                btr &= ~0x40;
 272                if (!(PCI_FUNC(dev->devfn) & 1))
 273                        btr |= 0x2;
 274                else
 275                        btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 276                pci_write_config_byte(dev, 0x5A, btr);
 277        }
 278        /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 279        else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 280                pci_read_config_byte(dev, 0x5A, &btr);
 281                btr &= ~0x40;
 282                btr |= 0x3;
 283                pci_write_config_byte(dev, 0x5A, btr);
 284        }
 285
 286        return dev->irq;
 287}
 288
 289static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
 290{
 291        return ATA_CBL_PATA80;
 292}
 293
 294/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 295 * of the subsystem device ID indicate presence of an 80-pin cable.
 296 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 297 * Bit 15 set   = secondary IDE channel has 80-pin cable.
 298 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 299 * Bit 14 set   = primary IDE channel has 80-pin cable.
 300 */
 301static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
 302{
 303        struct pci_dev *dev = hwif->pci_dev;
 304        if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 305            dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 306            (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 307             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 308                return ((1 << (hwif->channel + 14)) &
 309                        dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 310        return ATA_CBL_PATA40;
 311}
 312
 313/* Sun Cobalt Alpine hardware avoids the 80-pin cable
 314 * detect issue by attaching the drives directly to the board.
 315 * This check follows the Dell precedent (how scary is that?!)
 316 *
 317 * WARNING: this only works on Alpine hardware!
 318 */
 319static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
 320{
 321        struct pci_dev *dev = hwif->pci_dev;
 322        if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 323            dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 324            dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 325                return ((1 << (hwif->channel + 14)) &
 326                        dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 327        return ATA_CBL_PATA40;
 328}
 329
 330static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
 331{
 332        struct pci_dev *dev = hwif->pci_dev;
 333
 334        /* Server Works */
 335        if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 336                return ata66_svwks_svwks (hwif);
 337        
 338        /* Dell PowerEdge */
 339        if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 340                return ata66_svwks_dell (hwif);
 341
 342        /* Cobalt Alpine */
 343        if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 344                return ata66_svwks_cobalt (hwif);
 345
 346        /* Per Specified Design by OEM, and ASIC Architect */
 347        if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 348            (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 349                return ATA_CBL_PATA80;
 350
 351        return ATA_CBL_PATA40;
 352}
 353
 354static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 355{
 356        hwif->set_pio_mode = &svwks_set_pio_mode;
 357        hwif->set_dma_mode = &svwks_set_dma_mode;
 358        hwif->udma_filter = &svwks_udma_filter;
 359
 360        if (!hwif->dma_base)
 361                return;
 362
 363        if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 364                if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 365                        hwif->cbl = ata66_svwks(hwif);
 366        }
 367}
 368
 369static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
 370        {       /* 0 */
 371                .name           = "SvrWks OSB4",
 372                .init_chipset   = init_chipset_svwks,
 373                .init_hwif      = init_hwif_svwks,
 374                .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
 375                .pio_mask       = ATA_PIO4,
 376                .mwdma_mask     = ATA_MWDMA2,
 377                .udma_mask      = 0x00, /* UDMA is problematic on OSB4 */
 378        },{     /* 1 */
 379                .name           = "SvrWks CSB5",
 380                .init_chipset   = init_chipset_svwks,
 381                .init_hwif      = init_hwif_svwks,
 382                .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
 383                .pio_mask       = ATA_PIO4,
 384                .mwdma_mask     = ATA_MWDMA2,
 385                .udma_mask      = ATA_UDMA5,
 386        },{     /* 2 */
 387                .name           = "SvrWks CSB6",
 388                .init_chipset   = init_chipset_svwks,
 389                .init_hwif      = init_hwif_svwks,
 390                .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
 391                .pio_mask       = ATA_PIO4,
 392                .mwdma_mask     = ATA_MWDMA2,
 393                .udma_mask      = ATA_UDMA5,
 394        },{     /* 3 */
 395                .name           = "SvrWks CSB6",
 396                .init_chipset   = init_chipset_svwks,
 397                .init_hwif      = init_hwif_svwks,
 398                .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE |
 399                                  IDE_HFLAG_BOOTABLE,
 400                .pio_mask       = ATA_PIO4,
 401                .mwdma_mask     = ATA_MWDMA2,
 402                .udma_mask      = ATA_UDMA5,
 403        },{     /* 4 */
 404                .name           = "SvrWks HT1000",
 405                .init_chipset   = init_chipset_svwks,
 406                .init_hwif      = init_hwif_svwks,
 407                .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE |
 408                                  IDE_HFLAG_BOOTABLE,
 409                .pio_mask       = ATA_PIO4,
 410                .mwdma_mask     = ATA_MWDMA2,
 411                .udma_mask      = ATA_UDMA5,
 412        }
 413};
 414
 415/**
 416 *      svwks_init_one  -       called when a OSB/CSB is found
 417 *      @dev: the svwks device
 418 *      @id: the matching pci id
 419 *
 420 *      Called when the PCI registration layer (or the IDE initialization)
 421 *      finds a device matching our IDE device tables.
 422 */
 423 
 424static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 425{
 426        struct ide_port_info d;
 427        u8 idx = id->driver_data;
 428
 429        d = serverworks_chipsets[idx];
 430
 431        if (idx == 2 || idx == 3) {
 432                if ((PCI_FUNC(dev->devfn) & 1) == 0) {
 433                        if (pci_resource_start(dev, 0) != 0x01f1)
 434                                d.host_flags &= ~IDE_HFLAG_BOOTABLE;
 435                        d.host_flags |= IDE_HFLAG_SINGLE;
 436                } else
 437                        d.host_flags &= ~IDE_HFLAG_SINGLE;
 438        }
 439
 440        return ide_setup_pci_device(dev, &d);
 441}
 442
 443static const struct pci_device_id svwks_pci_tbl[] = {
 444        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
 445        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
 446        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
 447        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
 448        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
 449        { 0, },
 450};
 451MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 452
 453static struct pci_driver driver = {
 454        .name           = "Serverworks_IDE",
 455        .id_table       = svwks_pci_tbl,
 456        .probe          = svwks_init_one,
 457};
 458
 459static int __init svwks_ide_init(void)
 460{
 461        return ide_pci_register_driver(&driver);
 462}
 463
 464module_init(svwks_ide_init);
 465
 466MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 467MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 468MODULE_LICENSE("GPL");
 469
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