linux/drivers/ide/pci/sc1200.c
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   1/*
   2 * linux/drivers/ide/pci/sc1200.c               Version 0.97    Aug 3 2007
   3 *
   4 * Copyright (C) 2000-2002              Mark Lord <mlord@pobox.com>
   5 * Copyright (C)      2007              Bartlomiej Zolnierkiewicz
   6 *
   7 * May be copied or modified under the terms of the GNU General Public License
   8 *
   9 * Development of this chipset driver was funded
  10 * by the nice folks at National Semiconductor.
  11 *
  12 * Documentation:
  13 *      Available from National Semiconductor
  14 */
  15
  16#include <linux/module.h>
  17#include <linux/types.h>
  18#include <linux/kernel.h>
  19#include <linux/delay.h>
  20#include <linux/timer.h>
  21#include <linux/mm.h>
  22#include <linux/ioport.h>
  23#include <linux/blkdev.h>
  24#include <linux/hdreg.h>
  25#include <linux/interrupt.h>
  26#include <linux/pci.h>
  27#include <linux/init.h>
  28#include <linux/ide.h>
  29#include <linux/pm.h>
  30#include <asm/io.h>
  31#include <asm/irq.h>
  32
  33#define SC1200_REV_A    0x00
  34#define SC1200_REV_B1   0x01
  35#define SC1200_REV_B3   0x02
  36#define SC1200_REV_C1   0x03
  37#define SC1200_REV_D1   0x04
  38
  39#define PCI_CLK_33      0x00
  40#define PCI_CLK_48      0x01
  41#define PCI_CLK_66      0x02
  42#define PCI_CLK_33A     0x03
  43
  44static unsigned short sc1200_get_pci_clock (void)
  45{
  46        unsigned char chip_id, silicon_revision;
  47        unsigned int pci_clock;
  48        /*
  49         * Check the silicon revision, as not all versions of the chip
  50         * have the register with the fast PCI bus timings.
  51         */
  52        chip_id = inb (0x903c);
  53        silicon_revision = inb (0x903d);
  54
  55        // Read the fast pci clock frequency
  56        if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
  57                pci_clock = PCI_CLK_33;
  58        } else {
  59                // check clock generator configuration (cfcc)
  60                // the clock is in bits 8 and 9 of this word
  61
  62                pci_clock = inw (0x901e);
  63                pci_clock >>= 8;
  64                pci_clock &= 0x03;
  65                if (pci_clock == PCI_CLK_33A)
  66                        pci_clock = PCI_CLK_33;
  67        }
  68        return pci_clock;
  69}
  70
  71/*
  72 * Here are the standard PIO mode 0-4 timings for each "format".
  73 * Format-0 uses fast data reg timings, with slower command reg timings.
  74 * Format-1 uses fast timings for all registers, but won't work with all drives.
  75 */
  76static const unsigned int sc1200_pio_timings[4][5] =
  77        {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},  // format0  33Mhz
  78         {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},  // format1, 33Mhz
  79         {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},  // format1, 48Mhz
  80         {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
  81
  82/*
  83 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
  84 */
  85//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
  86
  87static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
  88{
  89        ide_hwif_t *hwif = drive->hwif;
  90        struct pci_dev *pdev = hwif->pci_dev;
  91        unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
  92
  93        pci_read_config_dword(pdev, basereg + 4, &format);
  94        format = (format >> 31) & 1;
  95        if (format)
  96                format += sc1200_get_pci_clock();
  97        pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
  98                               sc1200_pio_timings[format][pio]);
  99}
 100
 101/*
 102 *      The SC1200 specifies that two drives sharing a cable cannot mix
 103 *      UDMA/MDMA.  It has to be one or the other, for the pair, though
 104 *      different timings can still be chosen for each drive.  We could
 105 *      set the appropriate timing bits on the fly, but that might be
 106 *      a bit confusing.  So, for now we statically handle this requirement
 107 *      by looking at our mate drive to see what it is capable of, before
 108 *      choosing a mode for our own drive.
 109 */
 110static u8 sc1200_udma_filter(ide_drive_t *drive)
 111{
 112        ide_hwif_t *hwif = drive->hwif;
 113        ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
 114        struct hd_driveid *mateid = mate->id;
 115        u8 mask = hwif->ultra_mask;
 116
 117        if (mate->present == 0)
 118                goto out;
 119
 120        if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
 121                if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
 122                        goto out;
 123                if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
 124                        mask = 0;
 125        }
 126out:
 127        return mask;
 128}
 129
 130static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
 131{
 132        ide_hwif_t              *hwif = HWIF(drive);
 133        int                     unit = drive->select.b.unit;
 134        unsigned int            reg, timings;
 135        unsigned short          pci_clock;
 136        unsigned int            basereg = hwif->channel ? 0x50 : 0x40;
 137
 138        pci_clock = sc1200_get_pci_clock();
 139
 140        /*
 141         * Note that each DMA mode has several timings associated with it.
 142         * The correct timing depends on the fast PCI clock freq.
 143         */
 144        timings = 0;
 145        switch (mode) {
 146                case XFER_UDMA_0:
 147                        switch (pci_clock) {
 148                                case PCI_CLK_33:        timings = 0x00921250;   break;
 149                                case PCI_CLK_48:        timings = 0x00932470;   break;
 150                                case PCI_CLK_66:        timings = 0x009436a1;   break;
 151                        }
 152                        break;
 153                case XFER_UDMA_1:
 154                        switch (pci_clock) {
 155                                case PCI_CLK_33:        timings = 0x00911140;   break;
 156                                case PCI_CLK_48:        timings = 0x00922260;   break;
 157                                case PCI_CLK_66:        timings = 0x00933481;   break;
 158                        }
 159                        break;
 160                case XFER_UDMA_2:
 161                        switch (pci_clock) {
 162                                case PCI_CLK_33:        timings = 0x00911030;   break;
 163                                case PCI_CLK_48:        timings = 0x00922140;   break;
 164                                case PCI_CLK_66:        timings = 0x00923261;   break;
 165                        }
 166                        break;
 167                case XFER_MW_DMA_0:
 168                        switch (pci_clock) {
 169                                case PCI_CLK_33:        timings = 0x00077771;   break;
 170                                case PCI_CLK_48:        timings = 0x000bbbb2;   break;
 171                                case PCI_CLK_66:        timings = 0x000ffff3;   break;
 172                        }
 173                        break;
 174                case XFER_MW_DMA_1:
 175                        switch (pci_clock) {
 176                                case PCI_CLK_33:        timings = 0x00012121;   break;
 177                                case PCI_CLK_48:        timings = 0x00024241;   break;
 178                                case PCI_CLK_66:        timings = 0x00035352;   break;
 179                        }
 180                        break;
 181                case XFER_MW_DMA_2:
 182                        switch (pci_clock) {
 183                                case PCI_CLK_33:        timings = 0x00002020;   break;
 184                                case PCI_CLK_48:        timings = 0x00013131;   break;
 185                                case PCI_CLK_66:        timings = 0x00015151;   break;
 186                        }
 187                        break;
 188                default:
 189                        return;
 190        }
 191
 192        if (unit == 0) {                        /* are we configuring drive0? */
 193                pci_read_config_dword(hwif->pci_dev, basereg+4, &reg);
 194                timings |= reg & 0x80000000;    /* preserve PIO format bit */
 195                pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
 196        } else {
 197                pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
 198        }
 199}
 200
 201/*  Replacement for the standard ide_dma_end action in
 202 *  dma_proc.
 203 *
 204 *  returns 1 on error, 0 otherwise
 205 */
 206static int sc1200_ide_dma_end (ide_drive_t *drive)
 207{
 208        ide_hwif_t *hwif = HWIF(drive);
 209        unsigned long dma_base = hwif->dma_base;
 210        byte dma_stat;
 211
 212        dma_stat = inb(dma_base+2);             /* get DMA status */
 213
 214        if (!(dma_stat & 4))
 215                printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
 216                  dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
 217
 218        outb(dma_stat|0x1b, dma_base+2);        /* clear the INTR & ERROR bits */
 219        outb(inb(dma_base)&~1, dma_base);       /* !! DO THIS HERE !! stop DMA */
 220
 221        drive->waiting_for_dma = 0;
 222        ide_destroy_dmatable(drive);            /* purge DMA mappings */
 223
 224        return (dma_stat & 7) != 4;             /* verify good DMA status */
 225}
 226
 227/*
 228 * sc1200_set_pio_mode() handles setting of PIO modes
 229 * for both the chipset and drive.
 230 *
 231 * All existing BIOSs for this chipset guarantee that all drives
 232 * will have valid default PIO timings set up before we get here.
 233 */
 234
 235static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
 236{
 237        ide_hwif_t      *hwif = HWIF(drive);
 238        int             mode = -1;
 239
 240        /*
 241         * bad abuse of ->set_pio_mode interface
 242         */
 243        switch (pio) {
 244                case 200: mode = XFER_UDMA_0;   break;
 245                case 201: mode = XFER_UDMA_1;   break;
 246                case 202: mode = XFER_UDMA_2;   break;
 247                case 100: mode = XFER_MW_DMA_0; break;
 248                case 101: mode = XFER_MW_DMA_1; break;
 249                case 102: mode = XFER_MW_DMA_2; break;
 250        }
 251        if (mode != -1) {
 252                printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
 253                hwif->dma_off_quietly(drive);
 254                if (ide_set_dma_mode(drive, mode) == 0)
 255                        hwif->dma_host_on(drive);
 256                return;
 257        }
 258
 259        sc1200_tunepio(drive, pio);
 260}
 261
 262#ifdef CONFIG_PM
 263static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev)
 264{
 265        int     h;
 266
 267        for (h = 0; h < MAX_HWIFS; h++) {
 268                ide_hwif_t *hwif = &ide_hwifs[h];
 269                if (prev) {
 270                        if (hwif == prev)
 271                                prev = NULL;    // found previous, now look for next match
 272                } else {
 273                        if (hwif && hwif->pci_dev == dev)
 274                                return hwif;    // found next match
 275                }
 276        }
 277        return NULL;    // not found
 278}
 279
 280typedef struct sc1200_saved_state_s {
 281        __u32           regs[4];
 282} sc1200_saved_state_t;
 283
 284
 285static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
 286{
 287        ide_hwif_t              *hwif = NULL;
 288
 289        printk("SC1200: suspend(%u)\n", state.event);
 290
 291        if (state.event == PM_EVENT_ON) {
 292                // we only save state when going from full power to less
 293
 294                //
 295                // Loop over all interfaces that are part of this PCI device:
 296                //
 297                while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
 298                        sc1200_saved_state_t    *ss;
 299                        unsigned int            basereg, r;
 300                        //
 301                        // allocate a permanent save area, if not already allocated
 302                        //
 303                        ss = (sc1200_saved_state_t *)hwif->config_data;
 304                        if (ss == NULL) {
 305                                ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
 306                                if (ss == NULL)
 307                                        return -ENOMEM;
 308                                hwif->config_data = (unsigned long)ss;
 309                        }
 310                        ss = (sc1200_saved_state_t *)hwif->config_data;
 311                        //
 312                        // Save timing registers:  this may be unnecessary if 
 313                        // BIOS also does it
 314                        //
 315                        basereg = hwif->channel ? 0x50 : 0x40;
 316                        for (r = 0; r < 4; ++r) {
 317                                pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
 318                        }
 319                }
 320        }
 321
 322        /* You don't need to iterate over disks -- sysfs should have done that for you already */ 
 323
 324        pci_disable_device(dev);
 325        pci_set_power_state(dev, pci_choose_state(dev, state));
 326        return 0;
 327}
 328
 329static int sc1200_resume (struct pci_dev *dev)
 330{
 331        ide_hwif_t      *hwif = NULL;
 332        int             i;
 333
 334        i = pci_enable_device(dev);
 335        if (i)
 336                return i;
 337
 338        //
 339        // loop over all interfaces that are part of this pci device:
 340        //
 341        while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
 342                unsigned int            basereg, r;
 343                sc1200_saved_state_t    *ss = (sc1200_saved_state_t *)hwif->config_data;
 344
 345                //
 346                // Restore timing registers:  this may be unnecessary if BIOS also does it
 347                //
 348                basereg = hwif->channel ? 0x50 : 0x40;
 349                if (ss != NULL) {
 350                        for (r = 0; r < 4; ++r) {
 351                                pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
 352                        }
 353                }
 354        }
 355        return 0;
 356}
 357#endif
 358
 359/*
 360 * This gets invoked by the IDE driver once for each channel,
 361 * and performs channel-specific pre-initialization before drive probing.
 362 */
 363static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
 364{
 365        hwif->set_pio_mode = &sc1200_set_pio_mode;
 366        hwif->set_dma_mode = &sc1200_set_dma_mode;
 367
 368        if (hwif->dma_base == 0)
 369                return;
 370
 371        hwif->udma_filter = sc1200_udma_filter;
 372        hwif->ide_dma_end   = &sc1200_ide_dma_end;
 373}
 374
 375static const struct ide_port_info sc1200_chipset __devinitdata = {
 376        .name           = "SC1200",
 377        .init_hwif      = init_hwif_sc1200,
 378        .host_flags     = IDE_HFLAG_SERIALIZE |
 379                          IDE_HFLAG_POST_SET_MODE |
 380                          IDE_HFLAG_ABUSE_DMA_MODES |
 381                          IDE_HFLAG_BOOTABLE,
 382        .pio_mask       = ATA_PIO4,
 383        .mwdma_mask     = ATA_MWDMA2,
 384        .udma_mask      = ATA_UDMA2,
 385};
 386
 387static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 388{
 389        return ide_setup_pci_device(dev, &sc1200_chipset);
 390}
 391
 392static const struct pci_device_id sc1200_pci_tbl[] = {
 393        { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
 394        { 0, },
 395};
 396MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
 397
 398static struct pci_driver driver = {
 399        .name           = "SC1200_IDE",
 400        .id_table       = sc1200_pci_tbl,
 401        .probe          = sc1200_init_one,
 402#ifdef CONFIG_PM
 403        .suspend        = sc1200_suspend,
 404        .resume         = sc1200_resume,
 405#endif
 406};
 407
 408static int __init sc1200_ide_init(void)
 409{
 410        return ide_pci_register_driver(&driver);
 411}
 412
 413module_init(sc1200_ide_init);
 414
 415MODULE_AUTHOR("Mark Lord");
 416MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
 417MODULE_LICENSE("GPL");
 418
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