linux/drivers/ide/pci/piix.c
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   1/*
   2 *  linux/drivers/ide/pci/piix.c        Version 0.54    Sep 5, 2007
   3 *
   4 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   5 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   6 *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
   7 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   8 *
   9 *  May be copied or modified under the terms of the GNU General Public License
  10 *
  11 *  PIO mode setting function for Intel chipsets.
  12 *  For use instead of BIOS settings.
  13 *
  14 * 40-41
  15 * 42-43
  16 * 
  17 *                 41
  18 *                 43
  19 *
  20 * | PIO 0       | c0 | 80 | 0 |
  21 * | PIO 2 | SW2 | d0 | 90 | 4 |
  22 * | PIO 3 | MW1 | e1 | a1 | 9 |
  23 * | PIO 4 | MW2 | e3 | a3 | b |
  24 *
  25 * sitre = word40 & 0x4000; primary
  26 * sitre = word42 & 0x4000; secondary
  27 *
  28 * 44 8421|8421    hdd|hdb
  29 *
  30 * 48 8421         hdd|hdc|hdb|hda udma enabled
  31 *
  32 *    0001         hda
  33 *    0010         hdb
  34 *    0100         hdc
  35 *    1000         hdd
  36 *
  37 * 4a 84|21        hdb|hda
  38 * 4b 84|21        hdd|hdc
  39 *
  40 *    ata-33/82371AB
  41 *    ata-33/82371EB
  42 *    ata-33/82801AB            ata-66/82801AA
  43 *    00|00 udma 0              00|00 reserved
  44 *    01|01 udma 1              01|01 udma 3
  45 *    10|10 udma 2              10|10 udma 4
  46 *    11|11 reserved            11|11 reserved
  47 *
  48 * 54 8421|8421    ata66 drive|ata66 enable
  49 *
  50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
  51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
  52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
  53 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
  54 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
  55 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
  56 *
  57 * Documentation
  58 *      Publically available from Intel web site. Errata documentation
  59 * is also publically available. As an aide to anyone hacking on this
  60 * driver the list of errata that are relevant is below.going back to
  61 * PIIX4. Older device documentation is now a bit tricky to find.
  62 *
  63 * Errata of note:
  64 *
  65 * Unfixable
  66 *      PIIX4    errata #9      - Only on ultra obscure hw
  67 *      ICH3     errata #13     - Not observed to affect real hw
  68 *                                by Intel
  69 *
  70 * Things we must deal with
  71 *      PIIX4   errata #10      - BM IDE hang with non UDMA
  72 *                                (must stop/start dma to recover)
  73 *      440MX   errata #15      - As PIIX4 errata #10
  74 *      PIIX4   errata #15      - Must not read control registers
  75 *                                during a PIO transfer
  76 *      440MX   errata #13      - As PIIX4 errata #15
  77 *      ICH2    errata #21      - DMA mode 0 doesn't work right
  78 *      ICH0/1  errata #55      - As ICH2 errata #21
  79 *      ICH2    spec c #9       - Extra operations needed to handle
  80 *                                drive hotswap [NOT YET SUPPORTED]
  81 *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  82 *                                and must be dword aligned
  83 *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  84 *
  85 * Should have been BIOS fixed:
  86 *      450NX:  errata #19      - DMA hangs on old 450NX
  87 *      450NX:  errata #20      - DMA hangs on old 450NX
  88 *      450NX:  errata #25      - Corruption with DMA on old 450NX
  89 *      ICH3    errata #15      - IDE deadlock under high load
  90 *                                (BIOS must set dev 31 fn 0 bit 23)
  91 *      ICH3    errata #18      - Don't use native mode
  92 */
  93
  94#include <linux/types.h>
  95#include <linux/module.h>
  96#include <linux/kernel.h>
  97#include <linux/ioport.h>
  98#include <linux/pci.h>
  99#include <linux/hdreg.h>
 100#include <linux/ide.h>
 101#include <linux/delay.h>
 102#include <linux/init.h>
 103
 104#include <asm/io.h>
 105
 106static int no_piix_dma;
 107
 108/**
 109 *      piix_set_pio_mode       -       set host controller for PIO mode
 110 *      @drive: drive
 111 *      @pio: PIO mode number
 112 *
 113 *      Set the interface PIO mode based upon the settings done by AMI BIOS.
 114 */
 115
 116static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
 117{
 118        ide_hwif_t *hwif        = HWIF(drive);
 119        struct pci_dev *dev     = hwif->pci_dev;
 120        int is_slave            = drive->dn & 1;
 121        int master_port         = hwif->channel ? 0x42 : 0x40;
 122        int slave_port          = 0x44;
 123        unsigned long flags;
 124        u16 master_data;
 125        u8 slave_data;
 126        static DEFINE_SPINLOCK(tune_lock);
 127        int control = 0;
 128
 129                                     /* ISP  RTC */
 130        static const u8 timings[][2]= {
 131                                        { 0, 0 },
 132                                        { 0, 0 },
 133                                        { 1, 0 },
 134                                        { 2, 1 },
 135                                        { 2, 3 }, };
 136
 137        /*
 138         * Master vs slave is synchronized above us but the slave register is
 139         * shared by the two hwifs so the corner case of two slave timeouts in
 140         * parallel must be locked.
 141         */
 142        spin_lock_irqsave(&tune_lock, flags);
 143        pci_read_config_word(dev, master_port, &master_data);
 144
 145        if (pio > 1)
 146                control |= 1;   /* Programmable timing on */
 147        if (drive->media == ide_disk)
 148                control |= 4;   /* Prefetch, post write */
 149        if (pio > 2)
 150                control |= 2;   /* IORDY */
 151        if (is_slave) {
 152                master_data |=  0x4000;
 153                master_data &= ~0x0070;
 154                if (pio > 1) {
 155                        /* Set PPE, IE and TIME */
 156                        master_data |= control << 4;
 157                }
 158                pci_read_config_byte(dev, slave_port, &slave_data);
 159                slave_data &= hwif->channel ? 0x0f : 0xf0;
 160                slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
 161                               (hwif->channel ? 4 : 0);
 162        } else {
 163                master_data &= ~0x3307;
 164                if (pio > 1) {
 165                        /* enable PPE, IE and TIME */
 166                        master_data |= control;
 167                }
 168                master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
 169        }
 170        pci_write_config_word(dev, master_port, master_data);
 171        if (is_slave)
 172                pci_write_config_byte(dev, slave_port, slave_data);
 173        spin_unlock_irqrestore(&tune_lock, flags);
 174}
 175
 176/**
 177 *      piix_set_dma_mode       -       set host controller for DMA mode
 178 *      @drive: drive
 179 *      @speed: DMA mode
 180 *
 181 *      Set a PIIX host controller to the desired DMA mode.  This involves
 182 *      programming the right timing data into the PCI configuration space.
 183 */
 184
 185static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
 186{
 187        ide_hwif_t *hwif        = HWIF(drive);
 188        struct pci_dev *dev     = hwif->pci_dev;
 189        u8 maslave              = hwif->channel ? 0x42 : 0x40;
 190        int a_speed             = 3 << (drive->dn * 4);
 191        int u_flag              = 1 << drive->dn;
 192        int v_flag              = 0x01 << drive->dn;
 193        int w_flag              = 0x10 << drive->dn;
 194        int u_speed             = 0;
 195        int                     sitre;
 196        u16                     reg4042, reg4a;
 197        u8                      reg48, reg54, reg55;
 198
 199        pci_read_config_word(dev, maslave, &reg4042);
 200        sitre = (reg4042 & 0x4000) ? 1 : 0;
 201        pci_read_config_byte(dev, 0x48, &reg48);
 202        pci_read_config_word(dev, 0x4a, &reg4a);
 203        pci_read_config_byte(dev, 0x54, &reg54);
 204        pci_read_config_byte(dev, 0x55, &reg55);
 205
 206        switch(speed) {
 207                case XFER_UDMA_4:
 208                case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
 209                case XFER_UDMA_5:
 210                case XFER_UDMA_3:
 211                case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
 212                case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
 213                case XFER_MW_DMA_2:
 214                case XFER_MW_DMA_1:
 215                case XFER_SW_DMA_2:     break;
 216                default:                return;
 217        }
 218
 219        if (speed >= XFER_UDMA_0) {
 220                if (!(reg48 & u_flag))
 221                        pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 222                if (speed == XFER_UDMA_5) {
 223                        pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
 224                } else {
 225                        pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 226                }
 227                if ((reg4a & a_speed) != u_speed)
 228                        pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
 229                if (speed > XFER_UDMA_2) {
 230                        if (!(reg54 & v_flag))
 231                                pci_write_config_byte(dev, 0x54, reg54 | v_flag);
 232                } else
 233                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 234        } else {
 235                const u8 mwdma_to_pio[] = { 0, 3, 4 };
 236                u8 pio;
 237
 238                if (reg48 & u_flag)
 239                        pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 240                if (reg4a & a_speed)
 241                        pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 242                if (reg54 & v_flag)
 243                        pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 244                if (reg55 & w_flag)
 245                        pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 246
 247                if (speed >= XFER_MW_DMA_0)
 248                        pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
 249                else
 250                        pio = 2; /* only SWDMA2 is allowed */
 251
 252                piix_set_pio_mode(drive, pio);
 253        }
 254}
 255
 256/**
 257 *      init_chipset_ich        -       set up the ICH chipset
 258 *      @dev: PCI device to set up
 259 *      @name: Name of the device
 260 *
 261 *      Initialize the PCI device as required.  For the ICH this turns
 262 *      out to be nice and simple.
 263 */
 264
 265static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
 266{
 267        u32 extra = 0;
 268
 269        pci_read_config_dword(dev, 0x54, &extra);
 270        pci_write_config_dword(dev, 0x54, extra | 0x400);
 271
 272        return 0;
 273}
 274
 275/**
 276 *      piix_dma_clear_irq      -       clear BMDMA status
 277 *      @drive: IDE drive to clear
 278 *
 279 *      Called from ide_intr() for PIO interrupts
 280 *      to clear BMDMA status as needed by ICHx
 281 */
 282static void piix_dma_clear_irq(ide_drive_t *drive)
 283{
 284        ide_hwif_t *hwif = HWIF(drive);
 285        u8 dma_stat;
 286
 287        /* clear the INTR & ERROR bits */
 288        dma_stat = inb(hwif->dma_status);
 289        /* Should we force the bit as well ? */
 290        outb(dma_stat, hwif->dma_status);
 291}
 292
 293struct ich_laptop {
 294        u16 device;
 295        u16 subvendor;
 296        u16 subdevice;
 297};
 298
 299/*
 300 *      List of laptops that use short cables rather than 80 wire
 301 */
 302
 303static const struct ich_laptop ich_laptop[] = {
 304        /* devid, subvendor, subdev */
 305        { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
 306        { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 307        { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 308        { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 309        { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
 310        { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on Acer Aspire 2023WLMi */
 311        /* end marker */
 312        { 0, }
 313};
 314
 315static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
 316{
 317        struct pci_dev *pdev = hwif->pci_dev;
 318        const struct ich_laptop *lap = &ich_laptop[0];
 319        u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
 320
 321        /* check for specials */
 322        while (lap->device) {
 323                if (lap->device == pdev->device &&
 324                    lap->subvendor == pdev->subsystem_vendor &&
 325                    lap->subdevice == pdev->subsystem_device) {
 326                        return ATA_CBL_PATA40_SHORT;
 327                }
 328                lap++;
 329        }
 330
 331        pci_read_config_byte(pdev, 0x54, &reg54h);
 332
 333        return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 334}
 335
 336/**
 337 *      init_hwif_piix          -       fill in the hwif for the PIIX
 338 *      @hwif: IDE interface
 339 *
 340 *      Set up the ide_hwif_t for the PIIX interface according to the
 341 *      capabilities of the hardware.
 342 */
 343
 344static void __devinit init_hwif_piix(ide_hwif_t *hwif)
 345{
 346        hwif->set_pio_mode = &piix_set_pio_mode;
 347        hwif->set_dma_mode = &piix_set_dma_mode;
 348
 349        if (!hwif->dma_base)
 350                return;
 351
 352        if (hwif->ultra_mask & 0x78) {
 353                if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 354                        hwif->cbl = piix_cable_detect(hwif);
 355        }
 356
 357        if (no_piix_dma)
 358                hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
 359}
 360
 361static void __devinit init_hwif_ich(ide_hwif_t *hwif)
 362{
 363        init_hwif_piix(hwif);
 364
 365        /* ICHx need to clear the BMDMA status for all interrupts */
 366        if (hwif->dma_base)
 367                hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
 368}
 369
 370#ifndef CONFIG_IA64
 371 #define IDE_HFLAGS_PIIX (IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE)
 372#else
 373 #define IDE_HFLAGS_PIIX IDE_HFLAG_BOOTABLE
 374#endif
 375
 376#define DECLARE_PIIX_DEV(name_str, udma) \
 377        {                                               \
 378                .name           = name_str,             \
 379                .init_hwif      = init_hwif_piix,       \
 380                .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 381                .host_flags     = IDE_HFLAGS_PIIX,      \
 382                .pio_mask       = ATA_PIO4,             \
 383                .swdma_mask     = ATA_SWDMA2_ONLY,      \
 384                .mwdma_mask     = ATA_MWDMA12_ONLY,     \
 385                .udma_mask      = udma,                 \
 386        }
 387
 388#define DECLARE_ICH_DEV(name_str, udma) \
 389        { \
 390                .name           = name_str, \
 391                .init_chipset   = init_chipset_ich, \
 392                .init_hwif      = init_hwif_ich, \
 393                .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 394                .host_flags     = IDE_HFLAGS_PIIX, \
 395                .pio_mask       = ATA_PIO4, \
 396                .swdma_mask     = ATA_SWDMA2_ONLY, \
 397                .mwdma_mask     = ATA_MWDMA12_ONLY, \
 398                .udma_mask      = udma, \
 399        }
 400
 401static const struct ide_port_info piix_pci_info[] __devinitdata = {
 402        /*  0 */ DECLARE_PIIX_DEV("PIIXa",      0x00),  /* no udma */
 403        /*  1 */ DECLARE_PIIX_DEV("PIIXb",      0x00),  /* no udma */
 404
 405        /*  2 */
 406        {       /*
 407                 * MPIIX actually has only a single IDE channel mapped to
 408                 * the primary or secondary ports depending on the value
 409                 * of the bit 14 of the IDETIM register at offset 0x6c
 410                 */
 411                .name           = "MPIIX",
 412                .enablebits     = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
 413                .host_flags     = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
 414                                  IDE_HFLAGS_PIIX,
 415                .pio_mask       = ATA_PIO4,
 416                /* This is a painful system best to let it self tune for now */
 417        },
 418
 419        /*  3 */ DECLARE_PIIX_DEV("PIIX3",      0x00),  /* no udma */
 420        /*  4 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 421        /*  5 */ DECLARE_ICH_DEV("ICH0",        ATA_UDMA2),
 422        /*  6 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 423        /*  7 */ DECLARE_ICH_DEV("ICH",         ATA_UDMA4),
 424        /*  8 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA4),
 425        /*  9 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 426        /* 10 */ DECLARE_ICH_DEV("ICH2",        ATA_UDMA5),
 427        /* 11 */ DECLARE_ICH_DEV("ICH2M",       ATA_UDMA5),
 428        /* 12 */ DECLARE_ICH_DEV("ICH3M",       ATA_UDMA5),
 429        /* 13 */ DECLARE_ICH_DEV("ICH3",        ATA_UDMA5),
 430        /* 14 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 431        /* 15 */ DECLARE_ICH_DEV("ICH5",        ATA_UDMA5),
 432        /* 16 */ DECLARE_ICH_DEV("C-ICH",       ATA_UDMA5),
 433        /* 17 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 434        /* 18 */ DECLARE_ICH_DEV("ICH5-SATA",   ATA_UDMA5),
 435        /* 19 */ DECLARE_ICH_DEV("ICH5",        ATA_UDMA5),
 436        /* 20 */ DECLARE_ICH_DEV("ICH6",        ATA_UDMA5),
 437        /* 21 */ DECLARE_ICH_DEV("ICH7",        ATA_UDMA5),
 438        /* 22 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 439        /* 23 */ DECLARE_ICH_DEV("ESB2",        ATA_UDMA5),
 440        /* 24 */ DECLARE_ICH_DEV("ICH8M",       ATA_UDMA5),
 441};
 442
 443/**
 444 *      piix_init_one   -       called when a PIIX is found
 445 *      @dev: the piix device
 446 *      @id: the matching pci id
 447 *
 448 *      Called when the PCI registration layer (or the IDE initialization)
 449 *      finds a device matching our IDE device tables.
 450 */
 451 
 452static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 453{
 454        return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
 455}
 456
 457/**
 458 *      piix_check_450nx        -       Check for problem 450NX setup
 459 *      
 460 *      Check for the present of 450NX errata #19 and errata #25. If
 461 *      they are found, disable use of DMA IDE
 462 */
 463
 464static void __devinit piix_check_450nx(void)
 465{
 466        struct pci_dev *pdev = NULL;
 467        u16 cfg;
 468        while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
 469        {
 470                /* Look for 450NX PXB. Check for problem configurations
 471                   A PCI quirk checks bit 6 already */
 472                pci_read_config_word(pdev, 0x41, &cfg);
 473                /* Only on the original revision: IDE DMA can hang */
 474                if (pdev->revision == 0x00)
 475                        no_piix_dma = 1;
 476                /* On all revisions below 5 PXB bus lock must be disabled for IDE */
 477                else if (cfg & (1<<14) && pdev->revision < 5)
 478                        no_piix_dma = 2;
 479        }
 480        if(no_piix_dma)
 481                printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
 482        if(no_piix_dma == 2)
 483                printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
 484}               
 485
 486static const struct pci_device_id piix_pci_tbl[] = {
 487        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),   0 },
 488        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),   1 },
 489        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),     2 },
 490        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),   3 },
 491        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),     4 },
 492        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),   5 },
 493        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),   6 },
 494        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),   7 },
 495        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),   8 },
 496        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),     9 },
 497        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  10 },
 498        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  11 },
 499        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
 500        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
 501        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
 502        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
 503        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  16 },
 504        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
 505#ifdef CONFIG_BLK_DEV_IDE_SATA
 506        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  18 },
 507#endif
 508        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      19 },
 509        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    20 },
 510        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    21 },
 511        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  22 },
 512        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    23 },
 513        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     24 },
 514        { 0, },
 515};
 516MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 517
 518static struct pci_driver driver = {
 519        .name           = "PIIX_IDE",
 520        .id_table       = piix_pci_tbl,
 521        .probe          = piix_init_one,
 522};
 523
 524static int __init piix_ide_init(void)
 525{
 526        piix_check_450nx();
 527        return ide_pci_register_driver(&driver);
 528}
 529
 530module_init(piix_ide_init);
 531
 532MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
 533MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
 534MODULE_LICENSE("GPL");
 535
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