linux/drivers/ide/pci/hpt366.c
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   1/*
   2 * linux/drivers/ide/pci/hpt366.c               Version 1.22    Dec 4, 2007
   3 *
   4 * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5 * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6 * Portions Copyright (C) 2003          Red Hat Inc
   7 * Portions Copyright (C) 2007          Bartlomiej Zolnierkiewicz
   8 * Portions Copyright (C) 2005-2007     MontaVista Software, Inc.
   9 *
  10 * Thanks to HighPoint Technologies for their assistance, and hardware.
  11 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  12 * donation of an ABit BP6 mainboard, processor, and memory acellerated
  13 * development and support.
  14 *
  15 *
  16 * HighPoint has its own drivers (open source except for the RAID part)
  17 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  18 * This may be useful to anyone wanting to work on this driver, however  do not
  19 * trust  them too much since the code tends to become less and less meaningful
  20 * as the time passes... :-/
  21 *
  22 * Note that final HPT370 support was done by force extraction of GPL.
  23 *
  24 * - add function for getting/setting power status of drive
  25 * - the HPT370's state machine can get confused. reset it before each dma 
  26 *   xfer to prevent that from happening.
  27 * - reset state engine whenever we get an error.
  28 * - check for busmaster state at end of dma. 
  29 * - use new highpoint timings.
  30 * - detect bus speed using highpoint register.
  31 * - use pll if we don't have a clock table. added a 66MHz table that's
  32 *   just 2x the 33MHz table.
  33 * - removed turnaround. NOTE: we never want to switch between pll and
  34 *   pci clocks as the chip can glitch in those cases. the highpoint
  35 *   approved workaround slows everything down too much to be useful. in
  36 *   addition, we would have to serialize access to each chip.
  37 *      Adrian Sun <a.sun@sun.com>
  38 *
  39 * add drive timings for 66MHz PCI bus,
  40 * fix ATA Cable signal detection, fix incorrect /proc info
  41 * add /proc display for per-drive PIO/DMA/UDMA mode and
  42 * per-channel ATA-33/66 Cable detect.
  43 *      Duncan Laurie <void@sun.com>
  44 *
  45 * fixup /proc output for multiple controllers
  46 *      Tim Hockin <thockin@sun.com>
  47 *
  48 * On hpt366: 
  49 * Reset the hpt366 on error, reset on dma
  50 * Fix disabling Fast Interrupt hpt366.
  51 *      Mike Waychison <crlf@sun.com>
  52 *
  53 * Added support for 372N clocking and clock switching. The 372N needs
  54 * different clocks on read/write. This requires overloading rw_disk and
  55 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  56 * keeping me sane. 
  57 *              Alan Cox <alan@redhat.com>
  58 *
  59 * - fix the clock turnaround code: it was writing to the wrong ports when
  60 *   called for the secondary channel, caching the current clock mode per-
  61 *   channel caused the cached register value to get out of sync with the
  62 *   actual one, the channels weren't serialized, the turnaround shouldn't
  63 *   be done on 66 MHz PCI bus
  64 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
  65 *   does not allow for this speed anyway
  66 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
  67 *   their primary channel is kind of virtual, it isn't tied to any pins)
  68 * - fix/remove bad/unused timing tables and use one set of tables for the whole
  69 *   HPT37x chip family; save space by introducing the separate transfer mode
  70 *   table in which the mode lookup is done
  71 * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  72 *   the wrong PCI frequency since DPLL has already been calibrated by BIOS;
  73 *   read it only from the function 0 of HPT374 chips
  74 * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  75 *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  76 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  77 *   they tamper with its fields
  78 * - pass  to the init_setup handlers a copy of the ide_pci_device_t structure
  79 *   since they may tamper with its fields
  80 * - prefix the driver startup messages with the real chip name
  81 * - claim the extra 240 bytes of I/O space for all chips
  82 * - optimize the UltraDMA filtering and the drive list lookup code
  83 * - use pci_get_slot() to get to the function 1 of HPT36x/374
  84 * - cache offset of the channel's misc. control registers (MCRs) being used
  85 *   throughout the driver
  86 * - only touch the relevant MCR when detecting the cable type on HPT374's
  87 *   function 1
  88 * - rename all the register related variables consistently
  89 * - move all the interrupt twiddling code from the speedproc handlers into
  90 *   init_hwif_hpt366(), also grouping all the DMA related code together there
  91 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
  92 *   separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
  93 *   when setting an UltraDMA mode
  94 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
  95 *   the best possible one
  96 * - clean up DMA timeout handling for HPT370
  97 * - switch to using the enumeration type to differ between the numerous chip
  98 *   variants, matching PCI device/revision ID with the chip type early, at the
  99 *   init_setup stage
 100 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
 101 *   stop duplicating it for each channel by storing the pointer in the pci_dev
 102 *   structure: first, at the init_setup stage, point it to a static "template"
 103 *   with only the chip type and its specific base DPLL frequency, the highest
 104 *   UltraDMA mode, and the chip settings table pointer filled,  then, at the
 105 *   init_chipset stage, allocate per-chip instance  and fill it with the rest
 106 *   of the necessary information
 107 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
 108 *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
 109 *   frequency
 110 * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
 111 *   anything  newer than HPT370/A (except HPT374 that is not capable of this
 112 *   mode according to the manual)
 113 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
 114 *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
 115 *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
 116 *   the register setting lists into the table indexed by the clock selected
 117 * - set the correct hwif->ultra_mask for each individual chip
 118 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
 119 *      Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
 120 */
 121
 122#include <linux/types.h>
 123#include <linux/module.h>
 124#include <linux/kernel.h>
 125#include <linux/delay.h>
 126#include <linux/timer.h>
 127#include <linux/mm.h>
 128#include <linux/ioport.h>
 129#include <linux/blkdev.h>
 130#include <linux/hdreg.h>
 131
 132#include <linux/interrupt.h>
 133#include <linux/pci.h>
 134#include <linux/init.h>
 135#include <linux/ide.h>
 136
 137#include <asm/uaccess.h>
 138#include <asm/io.h>
 139#include <asm/irq.h>
 140
 141/* various tuning parameters */
 142#define HPT_RESET_STATE_ENGINE
 143#undef  HPT_DELAY_INTERRUPT
 144#define HPT_SERIALIZE_IO        0
 145
 146static const char *quirk_drives[] = {
 147        "QUANTUM FIREBALLlct08 08",
 148        "QUANTUM FIREBALLP KA6.4",
 149        "QUANTUM FIREBALLP LM20.4",
 150        "QUANTUM FIREBALLP LM20.5",
 151        NULL
 152};
 153
 154static const char *bad_ata100_5[] = {
 155        "IBM-DTLA-307075",
 156        "IBM-DTLA-307060",
 157        "IBM-DTLA-307045",
 158        "IBM-DTLA-307030",
 159        "IBM-DTLA-307020",
 160        "IBM-DTLA-307015",
 161        "IBM-DTLA-305040",
 162        "IBM-DTLA-305030",
 163        "IBM-DTLA-305020",
 164        "IC35L010AVER07-0",
 165        "IC35L020AVER07-0",
 166        "IC35L030AVER07-0",
 167        "IC35L040AVER07-0",
 168        "IC35L060AVER07-0",
 169        "WDC AC310200R",
 170        NULL
 171};
 172
 173static const char *bad_ata66_4[] = {
 174        "IBM-DTLA-307075",
 175        "IBM-DTLA-307060",
 176        "IBM-DTLA-307045",
 177        "IBM-DTLA-307030",
 178        "IBM-DTLA-307020",
 179        "IBM-DTLA-307015",
 180        "IBM-DTLA-305040",
 181        "IBM-DTLA-305030",
 182        "IBM-DTLA-305020",
 183        "IC35L010AVER07-0",
 184        "IC35L020AVER07-0",
 185        "IC35L030AVER07-0",
 186        "IC35L040AVER07-0",
 187        "IC35L060AVER07-0",
 188        "WDC AC310200R",
 189        "MAXTOR STM3320620A",
 190        NULL
 191};
 192
 193static const char *bad_ata66_3[] = {
 194        "WDC AC310200R",
 195        NULL
 196};
 197
 198static const char *bad_ata33[] = {
 199        "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 200        "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 201        "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 202        "Maxtor 90510D4",
 203        "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 204        "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 205        "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 206        NULL
 207};
 208
 209static u8 xfer_speeds[] = {
 210        XFER_UDMA_6,
 211        XFER_UDMA_5,
 212        XFER_UDMA_4,
 213        XFER_UDMA_3,
 214        XFER_UDMA_2,
 215        XFER_UDMA_1,
 216        XFER_UDMA_0,
 217
 218        XFER_MW_DMA_2,
 219        XFER_MW_DMA_1,
 220        XFER_MW_DMA_0,
 221
 222        XFER_PIO_4,
 223        XFER_PIO_3,
 224        XFER_PIO_2,
 225        XFER_PIO_1,
 226        XFER_PIO_0
 227};
 228
 229/* Key for bus clock timings
 230 * 36x   37x
 231 * bits  bits
 232 * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 233 *              cycles = value + 1
 234 * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 235 *              cycles = value + 1
 236 * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 237 *              register access.
 238 * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 239 *              register access.
 240 * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 241 * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 242 * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 243 *              MW DMA xfer.
 244 * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 245 *              task file register access.
 246 * 28    28     UDMA enable.
 247 * 29    29     DMA  enable.
 248 * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 249 *              PIO xfer.
 250 * 31    31     FIFO enable.
 251 */
 252
 253static u32 forty_base_hpt36x[] = {
 254        /* XFER_UDMA_6 */       0x900fd943,
 255        /* XFER_UDMA_5 */       0x900fd943,
 256        /* XFER_UDMA_4 */       0x900fd943,
 257        /* XFER_UDMA_3 */       0x900ad943,
 258        /* XFER_UDMA_2 */       0x900bd943,
 259        /* XFER_UDMA_1 */       0x9008d943,
 260        /* XFER_UDMA_0 */       0x9008d943,
 261
 262        /* XFER_MW_DMA_2 */     0xa008d943,
 263        /* XFER_MW_DMA_1 */     0xa010d955,
 264        /* XFER_MW_DMA_0 */     0xa010d9fc,
 265
 266        /* XFER_PIO_4 */        0xc008d963,
 267        /* XFER_PIO_3 */        0xc010d974,
 268        /* XFER_PIO_2 */        0xc010d997,
 269        /* XFER_PIO_1 */        0xc010d9c7,
 270        /* XFER_PIO_0 */        0xc018d9d9
 271};
 272
 273static u32 thirty_three_base_hpt36x[] = {
 274        /* XFER_UDMA_6 */       0x90c9a731,
 275        /* XFER_UDMA_5 */       0x90c9a731,
 276        /* XFER_UDMA_4 */       0x90c9a731,
 277        /* XFER_UDMA_3 */       0x90cfa731,
 278        /* XFER_UDMA_2 */       0x90caa731,
 279        /* XFER_UDMA_1 */       0x90cba731,
 280        /* XFER_UDMA_0 */       0x90c8a731,
 281
 282        /* XFER_MW_DMA_2 */     0xa0c8a731,
 283        /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 284        /* XFER_MW_DMA_0 */     0xa0c8a797,
 285
 286        /* XFER_PIO_4 */        0xc0c8a731,
 287        /* XFER_PIO_3 */        0xc0c8a742,
 288        /* XFER_PIO_2 */        0xc0d0a753,
 289        /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 290        /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 291};
 292
 293static u32 twenty_five_base_hpt36x[] = {
 294        /* XFER_UDMA_6 */       0x90c98521,
 295        /* XFER_UDMA_5 */       0x90c98521,
 296        /* XFER_UDMA_4 */       0x90c98521,
 297        /* XFER_UDMA_3 */       0x90cf8521,
 298        /* XFER_UDMA_2 */       0x90cf8521,
 299        /* XFER_UDMA_1 */       0x90cb8521,
 300        /* XFER_UDMA_0 */       0x90cb8521,
 301
 302        /* XFER_MW_DMA_2 */     0xa0ca8521,
 303        /* XFER_MW_DMA_1 */     0xa0ca8532,
 304        /* XFER_MW_DMA_0 */     0xa0ca8575,
 305
 306        /* XFER_PIO_4 */        0xc0ca8521,
 307        /* XFER_PIO_3 */        0xc0ca8532,
 308        /* XFER_PIO_2 */        0xc0ca8542,
 309        /* XFER_PIO_1 */        0xc0d08572,
 310        /* XFER_PIO_0 */        0xc0d08585
 311};
 312
 313#if 0
 314/* These are the timing tables from the HighPoint open source drivers... */
 315static u32 thirty_three_base_hpt37x[] = {
 316        /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 317        /* XFER_UDMA_5 */       0x12446231,
 318        /* XFER_UDMA_4 */       0x12446231,
 319        /* XFER_UDMA_3 */       0x126c6231,
 320        /* XFER_UDMA_2 */       0x12486231,
 321        /* XFER_UDMA_1 */       0x124c6233,
 322        /* XFER_UDMA_0 */       0x12506297,
 323
 324        /* XFER_MW_DMA_2 */     0x22406c31,
 325        /* XFER_MW_DMA_1 */     0x22406c33,
 326        /* XFER_MW_DMA_0 */     0x22406c97,
 327
 328        /* XFER_PIO_4 */        0x06414e31,
 329        /* XFER_PIO_3 */        0x06414e42,
 330        /* XFER_PIO_2 */        0x06414e53,
 331        /* XFER_PIO_1 */        0x06814e93,
 332        /* XFER_PIO_0 */        0x06814ea7
 333};
 334
 335static u32 fifty_base_hpt37x[] = {
 336        /* XFER_UDMA_6 */       0x12848242,
 337        /* XFER_UDMA_5 */       0x12848242,
 338        /* XFER_UDMA_4 */       0x12ac8242,
 339        /* XFER_UDMA_3 */       0x128c8242,
 340        /* XFER_UDMA_2 */       0x120c8242,
 341        /* XFER_UDMA_1 */       0x12148254,
 342        /* XFER_UDMA_0 */       0x121882ea,
 343
 344        /* XFER_MW_DMA_2 */     0x22808242,
 345        /* XFER_MW_DMA_1 */     0x22808254,
 346        /* XFER_MW_DMA_0 */     0x228082ea,
 347
 348        /* XFER_PIO_4 */        0x0a81f442,
 349        /* XFER_PIO_3 */        0x0a81f443,
 350        /* XFER_PIO_2 */        0x0a81f454,
 351        /* XFER_PIO_1 */        0x0ac1f465,
 352        /* XFER_PIO_0 */        0x0ac1f48a
 353};
 354
 355static u32 sixty_six_base_hpt37x[] = {
 356        /* XFER_UDMA_6 */       0x1c869c62,
 357        /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 358        /* XFER_UDMA_4 */       0x1c8a9c62,
 359        /* XFER_UDMA_3 */       0x1c8e9c62,
 360        /* XFER_UDMA_2 */       0x1c929c62,
 361        /* XFER_UDMA_1 */       0x1c9a9c62,
 362        /* XFER_UDMA_0 */       0x1c829c62,
 363
 364        /* XFER_MW_DMA_2 */     0x2c829c62,
 365        /* XFER_MW_DMA_1 */     0x2c829c66,
 366        /* XFER_MW_DMA_0 */     0x2c829d2e,
 367
 368        /* XFER_PIO_4 */        0x0c829c62,
 369        /* XFER_PIO_3 */        0x0c829c84,
 370        /* XFER_PIO_2 */        0x0c829ca6,
 371        /* XFER_PIO_1 */        0x0d029d26,
 372        /* XFER_PIO_0 */        0x0d029d5e
 373};
 374#else
 375/*
 376 * The following are the new timing tables with PIO mode data/taskfile transfer
 377 * overclocking fixed...
 378 */
 379
 380/* This table is taken from the HPT370 data manual rev. 1.02 */
 381static u32 thirty_three_base_hpt37x[] = {
 382        /* XFER_UDMA_6 */       0x16455031,     /* 0x16655031 ?? */
 383        /* XFER_UDMA_5 */       0x16455031,
 384        /* XFER_UDMA_4 */       0x16455031,
 385        /* XFER_UDMA_3 */       0x166d5031,
 386        /* XFER_UDMA_2 */       0x16495031,
 387        /* XFER_UDMA_1 */       0x164d5033,
 388        /* XFER_UDMA_0 */       0x16515097,
 389
 390        /* XFER_MW_DMA_2 */     0x26515031,
 391        /* XFER_MW_DMA_1 */     0x26515033,
 392        /* XFER_MW_DMA_0 */     0x26515097,
 393
 394        /* XFER_PIO_4 */        0x06515021,
 395        /* XFER_PIO_3 */        0x06515022,
 396        /* XFER_PIO_2 */        0x06515033,
 397        /* XFER_PIO_1 */        0x06915065,
 398        /* XFER_PIO_0 */        0x06d1508a
 399};
 400
 401static u32 fifty_base_hpt37x[] = {
 402        /* XFER_UDMA_6 */       0x1a861842,
 403        /* XFER_UDMA_5 */       0x1a861842,
 404        /* XFER_UDMA_4 */       0x1aae1842,
 405        /* XFER_UDMA_3 */       0x1a8e1842,
 406        /* XFER_UDMA_2 */       0x1a0e1842,
 407        /* XFER_UDMA_1 */       0x1a161854,
 408        /* XFER_UDMA_0 */       0x1a1a18ea,
 409
 410        /* XFER_MW_DMA_2 */     0x2a821842,
 411        /* XFER_MW_DMA_1 */     0x2a821854,
 412        /* XFER_MW_DMA_0 */     0x2a8218ea,
 413
 414        /* XFER_PIO_4 */        0x0a821842,
 415        /* XFER_PIO_3 */        0x0a821843,
 416        /* XFER_PIO_2 */        0x0a821855,
 417        /* XFER_PIO_1 */        0x0ac218a8,
 418        /* XFER_PIO_0 */        0x0b02190c
 419};
 420
 421static u32 sixty_six_base_hpt37x[] = {
 422        /* XFER_UDMA_6 */       0x1c86fe62,
 423        /* XFER_UDMA_5 */       0x1caefe62,     /* 0x1c8afe62 */
 424        /* XFER_UDMA_4 */       0x1c8afe62,
 425        /* XFER_UDMA_3 */       0x1c8efe62,
 426        /* XFER_UDMA_2 */       0x1c92fe62,
 427        /* XFER_UDMA_1 */       0x1c9afe62,
 428        /* XFER_UDMA_0 */       0x1c82fe62,
 429
 430        /* XFER_MW_DMA_2 */     0x2c82fe62,
 431        /* XFER_MW_DMA_1 */     0x2c82fe66,
 432        /* XFER_MW_DMA_0 */     0x2c82ff2e,
 433
 434        /* XFER_PIO_4 */        0x0c82fe62,
 435        /* XFER_PIO_3 */        0x0c82fe84,
 436        /* XFER_PIO_2 */        0x0c82fea6,
 437        /* XFER_PIO_1 */        0x0d02ff26,
 438        /* XFER_PIO_0 */        0x0d42ff7f
 439};
 440#endif
 441
 442#define HPT366_DEBUG_DRIVE_INFO         0
 443#define HPT371_ALLOW_ATA133_6           1
 444#define HPT302_ALLOW_ATA133_6           1
 445#define HPT372_ALLOW_ATA133_6           1
 446#define HPT370_ALLOW_ATA100_5           0
 447#define HPT366_ALLOW_ATA66_4            1
 448#define HPT366_ALLOW_ATA66_3            1
 449#define HPT366_MAX_DEVS                 8
 450
 451/* Supported ATA clock frequencies */
 452enum ata_clock {
 453        ATA_CLOCK_25MHZ,
 454        ATA_CLOCK_33MHZ,
 455        ATA_CLOCK_40MHZ,
 456        ATA_CLOCK_50MHZ,
 457        ATA_CLOCK_66MHZ,
 458        NUM_ATA_CLOCKS
 459};
 460
 461/*
 462 *      Hold all the HighPoint chip information in one place.
 463 */
 464
 465struct hpt_info {
 466        char *chip_name;        /* Chip name */
 467        u8 chip_type;           /* Chip type */
 468        u8 udma_mask;           /* Allowed UltraDMA modes mask. */
 469        u8 dpll_clk;            /* DPLL clock in MHz */
 470        u8 pci_clk;             /* PCI  clock in MHz */
 471        u32 **settings;         /* Chipset settings table */
 472};
 473
 474/* Supported HighPoint chips */
 475enum {
 476        HPT36x,
 477        HPT370,
 478        HPT370A,
 479        HPT374,
 480        HPT372,
 481        HPT372A,
 482        HPT302,
 483        HPT371,
 484        HPT372N,
 485        HPT302N,
 486        HPT371N
 487};
 488
 489static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
 490        twenty_five_base_hpt36x,
 491        thirty_three_base_hpt36x,
 492        forty_base_hpt36x,
 493        NULL,
 494        NULL
 495};
 496
 497static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
 498        NULL,
 499        thirty_three_base_hpt37x,
 500        NULL,
 501        fifty_base_hpt37x,
 502        sixty_six_base_hpt37x
 503};
 504
 505static const struct hpt_info hpt36x __devinitdata = {
 506        .chip_name      = "HPT36x",
 507        .chip_type      = HPT36x,
 508        .udma_mask      = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
 509        .dpll_clk       = 0,    /* no DPLL */
 510        .settings       = hpt36x_settings
 511};
 512
 513static const struct hpt_info hpt370 __devinitdata = {
 514        .chip_name      = "HPT370",
 515        .chip_type      = HPT370,
 516        .udma_mask      = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
 517        .dpll_clk       = 48,
 518        .settings       = hpt37x_settings
 519};
 520
 521static const struct hpt_info hpt370a __devinitdata = {
 522        .chip_name      = "HPT370A",
 523        .chip_type      = HPT370A,
 524        .udma_mask      = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
 525        .dpll_clk       = 48,
 526        .settings       = hpt37x_settings
 527};
 528
 529static const struct hpt_info hpt374 __devinitdata = {
 530        .chip_name      = "HPT374",
 531        .chip_type      = HPT374,
 532        .udma_mask      = ATA_UDMA5,
 533        .dpll_clk       = 48,
 534        .settings       = hpt37x_settings
 535};
 536
 537static const struct hpt_info hpt372 __devinitdata = {
 538        .chip_name      = "HPT372",
 539        .chip_type      = HPT372,
 540        .udma_mask      = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 541        .dpll_clk       = 55,
 542        .settings       = hpt37x_settings
 543};
 544
 545static const struct hpt_info hpt372a __devinitdata = {
 546        .chip_name      = "HPT372A",
 547        .chip_type      = HPT372A,
 548        .udma_mask      = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 549        .dpll_clk       = 66,
 550        .settings       = hpt37x_settings
 551};
 552
 553static const struct hpt_info hpt302 __devinitdata = {
 554        .chip_name      = "HPT302",
 555        .chip_type      = HPT302,
 556        .udma_mask      = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 557        .dpll_clk       = 66,
 558        .settings       = hpt37x_settings
 559};
 560
 561static const struct hpt_info hpt371 __devinitdata = {
 562        .chip_name      = "HPT371",
 563        .chip_type      = HPT371,
 564        .udma_mask      = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 565        .dpll_clk       = 66,
 566        .settings       = hpt37x_settings
 567};
 568
 569static const struct hpt_info hpt372n __devinitdata = {
 570        .chip_name      = "HPT372N",
 571        .chip_type      = HPT372N,
 572        .udma_mask      = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 573        .dpll_clk       = 77,
 574        .settings       = hpt37x_settings
 575};
 576
 577static const struct hpt_info hpt302n __devinitdata = {
 578        .chip_name      = "HPT302N",
 579        .chip_type      = HPT302N,
 580        .udma_mask      = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 581        .dpll_clk       = 77,
 582        .settings       = hpt37x_settings
 583};
 584
 585static const struct hpt_info hpt371n __devinitdata = {
 586        .chip_name      = "HPT371N",
 587        .chip_type      = HPT371N,
 588        .udma_mask      = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 589        .dpll_clk       = 77,
 590        .settings       = hpt37x_settings
 591};
 592
 593static int check_in_drive_list(ide_drive_t *drive, const char **list)
 594{
 595        struct hd_driveid *id = drive->id;
 596
 597        while (*list)
 598                if (!strcmp(*list++,id->model))
 599                        return 1;
 600        return 0;
 601}
 602
 603/*
 604 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
 605 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
 606 */
 607
 608static u8 hpt3xx_udma_filter(ide_drive_t *drive)
 609{
 610        ide_hwif_t *hwif        = HWIF(drive);
 611        struct hpt_info *info   = pci_get_drvdata(hwif->pci_dev);
 612        u8 mask                 = hwif->ultra_mask;
 613
 614        switch (info->chip_type) {
 615        case HPT36x:
 616                if (!HPT366_ALLOW_ATA66_4 ||
 617                    check_in_drive_list(drive, bad_ata66_4))
 618                        mask = ATA_UDMA3;
 619
 620                if (!HPT366_ALLOW_ATA66_3 ||
 621                    check_in_drive_list(drive, bad_ata66_3))
 622                        mask = ATA_UDMA2;
 623                break;
 624        case HPT370:
 625                if (!HPT370_ALLOW_ATA100_5 ||
 626                    check_in_drive_list(drive, bad_ata100_5))
 627                        mask = ATA_UDMA4;
 628                break;
 629        case HPT370A:
 630                if (!HPT370_ALLOW_ATA100_5 ||
 631                    check_in_drive_list(drive, bad_ata100_5))
 632                        return ATA_UDMA4;
 633        case HPT372 :
 634        case HPT372A:
 635        case HPT372N:
 636        case HPT374 :
 637                if (ide_dev_is_sata(drive->id))
 638                        mask &= ~0x0e;
 639                /* Fall thru */
 640        default:
 641                return mask;
 642        }
 643
 644        return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
 645}
 646
 647static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
 648{
 649        ide_hwif_t *hwif        = HWIF(drive);
 650        struct hpt_info *info   = pci_get_drvdata(hwif->pci_dev);
 651
 652        switch (info->chip_type) {
 653        case HPT372 :
 654        case HPT372A:
 655        case HPT372N:
 656        case HPT374 :
 657                if (ide_dev_is_sata(drive->id))
 658                        return 0x00;
 659                /* Fall thru */
 660        default:
 661                return 0x07;
 662        }
 663}
 664
 665static u32 get_speed_setting(u8 speed, struct hpt_info *info)
 666{
 667        int i;
 668
 669        /*
 670         * Lookup the transfer mode table to get the index into
 671         * the timing table.
 672         *
 673         * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 674         */
 675        for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 676                if (xfer_speeds[i] == speed)
 677                        break;
 678        /*
 679         * NOTE: info->settings only points to the pointer
 680         * to the list of the actual register values
 681         */
 682        return (*info->settings)[i];
 683}
 684
 685static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
 686{
 687        ide_hwif_t *hwif        = HWIF(drive);
 688        struct pci_dev  *dev    = hwif->pci_dev;
 689        struct hpt_info *info   = pci_get_drvdata(dev);
 690        u8  itr_addr            = drive->dn ? 0x44 : 0x40;
 691        u32 old_itr             = 0;
 692        u32 itr_mask, new_itr;
 693
 694        itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
 695                  (speed < XFER_UDMA_0   ? 0xc0070000 : 0xc03800ff);
 696
 697        new_itr = get_speed_setting(speed, info);
 698
 699        /*
 700         * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
 701         * to avoid problems handling I/O errors later
 702         */
 703        pci_read_config_dword(dev, itr_addr, &old_itr);
 704        new_itr  = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 705        new_itr &= ~0xc0000000;
 706
 707        pci_write_config_dword(dev, itr_addr, new_itr);
 708}
 709
 710static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
 711{
 712        ide_hwif_t *hwif        = HWIF(drive);
 713        struct pci_dev  *dev    = hwif->pci_dev;
 714        struct hpt_info *info   = pci_get_drvdata(dev);
 715        u8  itr_addr            = 0x40 + (drive->dn * 4);
 716        u32 old_itr             = 0;
 717        u32 itr_mask, new_itr;
 718
 719        itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
 720                  (speed < XFER_UDMA_0   ? 0xc03c0000 : 0xc1c001ff);
 721
 722        new_itr = get_speed_setting(speed, info);
 723
 724        pci_read_config_dword(dev, itr_addr, &old_itr);
 725        new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 726        
 727        if (speed < XFER_MW_DMA_0)
 728                new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 729        pci_write_config_dword(dev, itr_addr, new_itr);
 730}
 731
 732static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
 733{
 734        ide_hwif_t *hwif        = HWIF(drive);
 735        struct hpt_info *info   = pci_get_drvdata(hwif->pci_dev);
 736
 737        if (info->chip_type >= HPT370)
 738                hpt37x_set_mode(drive, speed);
 739        else    /* hpt368: hpt_minimum_revision(dev, 2) */
 740                hpt36x_set_mode(drive, speed);
 741}
 742
 743static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 744{
 745        hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
 746}
 747
 748static int hpt3xx_quirkproc(ide_drive_t *drive)
 749{
 750        struct hd_driveid *id   = drive->id;
 751        const  char **list      = quirk_drives;
 752
 753        while (*list)
 754                if (strstr(id->model, *list++))
 755                        return 1;
 756        return 0;
 757}
 758
 759static void hpt3xx_intrproc(ide_drive_t *drive)
 760{
 761        if (drive->quirk_list)
 762                return;
 763
 764        /* drives in the quirk_list may not like intr setups/cleanups */
 765        outb(drive->ctl | 2, IDE_CONTROL_REG);
 766}
 767
 768static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
 769{
 770        ide_hwif_t *hwif        = HWIF(drive);
 771        struct pci_dev  *dev    = hwif->pci_dev;
 772        struct hpt_info *info   = pci_get_drvdata(dev);
 773
 774        if (drive->quirk_list) {
 775                if (info->chip_type >= HPT370) {
 776                        u8 scr1 = 0;
 777
 778                        pci_read_config_byte(dev, 0x5a, &scr1);
 779                        if (((scr1 & 0x10) >> 4) != mask) {
 780                                if (mask)
 781                                        scr1 |=  0x10;
 782                                else
 783                                        scr1 &= ~0x10;
 784                                pci_write_config_byte(dev, 0x5a, scr1);
 785                        }
 786                } else {
 787                        if (mask)
 788                                disable_irq(hwif->irq);
 789                        else
 790                                enable_irq (hwif->irq);
 791                }
 792        } else
 793                outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 794                     IDE_CONTROL_REG);
 795}
 796
 797/*
 798 * This is specific to the HPT366 UDMA chipset
 799 * by HighPoint|Triones Technologies, Inc.
 800 */
 801static void hpt366_dma_lost_irq(ide_drive_t *drive)
 802{
 803        struct pci_dev *dev = HWIF(drive)->pci_dev;
 804        u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
 805
 806        pci_read_config_byte(dev, 0x50, &mcr1);
 807        pci_read_config_byte(dev, 0x52, &mcr3);
 808        pci_read_config_byte(dev, 0x5a, &scr1);
 809        printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
 810                drive->name, __FUNCTION__, mcr1, mcr3, scr1);
 811        if (scr1 & 0x10)
 812                pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 813        ide_dma_lost_irq(drive);
 814}
 815
 816static void hpt370_clear_engine(ide_drive_t *drive)
 817{
 818        ide_hwif_t *hwif = HWIF(drive);
 819
 820        pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
 821        udelay(10);
 822}
 823
 824static void hpt370_irq_timeout(ide_drive_t *drive)
 825{
 826        ide_hwif_t *hwif        = HWIF(drive);
 827        u16 bfifo               = 0;
 828        u8  dma_cmd;
 829
 830        pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 831        printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
 832
 833        /* get DMA command mode */
 834        dma_cmd = inb(hwif->dma_command);
 835        /* stop DMA */
 836        outb(dma_cmd & ~0x1, hwif->dma_command);
 837        hpt370_clear_engine(drive);
 838}
 839
 840static void hpt370_ide_dma_start(ide_drive_t *drive)
 841{
 842#ifdef HPT_RESET_STATE_ENGINE
 843        hpt370_clear_engine(drive);
 844#endif
 845        ide_dma_start(drive);
 846}
 847
 848static int hpt370_ide_dma_end(ide_drive_t *drive)
 849{
 850        ide_hwif_t *hwif        = HWIF(drive);
 851        u8  dma_stat            = inb(hwif->dma_status);
 852
 853        if (dma_stat & 0x01) {
 854                /* wait a little */
 855                udelay(20);
 856                dma_stat = inb(hwif->dma_status);
 857                if (dma_stat & 0x01)
 858                        hpt370_irq_timeout(drive);
 859        }
 860        return __ide_dma_end(drive);
 861}
 862
 863static void hpt370_dma_timeout(ide_drive_t *drive)
 864{
 865        hpt370_irq_timeout(drive);
 866        ide_dma_timeout(drive);
 867}
 868
 869/* returns 1 if DMA IRQ issued, 0 otherwise */
 870static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 871{
 872        ide_hwif_t *hwif        = HWIF(drive);
 873        u16 bfifo               = 0;
 874        u8  dma_stat;
 875
 876        pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 877        if (bfifo & 0x1FF) {
 878//              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 879                return 0;
 880        }
 881
 882        dma_stat = inb(hwif->dma_status);
 883        /* return 1 if INTR asserted */
 884        if (dma_stat & 4)
 885                return 1;
 886
 887        if (!drive->waiting_for_dma)
 888                printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 889                                drive->name, __FUNCTION__);
 890        return 0;
 891}
 892
 893static int hpt374_ide_dma_end(ide_drive_t *drive)
 894{
 895        ide_hwif_t *hwif        = HWIF(drive);
 896        struct pci_dev  *dev    = hwif->pci_dev;
 897        u8 mcr  = 0, mcr_addr   = hwif->select_data;
 898        u8 bwsr = 0, mask       = hwif->channel ? 0x02 : 0x01;
 899
 900        pci_read_config_byte(dev, 0x6a, &bwsr);
 901        pci_read_config_byte(dev, mcr_addr, &mcr);
 902        if (bwsr & mask)
 903                pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
 904        return __ide_dma_end(drive);
 905}
 906
 907/**
 908 *      hpt3xxn_set_clock       -       perform clock switching dance
 909 *      @hwif: hwif to switch
 910 *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 911 *
 912 *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 913 */
 914
 915static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 916{
 917        u8 scr2 = inb(hwif->dma_master + 0x7b);
 918
 919        if ((scr2 & 0x7f) == mode)
 920                return;
 921
 922        /* Tristate the bus */
 923        outb(0x80, hwif->dma_master + 0x73);
 924        outb(0x80, hwif->dma_master + 0x77);
 925
 926        /* Switch clock and reset channels */
 927        outb(mode, hwif->dma_master + 0x7b);
 928        outb(0xc0, hwif->dma_master + 0x79);
 929
 930        /*
 931         * Reset the state machines.
 932         * NOTE: avoid accidentally enabling the disabled channels.
 933         */
 934        outb(inb(hwif->dma_master + 0x70) | 0x32, hwif->dma_master + 0x70);
 935        outb(inb(hwif->dma_master + 0x74) | 0x32, hwif->dma_master + 0x74);
 936
 937        /* Complete reset */
 938        outb(0x00, hwif->dma_master + 0x79);
 939
 940        /* Reconnect channels to bus */
 941        outb(0x00, hwif->dma_master + 0x73);
 942        outb(0x00, hwif->dma_master + 0x77);
 943}
 944
 945/**
 946 *      hpt3xxn_rw_disk         -       prepare for I/O
 947 *      @drive: drive for command
 948 *      @rq: block request structure
 949 *
 950 *      This is called when a disk I/O is issued to HPT3xxN.
 951 *      We need it because of the clock switching.
 952 */
 953
 954static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 955{
 956        hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
 957}
 958
 959/* 
 960 * Set/get power state for a drive.
 961 * NOTE: affects both drives on each channel.
 962 *
 963 * When we turn the power back on, we need to re-initialize things.
 964 */
 965#define TRISTATE_BIT  0x8000
 966
 967static int hpt3xx_busproc(ide_drive_t *drive, int state)
 968{
 969        ide_hwif_t *hwif        = HWIF(drive);
 970        struct pci_dev *dev     = hwif->pci_dev;
 971        u8  mcr_addr            = hwif->select_data + 2;
 972        u8  resetmask           = hwif->channel ? 0x80 : 0x40;
 973        u8  bsr2                = 0;
 974        u16 mcr                 = 0;
 975
 976        hwif->bus_state = state;
 977
 978        /* Grab the status. */
 979        pci_read_config_word(dev, mcr_addr, &mcr);
 980        pci_read_config_byte(dev, 0x59, &bsr2);
 981
 982        /*
 983         * Set the state. We don't set it if we don't need to do so.
 984         * Make sure that the drive knows that it has failed if it's off.
 985         */
 986        switch (state) {
 987        case BUSSTATE_ON:
 988                if (!(bsr2 & resetmask))
 989                        return 0;
 990                hwif->drives[0].failures = hwif->drives[1].failures = 0;
 991
 992                pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
 993                pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
 994                return 0;
 995        case BUSSTATE_OFF:
 996                if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
 997                        return 0;
 998                mcr &= ~TRISTATE_BIT;
 999                break;
1000        case BUSSTATE_TRISTATE:
1001                if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
1002                        return 0;
1003                mcr |= TRISTATE_BIT;
1004                break;
1005        default:
1006                return -EINVAL;
1007        }
1008
1009        hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1010        hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1011
1012        pci_write_config_word(dev, mcr_addr, mcr);
1013        pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
1014        return 0;
1015}
1016
1017/**
1018 *      hpt37x_calibrate_dpll   -       calibrate the DPLL
1019 *      @dev: PCI device
1020 *
1021 *      Perform a calibration cycle on the DPLL.
1022 *      Returns 1 if this succeeds
1023 */
1024static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
1025{
1026        u32 dpll = (f_high << 16) | f_low | 0x100;
1027        u8  scr2;
1028        int i;
1029
1030        pci_write_config_dword(dev, 0x5c, dpll);
1031
1032        /* Wait for oscillator ready */
1033        for(i = 0; i < 0x5000; ++i) {
1034                udelay(50);
1035                pci_read_config_byte(dev, 0x5b, &scr2);
1036                if (scr2 & 0x80)
1037                        break;
1038        }
1039        /* See if it stays ready (we'll just bail out if it's not yet) */
1040        for(i = 0; i < 0x1000; ++i) {
1041                pci_read_config_byte(dev, 0x5b, &scr2);
1042                /* DPLL destabilized? */
1043                if(!(scr2 & 0x80))
1044                        return 0;
1045        }
1046        /* Turn off tuning, we have the DPLL set */
1047        pci_read_config_dword (dev, 0x5c, &dpll);
1048        pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
1049        return 1;
1050}
1051
1052static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1053{
1054        struct hpt_info *info   = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1055        unsigned long io_base   = pci_resource_start(dev, 4);
1056        u8 pci_clk,  dpll_clk   = 0;    /* PCI and DPLL clock in MHz */
1057        u8 chip_type;
1058        enum ata_clock  clock;
1059
1060        if (info == NULL) {
1061                printk(KERN_ERR "%s: out of memory!\n", name);
1062                return -ENOMEM;
1063        }
1064
1065        /*
1066         * Copy everything from a static "template" structure
1067         * to just allocated per-chip hpt_info structure.
1068         */
1069        memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
1070        chip_type = info->chip_type;
1071
1072        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1073        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1074        pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1075        pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1076
1077        /*
1078         * First, try to estimate the PCI clock frequency...
1079         */
1080        if (chip_type >= HPT370) {
1081                u8  scr1  = 0;
1082                u16 f_cnt = 0;
1083                u32 temp  = 0;
1084
1085                /* Interrupt force enable. */
1086                pci_read_config_byte(dev, 0x5a, &scr1);
1087                if (scr1 & 0x10)
1088                        pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1089
1090                /*
1091                 * HighPoint does this for HPT372A.
1092                 * NOTE: This register is only writeable via I/O space.
1093                 */
1094                if (chip_type == HPT372A)
1095                        outb(0x0e, io_base + 0x9c);
1096
1097                /*
1098                 * Default to PCI clock. Make sure MA15/16 are set to output
1099                 * to prevent drives having problems with 40-pin cables.
1100                 */
1101                pci_write_config_byte(dev, 0x5b, 0x23);
1102
1103                /*
1104                 * We'll have to read f_CNT value in order to determine
1105                 * the PCI clock frequency according to the following ratio:
1106                 *
1107                 * f_CNT = Fpci * 192 / Fdpll
1108                 *
1109                 * First try reading the register in which the HighPoint BIOS
1110                 * saves f_CNT value before  reprogramming the DPLL from its
1111                 * default setting (which differs for the various chips).
1112                 *
1113                 * NOTE: This register is only accessible via I/O space;
1114                 * HPT374 BIOS only saves it for the function 0, so we have to
1115                 * always read it from there -- no need to check the result of
1116                 * pci_get_slot() for the function 0 as the whole device has
1117                 * been already "pinned" (via function 1) in init_setup_hpt374()
1118                 */
1119                if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1120                        struct pci_dev  *dev1 = pci_get_slot(dev->bus,
1121                                                             dev->devfn - 1);
1122                        unsigned long io_base = pci_resource_start(dev1, 4);
1123
1124                        temp =  inl(io_base + 0x90);
1125                        pci_dev_put(dev1);
1126                } else
1127                        temp =  inl(io_base + 0x90);
1128
1129                /*
1130                 * In case the signature check fails, we'll have to
1131                 * resort to reading the f_CNT register itself in hopes
1132                 * that nobody has touched the DPLL yet...
1133                 */
1134                if ((temp & 0xFFFFF000) != 0xABCDE000) {
1135                        int i;
1136
1137                        printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1138                               name);
1139
1140                        /* Calculate the average value of f_CNT. */
1141                        for (temp = i = 0; i < 128; i++) {
1142                                pci_read_config_word(dev, 0x78, &f_cnt);
1143                                temp += f_cnt & 0x1ff;
1144                                mdelay(1);
1145                        }
1146                        f_cnt = temp / 128;
1147                } else
1148                        f_cnt = temp & 0x1ff;
1149
1150                dpll_clk = info->dpll_clk;
1151                pci_clk  = (f_cnt * dpll_clk) / 192;
1152
1153                /* Clamp PCI clock to bands. */
1154                if (pci_clk < 40)
1155                        pci_clk = 33;
1156                else if(pci_clk < 45)
1157                        pci_clk = 40;
1158                else if(pci_clk < 55)
1159                        pci_clk = 50;
1160                else
1161                        pci_clk = 66;
1162
1163                printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1164                       "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1165        } else {
1166                u32 itr1 = 0;
1167
1168                pci_read_config_dword(dev, 0x40, &itr1);
1169
1170                /* Detect PCI clock by looking at cmd_high_time. */
1171                switch((itr1 >> 8) & 0x07) {
1172                        case 0x09:
1173                                pci_clk = 40;
1174                                break;
1175                        case 0x05:
1176                                pci_clk = 25;
1177                                break;
1178                        case 0x07:
1179                        default:
1180                                pci_clk = 33;
1181                                break;
1182                }
1183        }
1184
1185        /* Let's assume we'll use PCI clock for the ATA clock... */
1186        switch (pci_clk) {
1187                case 25:
1188                        clock = ATA_CLOCK_25MHZ;
1189                        break;
1190                case 33:
1191                default:
1192                        clock = ATA_CLOCK_33MHZ;
1193                        break;
1194                case 40:
1195                        clock = ATA_CLOCK_40MHZ;
1196                        break;
1197                case 50:
1198                        clock = ATA_CLOCK_50MHZ;
1199                        break;
1200                case 66:
1201                        clock = ATA_CLOCK_66MHZ;
1202                        break;
1203        }
1204
1205        /*
1206         * Only try the DPLL if we don't have a table for the PCI clock that
1207         * we are running at for HPT370/A, always use it  for anything newer...
1208         *
1209         * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1210         * We also  don't like using  the DPLL because this causes glitches
1211         * on PRST-/SRST- when the state engine gets reset...
1212         */
1213        if (chip_type >= HPT374 || info->settings[clock] == NULL) {
1214                u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1215                int adjust;
1216
1217                 /*
1218                  * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1219                  * supported/enabled, use 50 MHz DPLL clock otherwise...
1220                  */
1221                if (info->udma_mask == ATA_UDMA6) {
1222                        dpll_clk = 66;
1223                        clock = ATA_CLOCK_66MHZ;
1224                } else if (dpll_clk) {  /* HPT36x chips don't have DPLL */
1225                        dpll_clk = 50;
1226                        clock = ATA_CLOCK_50MHZ;
1227                }
1228
1229                if (info->settings[clock] == NULL) {
1230                        printk(KERN_ERR "%s: unknown bus timing!\n", name);
1231                        kfree(info);
1232                        return -EIO;
1233                }
1234
1235                /* Select the DPLL clock. */
1236                pci_write_config_byte(dev, 0x5b, 0x21);
1237
1238                /*
1239                 * Adjust the DPLL based upon PCI clock, enable it,
1240                 * and wait for stabilization...
1241                 */
1242                f_low = (pci_clk * 48) / dpll_clk;
1243
1244                for (adjust = 0; adjust < 8; adjust++) {
1245                        if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1246                                break;
1247
1248                        /*
1249                         * See if it'll settle at a fractionally different clock
1250                         */
1251                        if (adjust & 1)
1252                                f_low -= adjust >> 1;
1253                        else
1254                                f_low += adjust >> 1;
1255                }
1256                if (adjust == 8) {
1257                        printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1258                        kfree(info);
1259                        return -EIO;
1260                }
1261
1262                printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1263        } else {
1264                /* Mark the fact that we're not using the DPLL. */
1265                dpll_clk = 0;
1266
1267                printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1268        }
1269
1270        /*
1271         * Advance the table pointer to a slot which points to the list
1272         * of the register values settings matching the clock being used.
1273         */
1274        info->settings += clock;
1275
1276        /* Store the clock frequencies. */
1277        info->dpll_clk  = dpll_clk;
1278        info->pci_clk   = pci_clk;
1279
1280        /* Point to this chip's own instance of the hpt_info structure. */
1281        pci_set_drvdata(dev, info);
1282
1283        if (chip_type >= HPT370) {
1284                u8  mcr1, mcr4;
1285
1286                /*
1287                 * Reset the state engines.
1288                 * NOTE: Avoid accidentally enabling the disabled channels.
1289                 */
1290                pci_read_config_byte (dev, 0x50, &mcr1);
1291                pci_read_config_byte (dev, 0x54, &mcr4);
1292                pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1293                pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1294                udelay(100);
1295        }
1296
1297        /*
1298         * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1299         * the MISC. register to stretch the UltraDMA Tss timing.
1300         * NOTE: This register is only writeable via I/O space.
1301         */
1302        if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1303
1304                outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1305
1306        return dev->irq;
1307}
1308
1309static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1310{
1311        struct pci_dev  *dev    = hwif->pci_dev;
1312        struct hpt_info *info   = pci_get_drvdata(dev);
1313        int serialize           = HPT_SERIALIZE_IO;
1314        u8  scr1 = 0, ata66     = hwif->channel ? 0x01 : 0x02;
1315        u8  chip_type           = info->chip_type;
1316        u8  new_mcr, old_mcr    = 0;
1317
1318        /* Cache the channel's MISC. control registers' offset */
1319        hwif->select_data       = hwif->channel ? 0x54 : 0x50;
1320
1321        hwif->set_pio_mode      = &hpt3xx_set_pio_mode;
1322        hwif->set_dma_mode      = &hpt3xx_set_mode;
1323        hwif->quirkproc         = &hpt3xx_quirkproc;
1324        hwif->intrproc          = &hpt3xx_intrproc;
1325        hwif->maskproc          = &hpt3xx_maskproc;
1326        hwif->busproc           = &hpt3xx_busproc;
1327
1328        hwif->udma_filter       = &hpt3xx_udma_filter;
1329        hwif->mdma_filter       = &hpt3xx_mdma_filter;
1330
1331        /*
1332         * HPT3xxN chips have some complications:
1333         *
1334         * - on 33 MHz PCI we must clock switch
1335         * - on 66 MHz PCI we must NOT use the PCI clock
1336         */
1337        if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1338                /*
1339                 * Clock is shared between the channels,
1340                 * so we'll have to serialize them... :-(
1341                 */
1342                serialize = 1;
1343                hwif->rw_disk = &hpt3xxn_rw_disk;
1344        }
1345
1346        /* Serialize access to this device if needed */
1347        if (serialize && hwif->mate)
1348                hwif->serialized = hwif->mate->serialized = 1;
1349
1350        /*
1351         * Disable the "fast interrupt" prediction.  Don't hold off
1352         * on interrupts. (== 0x01 despite what the docs say)
1353         */
1354        pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1355
1356        if (info->chip_type >= HPT374)
1357                new_mcr = old_mcr & ~0x07;
1358        else if (info->chip_type >= HPT370) {
1359                new_mcr = old_mcr;
1360                new_mcr &= ~0x02;
1361
1362#ifdef HPT_DELAY_INTERRUPT
1363                new_mcr &= ~0x01;
1364#else
1365                new_mcr |=  0x01;
1366#endif
1367        } else                                  /* HPT366 and HPT368  */
1368                new_mcr = old_mcr & ~0x80;
1369
1370        if (new_mcr != old_mcr)
1371                pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1372
1373        if (hwif->dma_base == 0)
1374                return;
1375
1376        /*
1377         * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1378         * address lines to access an external EEPROM.  To read valid
1379         * cable detect state the pins must be enabled as inputs.
1380         */
1381        if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1382                /*
1383                 * HPT374 PCI function 1
1384                 * - set bit 15 of reg 0x52 to enable TCBLID as input
1385                 * - set bit 15 of reg 0x56 to enable FCBLID as input
1386                 */
1387                u8  mcr_addr = hwif->select_data + 2;
1388                u16 mcr;
1389
1390                pci_read_config_word (dev, mcr_addr, &mcr);
1391                pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1392                /* now read cable id register */
1393                pci_read_config_byte (dev, 0x5a, &scr1);
1394                pci_write_config_word(dev, mcr_addr, mcr);
1395        } else if (chip_type >= HPT370) {
1396                /*
1397                 * HPT370/372 and 374 pcifn 0
1398                 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1399                 */
1400                u8 scr2 = 0;
1401
1402                pci_read_config_byte (dev, 0x5b, &scr2);
1403                pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1404                /* now read cable id register */
1405                pci_read_config_byte (dev, 0x5a, &scr1);
1406                pci_write_config_byte(dev, 0x5b,  scr2);
1407        } else
1408                pci_read_config_byte (dev, 0x5a, &scr1);
1409
1410        if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1411                hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1412
1413        if (chip_type >= HPT374) {
1414                hwif->ide_dma_test_irq  = &hpt374_ide_dma_test_irq;
1415                hwif->ide_dma_end       = &hpt374_ide_dma_end;
1416        } else if (chip_type >= HPT370) {
1417                hwif->dma_start         = &hpt370_ide_dma_start;
1418                hwif->ide_dma_end       = &hpt370_ide_dma_end;
1419                hwif->dma_timeout       = &hpt370_dma_timeout;
1420        } else
1421                hwif->dma_lost_irq      = &hpt366_dma_lost_irq;
1422}
1423
1424static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1425{
1426        struct pci_dev  *dev            = hwif->pci_dev;
1427        u8 masterdma    = 0, slavedma   = 0;
1428        u8 dma_new      = 0, dma_old    = 0;
1429        unsigned long flags;
1430
1431        dma_old = inb(dmabase + 2);
1432
1433        local_irq_save(flags);
1434
1435        dma_new = dma_old;
1436        pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1437        pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47,  &slavedma);
1438
1439        if (masterdma & 0x30)   dma_new |= 0x20;
1440        if ( slavedma & 0x30)   dma_new |= 0x40;
1441        if (dma_new != dma_old)
1442                outb(dma_new, dmabase + 2);
1443
1444        local_irq_restore(flags);
1445
1446        ide_setup_dma(hwif, dmabase, 8);
1447}
1448
1449static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1450{
1451        if (dev2->irq != dev->irq) {
1452                /* FIXME: we need a core pci_set_interrupt() */
1453                dev2->irq = dev->irq;
1454                printk(KERN_INFO "HPT374: PCI config space interrupt fixed\n");
1455        }
1456}
1457
1458static void __devinit hpt371_init(struct pci_dev *dev)
1459{
1460        u8 mcr1 = 0;
1461
1462        /*
1463         * HPT371 chips physically have only one channel, the secondary one,
1464         * but the primary channel registers do exist!  Go figure...
1465         * So,  we manually disable the non-existing channel here
1466         * (if the BIOS hasn't done this already).
1467         */
1468        pci_read_config_byte(dev, 0x50, &mcr1);
1469        if (mcr1 & 0x04)
1470                pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1471}
1472
1473static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1474{
1475        u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1476
1477        /*
1478         * Now we'll have to force both channels enabled if
1479         * at least one of them has been enabled by BIOS...
1480         */
1481        pci_read_config_byte(dev, 0x50, &mcr1);
1482        if (mcr1 & 0x30)
1483                pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1484
1485        pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1486        pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1487
1488        if (pin1 != pin2 && dev->irq == dev2->irq) {
1489                printk(KERN_INFO "HPT36x: onboard version of chipset, "
1490                                 "pin1=%d pin2=%d\n", pin1, pin2);
1491                return 1;
1492        }
1493
1494        return 0;
1495}
1496
1497static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1498        {       /* 0 */
1499                .name           = "HPT36x",
1500                .init_chipset   = init_chipset_hpt366,
1501                .init_hwif      = init_hwif_hpt366,
1502                .init_dma       = init_dma_hpt366,
1503                /*
1504                 * HPT36x chips have one channel per function and have
1505                 * both channel enable bits located differently and visible
1506                 * to both functions -- really stupid design decision... :-(
1507                 * Bit 4 is for the primary channel, bit 5 for the secondary.
1508                 */
1509                .enablebits     = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1510                .extra          = 240,
1511                .host_flags     = IDE_HFLAG_SINGLE |
1512                                  IDE_HFLAG_NO_ATAPI_DMA |
1513                                  IDE_HFLAG_OFF_BOARD,
1514                .pio_mask       = ATA_PIO4,
1515                .mwdma_mask     = ATA_MWDMA2,
1516        },{     /* 1 */
1517                .name           = "HPT372A",
1518                .init_chipset   = init_chipset_hpt366,
1519                .init_hwif      = init_hwif_hpt366,
1520                .init_dma       = init_dma_hpt366,
1521                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1522                .extra          = 240,
1523                .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1524                .pio_mask       = ATA_PIO4,
1525                .mwdma_mask     = ATA_MWDMA2,
1526        },{     /* 2 */
1527                .name           = "HPT302",
1528                .init_chipset   = init_chipset_hpt366,
1529                .init_hwif      = init_hwif_hpt366,
1530                .init_dma       = init_dma_hpt366,
1531                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1532                .extra          = 240,
1533                .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1534                .pio_mask       = ATA_PIO4,
1535                .mwdma_mask     = ATA_MWDMA2,
1536        },{     /* 3 */
1537                .name           = "HPT371",
1538                .init_chipset   = init_chipset_hpt366,
1539                .init_hwif      = init_hwif_hpt366,
1540                .init_dma       = init_dma_hpt366,
1541                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1542                .extra          = 240,
1543                .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1544                .pio_mask       = ATA_PIO4,
1545                .mwdma_mask     = ATA_MWDMA2,
1546        },{     /* 4 */
1547                .name           = "HPT374",
1548                .init_chipset   = init_chipset_hpt366,
1549                .init_hwif      = init_hwif_hpt366,
1550                .init_dma       = init_dma_hpt366,
1551                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1552                .udma_mask      = ATA_UDMA5,
1553                .extra          = 240,
1554                .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1555                .pio_mask       = ATA_PIO4,
1556                .mwdma_mask     = ATA_MWDMA2,
1557        },{     /* 5 */
1558                .name           = "HPT372N",
1559                .init_chipset   = init_chipset_hpt366,
1560                .init_hwif      = init_hwif_hpt366,
1561                .init_dma       = init_dma_hpt366,
1562                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1563                .extra          = 240,
1564                .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
1565                .pio_mask       = ATA_PIO4,
1566                .mwdma_mask     = ATA_MWDMA2,
1567        }
1568};
1569
1570/**
1571 *      hpt366_init_one -       called when an HPT366 is found
1572 *      @dev: the hpt366 device
1573 *      @id: the matching pci id
1574 *
1575 *      Called when the PCI registration layer (or the IDE initialization)
1576 *      finds a device matching our IDE device tables.
1577 */
1578static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1579{
1580        const struct hpt_info *info = NULL;
1581        struct pci_dev *dev2 = NULL;
1582        struct ide_port_info d;
1583        u8 idx = id->driver_data;
1584        u8 rev = dev->revision;
1585
1586        if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1587                return -ENODEV;
1588
1589        switch (idx) {
1590        case 0:
1591                if (rev < 3)
1592                        info = &hpt36x;
1593                else {
1594                        static const struct hpt_info *hpt37x_info[] =
1595                                { &hpt370, &hpt370a, &hpt372, &hpt372n };
1596
1597                        info = hpt37x_info[min_t(u8, rev, 6) - 3];
1598                        idx++;
1599                }
1600                break;
1601        case 1:
1602                info = (rev > 1) ? &hpt372n : &hpt372a;
1603                break;
1604        case 2:
1605                info = (rev > 1) ? &hpt302n : &hpt302;
1606                break;
1607        case 3:
1608                hpt371_init(dev);
1609                info = (rev > 1) ? &hpt371n : &hpt371;
1610                break;
1611        case 4:
1612                info = &hpt374;
1613                break;
1614        case 5:
1615                info = &hpt372n;
1616                break;
1617        }
1618
1619        d = hpt366_chipsets[idx];
1620
1621        d.name = info->chip_name;
1622        d.udma_mask = info->udma_mask;
1623
1624        pci_set_drvdata(dev, (void *)info);
1625
1626        if (info == &hpt36x || info == &hpt374)
1627                dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1628
1629        if (dev2) {
1630                int ret;
1631
1632                pci_set_drvdata(dev2, (void *)info);
1633
1634                if (info == &hpt374)
1635                        hpt374_init(dev, dev2);
1636                else {
1637                        if (hpt36x_init(dev, dev2))
1638                                d.host_flags |= IDE_HFLAG_BOOTABLE;
1639                }
1640
1641                ret = ide_setup_pci_devices(dev, dev2, &d);
1642                if (ret < 0)
1643                        pci_dev_put(dev2);
1644                return ret;
1645        }
1646
1647        return ide_setup_pci_device(dev, &d);
1648}
1649
1650static const struct pci_device_id hpt366_pci_tbl[] = {
1651        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366),  0 },
1652        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372),  1 },
1653        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302),  2 },
1654        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371),  3 },
1655        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374),  4 },
1656        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1657        { 0, },
1658};
1659MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1660
1661static struct pci_driver driver = {
1662        .name           = "HPT366_IDE",
1663        .id_table       = hpt366_pci_tbl,
1664        .probe          = hpt366_init_one,
1665};
1666
1667static int __init hpt366_ide_init(void)
1668{
1669        return ide_pci_register_driver(&driver);
1670}
1671
1672module_init(hpt366_ide_init);
1673
1674MODULE_AUTHOR("Andre Hedrick");
1675MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1676MODULE_LICENSE("GPL");
1677
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