linux/drivers/ide/pci/cmd64x.c
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   1/*
   2 * linux/drivers/ide/pci/cmd64x.c               Version 1.52    Dec 24, 2007
   3 *
   4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
   5 *           Due to massive hardware bugs, UltraDMA is only supported
   6 *           on the 646U2 and not on the 646U.
   7 *
   8 * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
   9 * Copyright (C) 1998           David S. Miller (davem@redhat.com)
  10 *
  11 * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
  12 * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
  13 */
  14
  15#include <linux/module.h>
  16#include <linux/types.h>
  17#include <linux/pci.h>
  18#include <linux/delay.h>
  19#include <linux/hdreg.h>
  20#include <linux/ide.h>
  21#include <linux/init.h>
  22
  23#include <asm/io.h>
  24
  25#define DISPLAY_CMD64X_TIMINGS
  26
  27#define CMD_DEBUG 0
  28
  29#if CMD_DEBUG
  30#define cmdprintk(x...) printk(x)
  31#else
  32#define cmdprintk(x...)
  33#endif
  34
  35/*
  36 * CMD64x specific registers definition.
  37 */
  38#define CFR             0x50
  39#define   CFR_INTR_CH0          0x04
  40#define CNTRL           0x51
  41#define   CNTRL_ENA_1ST         0x04
  42#define   CNTRL_ENA_2ND         0x08
  43#define   CNTRL_DIS_RA0         0x40
  44#define   CNTRL_DIS_RA1         0x80
  45
  46#define CMDTIM          0x52
  47#define ARTTIM0         0x53
  48#define DRWTIM0         0x54
  49#define ARTTIM1         0x55
  50#define DRWTIM1         0x56
  51#define ARTTIM23        0x57
  52#define   ARTTIM23_DIS_RA2      0x04
  53#define   ARTTIM23_DIS_RA3      0x08
  54#define   ARTTIM23_INTR_CH1     0x10
  55#define DRWTIM2         0x58
  56#define BRST            0x59
  57#define DRWTIM3         0x5b
  58
  59#define BMIDECR0        0x70
  60#define MRDMODE         0x71
  61#define   MRDMODE_INTR_CH0      0x04
  62#define   MRDMODE_INTR_CH1      0x08
  63#define   MRDMODE_BLK_CH0       0x10
  64#define   MRDMODE_BLK_CH1       0x20
  65#define BMIDESR0        0x72
  66#define UDIDETCR0       0x73
  67#define DTPR0           0x74
  68#define BMIDECR1        0x78
  69#define BMIDECSR        0x79
  70#define BMIDESR1        0x7A
  71#define UDIDETCR1       0x7B
  72#define DTPR1           0x7C
  73
  74#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
  75#include <linux/stat.h>
  76#include <linux/proc_fs.h>
  77
  78static u8 cmd64x_proc = 0;
  79
  80#define CMD_MAX_DEVS            5
  81
  82static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
  83static int n_cmd_devs;
  84
  85static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
  86{
  87        char *p = buf;
  88        u8 reg72 = 0, reg73 = 0;                        /* primary */
  89        u8 reg7a = 0, reg7b = 0;                        /* secondary */
  90        u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0;  /* extra */
  91
  92        p += sprintf(p, "\nController: %d\n", index);
  93        p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
  94
  95        (void) pci_read_config_byte(dev, CFR,       &reg50);
  96        (void) pci_read_config_byte(dev, CNTRL,     &reg51);
  97        (void) pci_read_config_byte(dev, ARTTIM23,  &reg57);
  98        (void) pci_read_config_byte(dev, MRDMODE,   &reg71);
  99        (void) pci_read_config_byte(dev, BMIDESR0,  &reg72);
 100        (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
 101        (void) pci_read_config_byte(dev, BMIDESR1,  &reg7a);
 102        (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
 103
 104        /* PCI0643/6 originally didn't have the primary channel enable bit */
 105        if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
 106            (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3))
 107                reg51 |= CNTRL_ENA_1ST;
 108
 109        p += sprintf(p, "---------------- Primary Channel "
 110                        "---------------- Secondary Channel ------------\n");
 111        p += sprintf(p, "                 %s                         %s\n",
 112                 (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
 113                 (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
 114        p += sprintf(p, "---------------- drive0 --------- drive1 "
 115                        "-------- drive0 --------- drive1 ------\n");
 116        p += sprintf(p, "DMA enabled:     %s              %s"
 117                        "             %s              %s\n",
 118                (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
 119                (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
 120        p += sprintf(p, "UltraDMA mode:   %s (%c)          %s (%c)",
 121                ( reg73 & 0x01) ? " on" : "off",
 122                ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
 123                ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
 124                ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
 125                ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
 126                ( reg73 & 0x02) ? " on" : "off",
 127                ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
 128                ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
 129                ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
 130                ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
 131        p += sprintf(p, "         %s (%c)          %s (%c)\n",
 132                ( reg7b & 0x01) ? " on" : "off",
 133                ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
 134                ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
 135                ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
 136                ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
 137                ( reg7b & 0x02) ? " on" : "off",
 138                ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
 139                ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
 140                ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
 141                ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
 142        p += sprintf(p, "Interrupt:       %s, %s                 %s, %s\n",
 143                (reg71 & MRDMODE_BLK_CH0  ) ? "blocked" : "enabled",
 144                (reg50 & CFR_INTR_CH0     ) ? "pending" : "clear  ",
 145                (reg71 & MRDMODE_BLK_CH1  ) ? "blocked" : "enabled",
 146                (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear  ");
 147
 148        return (char *)p;
 149}
 150
 151static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
 152{
 153        char *p = buffer;
 154        int i;
 155
 156        for (i = 0; i < n_cmd_devs; i++) {
 157                struct pci_dev *dev     = cmd_devs[i];
 158                p = print_cmd64x_get_info(p, dev, i);
 159        }
 160        return p-buffer;        /* => must be less than 4k! */
 161}
 162
 163#endif  /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
 164
 165static u8 quantize_timing(int timing, int quant)
 166{
 167        return (timing + quant - 1) / quant;
 168}
 169
 170/*
 171 * This routine calculates active/recovery counts and then writes them into
 172 * the chipset registers.
 173 */
 174static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
 175{
 176        struct pci_dev *dev     = HWIF(drive)->pci_dev;
 177        int clock_time          = 1000 / system_bus_clock();
 178        u8  cycle_count, active_count, recovery_count, drwtim;
 179        static const u8 recovery_values[] =
 180                {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
 181        static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
 182
 183        cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
 184                  cycle_time, active_time);
 185
 186        cycle_count     = quantize_timing( cycle_time, clock_time);
 187        active_count    = quantize_timing(active_time, clock_time);
 188        recovery_count  = cycle_count - active_count;
 189
 190        /*
 191         * In case we've got too long recovery phase, try to lengthen
 192         * the active phase
 193         */
 194        if (recovery_count > 16) {
 195                active_count += recovery_count - 16;
 196                recovery_count = 16;
 197        }
 198        if (active_count > 16)          /* shouldn't actually happen... */
 199                active_count = 16;
 200
 201        cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
 202                  cycle_count, active_count, recovery_count);
 203
 204        /*
 205         * Convert values to internal chipset representation
 206         */
 207        recovery_count = recovery_values[recovery_count];
 208        active_count  &= 0x0f;
 209
 210        /* Program the active/recovery counts into the DRWTIM register */
 211        drwtim = (active_count << 4) | recovery_count;
 212        (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
 213        cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
 214}
 215
 216/*
 217 * This routine writes into the chipset registers
 218 * PIO setup/active/recovery timings.
 219 */
 220static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
 221{
 222        ide_hwif_t *hwif        = HWIF(drive);
 223        struct pci_dev *dev     = hwif->pci_dev;
 224        unsigned int cycle_time;
 225        u8 setup_count, arttim = 0;
 226
 227        static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
 228        static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
 229
 230        cycle_time = ide_pio_cycle_time(drive, pio);
 231
 232        program_cycle_times(drive, cycle_time,
 233                            ide_pio_timings[pio].active_time);
 234
 235        setup_count = quantize_timing(ide_pio_timings[pio].setup_time,
 236                                      1000 / system_bus_clock());
 237
 238        /*
 239         * The primary channel has individual address setup timing registers
 240         * for each drive and the hardware selects the slowest timing itself.
 241         * The secondary channel has one common register and we have to select
 242         * the slowest address setup timing ourselves.
 243         */
 244        if (hwif->channel) {
 245                ide_drive_t *drives = hwif->drives;
 246
 247                drive->drive_data = setup_count;
 248                setup_count = max(drives[0].drive_data, drives[1].drive_data);
 249        }
 250
 251        if (setup_count > 5)            /* shouldn't actually happen... */
 252                setup_count = 5;
 253        cmdprintk("Final address setup count: %d\n", setup_count);
 254
 255        /*
 256         * Program the address setup clocks into the ARTTIM registers.
 257         * Avoid clearing the secondary channel's interrupt bit.
 258         */
 259        (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
 260        if (hwif->channel)
 261                arttim &= ~ARTTIM23_INTR_CH1;
 262        arttim &= ~0xc0;
 263        arttim |= setup_values[setup_count];
 264        (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
 265        cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
 266}
 267
 268/*
 269 * Attempts to set drive's PIO mode.
 270 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 271 */
 272
 273static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
 274{
 275        /*
 276         * Filter out the prefetch control values
 277         * to prevent PIO5 from being programmed
 278         */
 279        if (pio == 8 || pio == 9)
 280                return;
 281
 282        cmd64x_tune_pio(drive, pio);
 283}
 284
 285static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
 286{
 287        ide_hwif_t *hwif        = HWIF(drive);
 288        struct pci_dev *dev     = hwif->pci_dev;
 289        u8 unit                 = drive->dn & 0x01;
 290        u8 regU = 0, pciU       = hwif->channel ? UDIDETCR1 : UDIDETCR0;
 291
 292        if (speed >= XFER_SW_DMA_0) {
 293                (void) pci_read_config_byte(dev, pciU, &regU);
 294                regU &= ~(unit ? 0xCA : 0x35);
 295        }
 296
 297        switch(speed) {
 298        case XFER_UDMA_5:
 299                regU |= unit ? 0x0A : 0x05;
 300                break;
 301        case XFER_UDMA_4:
 302                regU |= unit ? 0x4A : 0x15;
 303                break;
 304        case XFER_UDMA_3:
 305                regU |= unit ? 0x8A : 0x25;
 306                break;
 307        case XFER_UDMA_2:
 308                regU |= unit ? 0x42 : 0x11;
 309                break;
 310        case XFER_UDMA_1:
 311                regU |= unit ? 0x82 : 0x21;
 312                break;
 313        case XFER_UDMA_0:
 314                regU |= unit ? 0xC2 : 0x31;
 315                break;
 316        case XFER_MW_DMA_2:
 317                program_cycle_times(drive, 120, 70);
 318                break;
 319        case XFER_MW_DMA_1:
 320                program_cycle_times(drive, 150, 80);
 321                break;
 322        case XFER_MW_DMA_0:
 323                program_cycle_times(drive, 480, 215);
 324                break;
 325        default:
 326                return;
 327        }
 328
 329        if (speed >= XFER_SW_DMA_0)
 330                (void) pci_write_config_byte(dev, pciU, regU);
 331}
 332
 333static int cmd648_ide_dma_end (ide_drive_t *drive)
 334{
 335        ide_hwif_t *hwif        = HWIF(drive);
 336        int err                 = __ide_dma_end(drive);
 337        u8  irq_mask            = hwif->channel ? MRDMODE_INTR_CH1 :
 338                                                  MRDMODE_INTR_CH0;
 339        u8  mrdmode             = inb(hwif->dma_master + 0x01);
 340
 341        /* clear the interrupt bit */
 342        outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
 343             hwif->dma_master + 0x01);
 344
 345        return err;
 346}
 347
 348static int cmd64x_ide_dma_end (ide_drive_t *drive)
 349{
 350        ide_hwif_t *hwif        = HWIF(drive);
 351        struct pci_dev *dev     = hwif->pci_dev;
 352        int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 353        u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 354                                                  CFR_INTR_CH0;
 355        u8  irq_stat            = 0;
 356        int err                 = __ide_dma_end(drive);
 357
 358        (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 359        /* clear the interrupt bit */
 360        (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
 361
 362        return err;
 363}
 364
 365static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
 366{
 367        ide_hwif_t *hwif        = HWIF(drive);
 368        u8 irq_mask             = hwif->channel ? MRDMODE_INTR_CH1 :
 369                                                  MRDMODE_INTR_CH0;
 370        u8 dma_stat             = inb(hwif->dma_status);
 371        u8 mrdmode              = inb(hwif->dma_master + 0x01);
 372
 373#ifdef DEBUG
 374        printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
 375               drive->name, dma_stat, mrdmode, irq_mask);
 376#endif
 377        if (!(mrdmode & irq_mask))
 378                return 0;
 379
 380        /* return 1 if INTR asserted */
 381        if (dma_stat & 4)
 382                return 1;
 383
 384        return 0;
 385}
 386
 387static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
 388{
 389        ide_hwif_t *hwif        = HWIF(drive);
 390        struct pci_dev *dev     = hwif->pci_dev;
 391        int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 392        u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 393                                                  CFR_INTR_CH0;
 394        u8  dma_stat            = inb(hwif->dma_status);
 395        u8  irq_stat            = 0;
 396
 397        (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 398
 399#ifdef DEBUG
 400        printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
 401               drive->name, dma_stat, irq_stat, irq_mask);
 402#endif
 403        if (!(irq_stat & irq_mask))
 404                return 0;
 405
 406        /* return 1 if INTR asserted */
 407        if (dma_stat & 4)
 408                return 1;
 409
 410        return 0;
 411}
 412
 413/*
 414 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 415 * event order for DMA transfers.
 416 */
 417
 418static int cmd646_1_ide_dma_end (ide_drive_t *drive)
 419{
 420        ide_hwif_t *hwif = HWIF(drive);
 421        u8 dma_stat = 0, dma_cmd = 0;
 422
 423        drive->waiting_for_dma = 0;
 424        /* get DMA status */
 425        dma_stat = inb(hwif->dma_status);
 426        /* read DMA command state */
 427        dma_cmd = inb(hwif->dma_command);
 428        /* stop DMA */
 429        outb(dma_cmd & ~1, hwif->dma_command);
 430        /* clear the INTR & ERROR bits */
 431        outb(dma_stat | 6, hwif->dma_status);
 432        /* and free any DMA resources */
 433        ide_destroy_dmatable(drive);
 434        /* verify good DMA status */
 435        return (dma_stat & 7) != 4;
 436}
 437
 438static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
 439{
 440        u8 mrdmode = 0;
 441
 442        if (dev->device == PCI_DEVICE_ID_CMD_646) {
 443
 444                switch (dev->revision) {
 445                case 0x07:
 446                case 0x05:
 447                        printk("%s: UltraDMA capable\n", name);
 448                        break;
 449                case 0x03:
 450                default:
 451                        printk("%s: MultiWord DMA force limited\n", name);
 452                        break;
 453                case 0x01:
 454                        printk("%s: MultiWord DMA limited, "
 455                               "IRQ workaround enabled\n", name);
 456                        break;
 457                }
 458        }
 459
 460        /* Set a good latency timer and cache line size value. */
 461        (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 462        /* FIXME: pci_set_master() to ensure a good latency timer value */
 463
 464        /*
 465         * Enable interrupts, select MEMORY READ LINE for reads.
 466         *
 467         * NOTE: although not mentioned in the PCI0646U specs,
 468         * bits 0-1 are write only and won't be read back as
 469         * set or not -- PCI0646U2 specs clarify this point.
 470         */
 471        (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
 472        mrdmode &= ~0x30;
 473        (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
 474
 475#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
 476
 477        cmd_devs[n_cmd_devs++] = dev;
 478
 479        if (!cmd64x_proc) {
 480                cmd64x_proc = 1;
 481                ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
 482        }
 483#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */
 484
 485        return 0;
 486}
 487
 488static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
 489{
 490        struct pci_dev  *dev    = hwif->pci_dev;
 491        u8 bmidecsr = 0, mask   = hwif->channel ? 0x02 : 0x01;
 492
 493        switch (dev->device) {
 494        case PCI_DEVICE_ID_CMD_648:
 495        case PCI_DEVICE_ID_CMD_649:
 496                pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
 497                return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 498        default:
 499                return ATA_CBL_PATA40;
 500        }
 501}
 502
 503static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
 504{
 505        struct pci_dev *dev     = hwif->pci_dev;
 506
 507        hwif->set_pio_mode = &cmd64x_set_pio_mode;
 508        hwif->set_dma_mode = &cmd64x_set_dma_mode;
 509
 510        if (!hwif->dma_base)
 511                return;
 512
 513        /*
 514         * UltraDMA only supported on PCI646U and PCI646U2, which
 515         * correspond to revisions 0x03, 0x05 and 0x07 respectively.
 516         * Actually, although the CMD tech support people won't
 517         * tell me the details, the 0x03 revision cannot support
 518         * UDMA correctly without hardware modifications, and even
 519         * then it only works with Quantum disks due to some
 520         * hold time assumptions in the 646U part which are fixed
 521         * in the 646U2.
 522         *
 523         * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
 524         */
 525        if (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 5)
 526                hwif->ultra_mask = 0x00;
 527
 528        if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 529                hwif->cbl = ata66_cmd64x(hwif);
 530
 531        switch (dev->device) {
 532        case PCI_DEVICE_ID_CMD_648:
 533        case PCI_DEVICE_ID_CMD_649:
 534        alt_irq_bits:
 535                hwif->ide_dma_end       = &cmd648_ide_dma_end;
 536                hwif->ide_dma_test_irq  = &cmd648_ide_dma_test_irq;
 537                break;
 538        case PCI_DEVICE_ID_CMD_646:
 539                if (dev->revision == 0x01) {
 540                        hwif->ide_dma_end = &cmd646_1_ide_dma_end;
 541                        break;
 542                } else if (dev->revision >= 0x03)
 543                        goto alt_irq_bits;
 544                /* fall thru */
 545        default:
 546                hwif->ide_dma_end       = &cmd64x_ide_dma_end;
 547                hwif->ide_dma_test_irq  = &cmd64x_ide_dma_test_irq;
 548                break;
 549        }
 550}
 551
 552static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
 553        {       /* 0 */
 554                .name           = "CMD643",
 555                .init_chipset   = init_chipset_cmd64x,
 556                .init_hwif      = init_hwif_cmd64x,
 557                .enablebits     = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
 558                .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 559                .pio_mask       = ATA_PIO5,
 560                .mwdma_mask     = ATA_MWDMA2,
 561                .udma_mask      = 0x00, /* no udma */
 562        },{     /* 1 */
 563                .name           = "CMD646",
 564                .init_chipset   = init_chipset_cmd64x,
 565                .init_hwif      = init_hwif_cmd64x,
 566                .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 567                .chipset        = ide_cmd646,
 568                .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 569                .pio_mask       = ATA_PIO5,
 570                .mwdma_mask     = ATA_MWDMA2,
 571                .udma_mask      = ATA_UDMA2,
 572        },{     /* 2 */
 573                .name           = "CMD648",
 574                .init_chipset   = init_chipset_cmd64x,
 575                .init_hwif      = init_hwif_cmd64x,
 576                .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 577                .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 578                .pio_mask       = ATA_PIO5,
 579                .mwdma_mask     = ATA_MWDMA2,
 580                .udma_mask      = ATA_UDMA4,
 581        },{     /* 3 */
 582                .name           = "CMD649",
 583                .init_chipset   = init_chipset_cmd64x,
 584                .init_hwif      = init_hwif_cmd64x,
 585                .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 586                .host_flags     = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
 587                .pio_mask       = ATA_PIO5,
 588                .mwdma_mask     = ATA_MWDMA2,
 589                .udma_mask      = ATA_UDMA5,
 590        }
 591};
 592
 593static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 594{
 595        struct ide_port_info d;
 596        u8 idx = id->driver_data;
 597
 598        d = cmd64x_chipsets[idx];
 599
 600        /*
 601         * The original PCI0646 didn't have the primary channel enable bit,
 602         * it appeared starting with PCI0646U (i.e. revision ID 3).
 603         */
 604        if (idx == 1 && dev->revision < 3)
 605                d.enablebits[0].reg = 0;
 606
 607        return ide_setup_pci_device(dev, &d);
 608}
 609
 610static const struct pci_device_id cmd64x_pci_tbl[] = {
 611        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
 612        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
 613        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
 614        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
 615        { 0, },
 616};
 617MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
 618
 619static struct pci_driver driver = {
 620        .name           = "CMD64x_IDE",
 621        .id_table       = cmd64x_pci_tbl,
 622        .probe          = cmd64x_init_one,
 623};
 624
 625static int __init cmd64x_ide_init(void)
 626{
 627        return ide_pci_register_driver(&driver);
 628}
 629
 630module_init(cmd64x_ide_init);
 631
 632MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
 633MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
 634MODULE_LICENSE("GPL");
 635
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