linux/drivers/ide/cris/ide-cris.c
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   1/* $Id: cris-ide-driver.patch,v 1.1 2005/06/29 21:39:07 akpm Exp $
   2 *
   3 * Etrax specific IDE functions, like init and PIO-mode setting etc.
   4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
   5 * Copyright (c) 2000-2005 Axis Communications AB
   6 *
   7 * Authors:    Bjorn Wesen        (initial version)
   8 *             Mikael Starvik     (crisv32 port)
   9 */
  10
  11/* Regarding DMA:
  12 *
  13 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
  14 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
  15 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
  16 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
  17 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
  18 */
  19
  20#include <linux/types.h>
  21#include <linux/kernel.h>
  22#include <linux/timer.h>
  23#include <linux/mm.h>
  24#include <linux/interrupt.h>
  25#include <linux/delay.h>
  26#include <linux/blkdev.h>
  27#include <linux/hdreg.h>
  28#include <linux/ide.h>
  29#include <linux/init.h>
  30
  31#include <asm/io.h>
  32#include <asm/dma.h>
  33
  34/* number of DMA descriptors */
  35#define MAX_DMA_DESCRS 64
  36
  37/* number of times to retry busy-flags when reading/writing IDE-registers
  38 * this can't be too high because a hung harddisk might cause the watchdog
  39 * to trigger (sometimes INB and OUTB are called with irq's disabled)
  40 */
  41
  42#define IDE_REGISTER_TIMEOUT 300
  43
  44#define LOWDB(x)
  45#define D(x)
  46
  47enum /* Transfer types */
  48{
  49        TYPE_PIO,
  50        TYPE_DMA,
  51        TYPE_UDMA
  52};
  53
  54/* CRISv32 specifics */
  55#ifdef CONFIG_ETRAX_ARCH_V32
  56#include <asm/arch/hwregs/ata_defs.h>
  57#include <asm/arch/hwregs/dma_defs.h>
  58#include <asm/arch/hwregs/dma.h>
  59#include <asm/arch/pinmux.h>
  60
  61#define ATA_UDMA2_CYC    2
  62#define ATA_UDMA2_DVS    3
  63#define ATA_UDMA1_CYC    2
  64#define ATA_UDMA1_DVS    4
  65#define ATA_UDMA0_CYC    4
  66#define ATA_UDMA0_DVS    6
  67#define ATA_DMA2_STROBE  7
  68#define ATA_DMA2_HOLD    1
  69#define ATA_DMA1_STROBE  8
  70#define ATA_DMA1_HOLD    3
  71#define ATA_DMA0_STROBE 25
  72#define ATA_DMA0_HOLD   19
  73#define ATA_PIO4_SETUP   3
  74#define ATA_PIO4_STROBE  7
  75#define ATA_PIO4_HOLD    1
  76#define ATA_PIO3_SETUP   3
  77#define ATA_PIO3_STROBE  9
  78#define ATA_PIO3_HOLD    3
  79#define ATA_PIO2_SETUP   3
  80#define ATA_PIO2_STROBE 13
  81#define ATA_PIO2_HOLD    5
  82#define ATA_PIO1_SETUP   5
  83#define ATA_PIO1_STROBE 23
  84#define ATA_PIO1_HOLD    9
  85#define ATA_PIO0_SETUP   9
  86#define ATA_PIO0_STROBE 39
  87#define ATA_PIO0_HOLD    9
  88
  89int
  90cris_ide_ack_intr(ide_hwif_t* hwif)
  91{
  92        reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
  93                                 int, hwif->io_ports[0]);
  94        REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
  95        return 1;
  96}
  97
  98static inline int
  99cris_ide_busy(void)
 100{
 101        reg_ata_rs_stat_data stat_data;
 102        stat_data = REG_RD(ata, regi_ata, rs_stat_data);
 103        return stat_data.busy;
 104}
 105
 106static inline int
 107cris_ide_ready(void)
 108{
 109        return !cris_ide_busy();
 110}
 111
 112static inline int
 113cris_ide_data_available(unsigned short* data)
 114{
 115        reg_ata_rs_stat_data stat_data;
 116        stat_data = REG_RD(ata, regi_ata, rs_stat_data);
 117        *data = stat_data.data;
 118        return stat_data.dav;
 119}
 120
 121static void
 122cris_ide_write_command(unsigned long command)
 123{
 124        REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
 125}
 126
 127static void
 128cris_ide_set_speed(int type, int setup, int strobe, int hold)
 129{
 130        reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
 131        reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
 132
 133        if (type == TYPE_PIO) {
 134                ctrl0.pio_setup = setup;
 135                ctrl0.pio_strb = strobe;
 136                ctrl0.pio_hold = hold;
 137        } else if (type == TYPE_DMA) {
 138                ctrl0.dma_strb = strobe;
 139                ctrl0.dma_hold = hold;
 140        } else if (type == TYPE_UDMA) {
 141                ctrl1.udma_tcyc = setup;
 142                ctrl1.udma_tdvs = strobe;
 143        }
 144        REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
 145        REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
 146}
 147
 148static unsigned long
 149cris_ide_base_address(int bus)
 150{
 151        reg_ata_rw_ctrl2 ctrl2 = {0};
 152        ctrl2.sel = bus;
 153        return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
 154}
 155
 156static unsigned long
 157cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
 158{
 159        reg_ata_rw_ctrl2 ctrl2 = {0};
 160        ctrl2.addr = addr;
 161        ctrl2.cs1 = cs1;
 162        ctrl2.cs0 = cs0;
 163        return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
 164}
 165
 166static __init void
 167cris_ide_reset(unsigned val)
 168{
 169        reg_ata_rw_ctrl0 ctrl0 = {0};
 170        ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
 171        REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
 172}
 173
 174static __init void
 175cris_ide_init(void)
 176{
 177        reg_ata_rw_ctrl0 ctrl0 = {0};
 178        reg_ata_rw_intr_mask intr_mask = {0};
 179
 180        ctrl0.en = regk_ata_yes;
 181        REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
 182
 183        intr_mask.bus0 = regk_ata_yes;
 184        intr_mask.bus1 = regk_ata_yes;
 185        intr_mask.bus2 = regk_ata_yes;
 186        intr_mask.bus3 = regk_ata_yes;
 187
 188        REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
 189
 190        crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
 191        crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
 192
 193        crisv32_pinmux_alloc_fixed(pinmux_ata);
 194        crisv32_pinmux_alloc_fixed(pinmux_ata0);
 195        crisv32_pinmux_alloc_fixed(pinmux_ata1);
 196        crisv32_pinmux_alloc_fixed(pinmux_ata2);
 197        crisv32_pinmux_alloc_fixed(pinmux_ata3);
 198
 199        DMA_RESET(regi_dma2);
 200        DMA_ENABLE(regi_dma2);
 201        DMA_RESET(regi_dma3);
 202        DMA_ENABLE(regi_dma3);
 203
 204        DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
 205        DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
 206}
 207
 208static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
 209
 210#define cris_dma_descr_type dma_descr_data
 211#define cris_pio_read regk_ata_rd
 212#define cris_ultra_mask 0x7
 213#define MAX_DESCR_SIZE 0xffffffffUL
 214
 215static unsigned long
 216cris_ide_get_reg(unsigned long reg)
 217{
 218        return (reg & 0x0e000000) >> 25;
 219}
 220
 221static void
 222cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
 223{
 224        d->buf = (char*)virt_to_phys(buf);
 225        d->after = d->buf + len;
 226        d->eol = last;
 227}
 228
 229static void
 230cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
 231{
 232        reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
 233        reg_ata_rw_trf_cnt trf_cnt = {0};
 234
 235        mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
 236        mycontext.saved_data_buf = d->buf;
 237        /* start the dma channel */
 238        DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
 239
 240        /* initiate a multi word dma read using PIO handshaking */
 241        trf_cnt.cnt = len >> 1;
 242        /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
 243        if (type == TYPE_UDMA)
 244                trf_cnt.cnt++;
 245        REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
 246
 247        ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
 248        ctrl2.trf_mode = regk_ata_dma;
 249        ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
 250                    type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
 251        ctrl2.multi = regk_ata_yes;
 252        ctrl2.dma_size = regk_ata_word;
 253        REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
 254}
 255
 256static void
 257cris_ide_wait_dma(int dir)
 258{
 259        reg_dma_rw_stat status;
 260        do
 261        {
 262                status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
 263        } while(status.list_state != regk_dma_data_at_eol);
 264}
 265
 266static int cris_dma_test_irq(ide_drive_t *drive)
 267{
 268        int intr = REG_RD_INT(ata, regi_ata, r_intr);
 269        reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
 270        return intr & (1 << ctrl2.sel) ? 1 : 0;
 271}
 272
 273static void cris_ide_initialize_dma(int dir)
 274{
 275}
 276
 277#else
 278/* CRISv10 specifics */
 279#include <asm/arch/svinto.h>
 280#include <asm/arch/io_interface_mux.h>
 281
 282/* PIO timing (in R_ATA_CONFIG)
 283 *
 284 *                        _____________________________
 285 * ADDRESS :     ________/
 286 *
 287 *                            _______________
 288 * DIOR    :     ____________/               \__________
 289 *
 290 *                               _______________
 291 * DATA    :     XXXXXXXXXXXXXXXX_______________XXXXXXXX
 292 *
 293 *
 294 * DIOR is unbuffered while address and data is buffered.
 295 * This creates two problems:
 296 * 1. The DIOR pulse is to early (because it is unbuffered)
 297 * 2. The rise time of DIOR is long
 298 *
 299 * There are at least three different plausible solutions
 300 * 1. Use a pad capable of larger currents in Etrax
 301 * 2. Use an external buffer
 302 * 3. Make the strobe pulse longer
 303 *
 304 * Some of the strobe timings below are modified to compensate
 305 * for this. This implies a slight performance decrease.
 306 *
 307 * THIS SHOULD NEVER BE CHANGED!
 308 *
 309 * TODO: Is this true for the latest LX boards still ?
 310 */
 311
 312#define ATA_UDMA2_CYC    0 /* No UDMA supported, just to make it compile. */
 313#define ATA_UDMA2_DVS    0
 314#define ATA_UDMA1_CYC    0
 315#define ATA_UDMA1_DVS    0
 316#define ATA_UDMA0_CYC    0
 317#define ATA_UDMA0_DVS    0
 318#define ATA_DMA2_STROBE  4
 319#define ATA_DMA2_HOLD    0
 320#define ATA_DMA1_STROBE  4
 321#define ATA_DMA1_HOLD    1
 322#define ATA_DMA0_STROBE 12
 323#define ATA_DMA0_HOLD    9
 324#define ATA_PIO4_SETUP   1
 325#define ATA_PIO4_STROBE  5
 326#define ATA_PIO4_HOLD    0
 327#define ATA_PIO3_SETUP   1
 328#define ATA_PIO3_STROBE  5
 329#define ATA_PIO3_HOLD    1
 330#define ATA_PIO2_SETUP   1
 331#define ATA_PIO2_STROBE  6
 332#define ATA_PIO2_HOLD    2
 333#define ATA_PIO1_SETUP   2
 334#define ATA_PIO1_STROBE 11
 335#define ATA_PIO1_HOLD    4
 336#define ATA_PIO0_SETUP   4
 337#define ATA_PIO0_STROBE 19
 338#define ATA_PIO0_HOLD    4
 339
 340int
 341cris_ide_ack_intr(ide_hwif_t* hwif)
 342{
 343        return 1;
 344}
 345
 346static inline int
 347cris_ide_busy(void)
 348{
 349        return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
 350}
 351
 352static inline int
 353cris_ide_ready(void)
 354{
 355        return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
 356}
 357
 358static inline int
 359cris_ide_data_available(unsigned short* data)
 360{
 361        unsigned long status = *R_ATA_STATUS_DATA;
 362        *data = (unsigned short)status;
 363        return status & IO_MASK(R_ATA_STATUS_DATA, dav);
 364}
 365
 366static void
 367cris_ide_write_command(unsigned long command)
 368{
 369        *R_ATA_CTRL_DATA = command;
 370}
 371
 372static void
 373cris_ide_set_speed(int type, int setup, int strobe, int hold)
 374{
 375        static int pio_setup = ATA_PIO4_SETUP;
 376        static int pio_strobe = ATA_PIO4_STROBE;
 377        static int pio_hold = ATA_PIO4_HOLD;
 378        static int dma_strobe = ATA_DMA2_STROBE;
 379        static int dma_hold = ATA_DMA2_HOLD;
 380
 381        if (type == TYPE_PIO) {
 382                pio_setup = setup;
 383                pio_strobe = strobe;
 384                pio_hold = hold;
 385        } else if (type == TYPE_DMA) {
 386                dma_strobe = strobe;
 387          dma_hold = hold;
 388        }
 389        *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
 390          IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
 391                IO_FIELD( R_ATA_CONFIG, dma_hold,   dma_hold ) |
 392                IO_FIELD( R_ATA_CONFIG, pio_setup,  pio_setup ) |
 393                IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
 394                IO_FIELD( R_ATA_CONFIG, pio_hold,   pio_hold ) );
 395}
 396
 397static unsigned long
 398cris_ide_base_address(int bus)
 399{
 400        return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
 401}
 402
 403static unsigned long
 404cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
 405{
 406        return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
 407               IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
 408               IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
 409}
 410
 411static __init void
 412cris_ide_reset(unsigned val)
 413{
 414#ifdef CONFIG_ETRAX_IDE_G27_RESET
 415        REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
 416#endif
 417#ifdef CONFIG_ETRAX_IDE_PB7_RESET
 418        port_pb_dir_shadow = port_pb_dir_shadow |
 419                IO_STATE(R_PORT_PB_DIR, dir7, output);
 420        *R_PORT_PB_DIR = port_pb_dir_shadow;
 421        REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
 422#endif
 423}
 424
 425static __init void
 426cris_ide_init(void)
 427{
 428        volatile unsigned int dummy;
 429
 430        *R_ATA_CTRL_DATA = 0;
 431        *R_ATA_TRANSFER_CNT = 0;
 432        *R_ATA_CONFIG = 0;
 433
 434        if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
 435                printk(KERN_CRIT "ide: Failed to get IO interface\n");
 436                return;
 437        } else if (cris_request_dma(ATA_TX_DMA_NBR,
 438                                          "ETRAX100LX IDE TX",
 439                                          DMA_VERBOSE_ON_ERROR,
 440                                          dma_ata)) {
 441                cris_free_io_interface(if_ata);
 442                printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
 443                return;
 444        } else if (cris_request_dma(ATA_RX_DMA_NBR,
 445                                          "ETRAX100LX IDE RX",
 446                                          DMA_VERBOSE_ON_ERROR,
 447                                          dma_ata)) {
 448                cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
 449                cris_free_io_interface(if_ata);
 450                printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
 451                return;
 452        }
 453
 454        /* make a dummy read to set the ata controller in a proper state */
 455        dummy = *R_ATA_STATUS_DATA;
 456
 457        *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
 458        *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw,   read) |
 459                             IO_FIELD( R_ATA_CTRL_DATA, addr, 1   ) );
 460
 461        while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
 462
 463        *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
 464                             IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
 465                             IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
 466                             IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
 467
 468        /* reset the dma channels we will use */
 469
 470        RESET_DMA(ATA_TX_DMA_NBR);
 471        RESET_DMA(ATA_RX_DMA_NBR);
 472        WAIT_DMA(ATA_TX_DMA_NBR);
 473        WAIT_DMA(ATA_RX_DMA_NBR);
 474}
 475
 476#define cris_dma_descr_type etrax_dma_descr
 477#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
 478#define cris_ultra_mask 0x0
 479#define MAX_DESCR_SIZE 0x10000UL
 480
 481static unsigned long
 482cris_ide_get_reg(unsigned long reg)
 483{
 484        return (reg & 0x0e000000) >> 25;
 485}
 486
 487static void
 488cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
 489{
 490        d->buf = virt_to_phys(buf);
 491        d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
 492        if (last)
 493                d->ctrl |= d_eol;
 494}
 495
 496static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
 497{
 498        unsigned long cmd;
 499
 500        if (dir) {
 501                /* need to do this before RX DMA due to a chip bug
 502                 * it is enough to just flush the part of the cache that
 503                 * corresponds to the buffers we start, but since HD transfers
 504                 * usually are more than 8 kB, it is easier to optimize for the
 505                 * normal case and just flush the entire cache. its the only
 506                 * way to be sure! (OB movie quote)
 507                 */
 508                flush_etrax_cache();
 509                *R_DMA_CH3_FIRST = virt_to_phys(d);
 510                *R_DMA_CH3_CMD   = IO_STATE(R_DMA_CH3_CMD, cmd, start);
 511
 512        } else {
 513                *R_DMA_CH2_FIRST = virt_to_phys(d);
 514                *R_DMA_CH2_CMD   = IO_STATE(R_DMA_CH2_CMD, cmd, start);
 515        }
 516
 517        /* initiate a multi word dma read using DMA handshaking */
 518
 519        *R_ATA_TRANSFER_CNT =
 520                IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
 521
 522        cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
 523        cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
 524                                  IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
 525        *R_ATA_CTRL_DATA =
 526                cmd |
 527                IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
 528                IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma)  |
 529                IO_STATE(R_ATA_CTRL_DATA, multi,    on)   |
 530                IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
 531}
 532
 533static void
 534cris_ide_wait_dma(int dir)
 535{
 536        if (dir)
 537                WAIT_DMA(ATA_RX_DMA_NBR);
 538        else
 539                WAIT_DMA(ATA_TX_DMA_NBR);
 540}
 541
 542static int cris_dma_test_irq(ide_drive_t *drive)
 543{
 544        int intr = *R_IRQ_MASK0_RD;
 545        int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG);
 546        return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
 547}
 548
 549
 550static void cris_ide_initialize_dma(int dir)
 551{
 552        if (dir)
 553        {
 554                RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
 555                WAIT_DMA(ATA_RX_DMA_NBR);
 556        }
 557        else
 558        {
 559                RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
 560                WAIT_DMA(ATA_TX_DMA_NBR);
 561        }
 562}
 563
 564#endif
 565
 566void
 567cris_ide_outw(unsigned short data, unsigned long reg) {
 568        int timeleft;
 569
 570        LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
 571
 572        /* note the lack of handling any timeouts. we stop waiting, but we don't
 573         * really notify anybody.
 574         */
 575
 576        timeleft = IDE_REGISTER_TIMEOUT;
 577        /* wait for busy flag */
 578        do {
 579                timeleft--;
 580        } while(timeleft && cris_ide_busy());
 581
 582        /*
 583         * Fall through at a timeout, so the ongoing command will be
 584         * aborted by the write below, which is expected to be a dummy
 585         * command to the command register.  This happens when a faulty
 586         * drive times out on a command.  See comment on timeout in
 587         * INB.
 588         */
 589        if(!timeleft)
 590                printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
 591
 592        cris_ide_write_command(reg|data); /* write data to the drive's register */
 593
 594        timeleft = IDE_REGISTER_TIMEOUT;
 595        /* wait for transmitter ready */
 596        do {
 597                timeleft--;
 598        } while(timeleft && !cris_ide_ready());
 599}
 600
 601void
 602cris_ide_outb(unsigned char data, unsigned long reg)
 603{
 604        cris_ide_outw(data, reg);
 605}
 606
 607void
 608cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
 609{
 610        cris_ide_outw(addr, port);
 611}
 612
 613unsigned short
 614cris_ide_inw(unsigned long reg) {
 615        int timeleft;
 616        unsigned short val;
 617
 618        timeleft = IDE_REGISTER_TIMEOUT;
 619        /* wait for busy flag */
 620        do {
 621                timeleft--;
 622        } while(timeleft && cris_ide_busy());
 623
 624        if(!timeleft) {
 625                /*
 626                 * If we're asked to read the status register, like for
 627                 * example when a command does not complete for an
 628                 * extended time, but the ATA interface is stuck in a
 629                 * busy state at the *ETRAX* ATA interface level (as has
 630                 * happened repeatedly with at least one bad disk), then
 631                 * the best thing to do is to pretend that we read
 632                 * "busy" in the status register, so the IDE driver will
 633                 * time-out, abort the ongoing command and perform a
 634                 * reset sequence.  Note that the subsequent OUT_BYTE
 635                 * call will also timeout on busy, but as long as the
 636                 * write is still performed, everything will be fine.
 637                 */
 638                if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
 639                        return BUSY_STAT;
 640                else
 641                        /* For other rare cases we assume 0 is good enough.  */
 642                        return 0;
 643        }
 644
 645        cris_ide_write_command(reg | cris_pio_read);
 646
 647        timeleft = IDE_REGISTER_TIMEOUT;
 648        /* wait for available */
 649        do {
 650                timeleft--;
 651        } while(timeleft && !cris_ide_data_available(&val));
 652
 653        if(!timeleft)
 654                return 0;
 655
 656        LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
 657
 658        return val;
 659}
 660
 661unsigned char
 662cris_ide_inb(unsigned long reg)
 663{
 664        return (unsigned char)cris_ide_inw(reg);
 665}
 666
 667static int cris_dma_end (ide_drive_t *drive);
 668static int cris_dma_setup (ide_drive_t *drive);
 669static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command);
 670static int cris_dma_test_irq(ide_drive_t *drive);
 671static void cris_dma_start(ide_drive_t *drive);
 672static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
 673static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
 674static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
 675static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
 676static int cris_dma_on (ide_drive_t *drive);
 677
 678static void cris_dma_off(ide_drive_t *drive)
 679{
 680}
 681
 682static void cris_set_pio_mode(ide_drive_t *drive, const u8 pio)
 683{
 684        int setup, strobe, hold;
 685
 686        switch(pio)
 687        {
 688                case 0:
 689                        setup = ATA_PIO0_SETUP;
 690                        strobe = ATA_PIO0_STROBE;
 691                        hold = ATA_PIO0_HOLD;
 692                        break;
 693                case 1:
 694                        setup = ATA_PIO1_SETUP;
 695                        strobe = ATA_PIO1_STROBE;
 696                        hold = ATA_PIO1_HOLD;
 697                        break;
 698                case 2:
 699                        setup = ATA_PIO2_SETUP;
 700                        strobe = ATA_PIO2_STROBE;
 701                        hold = ATA_PIO2_HOLD;
 702                        break;
 703                case 3:
 704                        setup = ATA_PIO3_SETUP;
 705                        strobe = ATA_PIO3_STROBE;
 706                        hold = ATA_PIO3_HOLD;
 707                        break;
 708                case 4:
 709                        setup = ATA_PIO4_SETUP;
 710                        strobe = ATA_PIO4_STROBE;
 711                        hold = ATA_PIO4_HOLD;
 712                        break;
 713                default:
 714                        return;
 715        }
 716
 717        cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
 718}
 719
 720static void cris_set_dma_mode(ide_drive_t *drive, const u8 speed)
 721{
 722        int cyc = 0, dvs = 0, strobe = 0, hold = 0;
 723
 724        switch(speed)
 725        {
 726                case XFER_UDMA_0:
 727                        cyc = ATA_UDMA0_CYC;
 728                        dvs = ATA_UDMA0_DVS;
 729                        break;
 730                case XFER_UDMA_1:
 731                        cyc = ATA_UDMA1_CYC;
 732                        dvs = ATA_UDMA1_DVS;
 733                        break;
 734                case XFER_UDMA_2:
 735                        cyc = ATA_UDMA2_CYC;
 736                        dvs = ATA_UDMA2_DVS;
 737                        break;
 738                case XFER_MW_DMA_0:
 739                        strobe = ATA_DMA0_STROBE;
 740                        hold = ATA_DMA0_HOLD;
 741                        break;
 742                case XFER_MW_DMA_1:
 743                        strobe = ATA_DMA1_STROBE;
 744                        hold = ATA_DMA1_HOLD;
 745                        break;
 746                case XFER_MW_DMA_2:
 747                        strobe = ATA_DMA2_STROBE;
 748                        hold = ATA_DMA2_HOLD;
 749                        break;
 750                default:
 751                        return;
 752        }
 753
 754        if (speed >= XFER_UDMA_0)
 755                cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
 756        else
 757                cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
 758}
 759
 760void __init
 761init_e100_ide (void)
 762{
 763        hw_regs_t hw;
 764        int ide_offsets[IDE_NR_PORTS];
 765        int h;
 766        int i;
 767
 768        printk("ide: ETRAX FS built-in ATA DMA controller\n");
 769
 770        for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
 771                ide_offsets[i] = cris_ide_reg_addr(i, 0, 1);
 772
 773        /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
 774        ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0);
 775
 776        for (h = 0; h < 4; h++) {
 777                ide_hwif_t *hwif = NULL;
 778
 779                ide_setup_ports(&hw, cris_ide_base_address(h),
 780                                ide_offsets,
 781                                0, 0, cris_ide_ack_intr,
 782                                ide_default_irq(0));
 783                ide_register_hw(&hw, NULL, 1, &hwif);
 784                if (hwif == NULL)
 785                        continue;
 786                hwif->mmio = 1;
 787                hwif->chipset = ide_etrax100;
 788                hwif->set_pio_mode = &cris_set_pio_mode;
 789                hwif->set_dma_mode = &cris_set_dma_mode;
 790                hwif->ata_input_data = &cris_ide_input_data;
 791                hwif->ata_output_data = &cris_ide_output_data;
 792                hwif->atapi_input_bytes = &cris_atapi_input_bytes;
 793                hwif->atapi_output_bytes = &cris_atapi_output_bytes;
 794                hwif->ide_dma_end = &cris_dma_end;
 795                hwif->dma_setup = &cris_dma_setup;
 796                hwif->dma_exec_cmd = &cris_dma_exec_cmd;
 797                hwif->ide_dma_test_irq = &cris_dma_test_irq;
 798                hwif->dma_start = &cris_dma_start;
 799                hwif->OUTB = &cris_ide_outb;
 800                hwif->OUTW = &cris_ide_outw;
 801                hwif->OUTBSYNC = &cris_ide_outbsync;
 802                hwif->INB = &cris_ide_inb;
 803                hwif->INW = &cris_ide_inw;
 804                hwif->dma_host_off = &cris_dma_off;
 805                hwif->dma_host_on = &cris_dma_on;
 806                hwif->dma_off_quietly = &cris_dma_off;
 807                hwif->cbl = ATA_CBL_PATA40;
 808                hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
 809                hwif->pio_mask = ATA_PIO4,
 810                hwif->drives[0].autotune = 1;
 811                hwif->drives[1].autotune = 1;
 812                hwif->ultra_mask = cris_ultra_mask;
 813                hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */
 814        }
 815
 816        /* Reset pulse */
 817        cris_ide_reset(0);
 818        udelay(25);
 819        cris_ide_reset(1);
 820
 821        cris_ide_init();
 822
 823        cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
 824        cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
 825        cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
 826}
 827
 828static int cris_dma_on (ide_drive_t *drive)
 829{
 830        return 0;
 831}
 832
 833
 834static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
 835
 836/*
 837 * The following routines are mainly used by the ATAPI drivers.
 838 *
 839 * These routines will round up any request for an odd number of bytes,
 840 * so if an odd bytecount is specified, be sure that there's at least one
 841 * extra byte allocated for the buffer.
 842 */
 843static void
 844cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
 845{
 846        D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
 847                 buffer, bytecount));
 848
 849        if(bytecount & 1) {
 850                printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
 851                bytecount++; /* to round off */
 852        }
 853
 854        /* setup DMA and start transfer */
 855
 856        cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
 857        cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
 858
 859        /* wait for completion */
 860        LED_DISK_READ(1);
 861        cris_ide_wait_dma(1);
 862        LED_DISK_READ(0);
 863}
 864
 865static void
 866cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
 867{
 868        D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
 869                 buffer, bytecount));
 870
 871        if(bytecount & 1) {
 872                printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
 873                bytecount++;
 874        }
 875
 876        cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
 877        cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
 878
 879        /* wait for completion */
 880
 881        LED_DISK_WRITE(1);
 882        LED_DISK_READ(1);
 883        cris_ide_wait_dma(0);
 884        LED_DISK_WRITE(0);
 885}
 886
 887/*
 888 * This is used for most PIO data transfers *from* the IDE interface
 889 */
 890static void
 891cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
 892{
 893        cris_atapi_input_bytes(drive, buffer, wcount << 2);
 894}
 895
 896/*
 897 * This is used for most PIO data transfers *to* the IDE interface
 898 */
 899static void
 900cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
 901{
 902        cris_atapi_output_bytes(drive, buffer, wcount << 2);
 903}
 904
 905/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
 906static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
 907static unsigned int ata_tot_size;
 908
 909/*
 910 * cris_ide_build_dmatable() prepares a dma request.
 911 * Returns 0 if all went okay, returns 1 otherwise.
 912 */
 913static int cris_ide_build_dmatable (ide_drive_t *drive)
 914{
 915        ide_hwif_t *hwif = drive->hwif;
 916        struct scatterlist* sg;
 917        struct request *rq  = drive->hwif->hwgroup->rq;
 918        unsigned long size, addr;
 919        unsigned int count = 0;
 920        int i = 0;
 921
 922        sg = hwif->sg_table;
 923
 924        ata_tot_size = 0;
 925
 926        ide_map_sg(drive, rq);
 927        i = hwif->sg_nents;
 928
 929        while(i) {
 930                /*
 931                 * Determine addr and size of next buffer area.  We assume that
 932                 * individual virtual buffers are always composed linearly in
 933                 * physical memory.  For example, we assume that any 8kB buffer
 934                 * is always composed of two adjacent physical 4kB pages rather
 935                 * than two possibly non-adjacent physical 4kB pages.
 936                 */
 937                /* group sequential buffers into one large buffer */
 938                addr = sg_phys(sg);
 939                size = sg_dma_len(sg);
 940                while (--i) {
 941                        sg = sg_next(sg);
 942                        if ((addr + size) != sg_phys(sg))
 943                                break;
 944                        size += sg_dma_len(sg);
 945                }
 946
 947                /* did we run out of descriptors? */
 948
 949                if(count >= MAX_DMA_DESCRS) {
 950                        printk("%s: too few DMA descriptors\n", drive->name);
 951                        return 1;
 952                }
 953
 954                /* however, this case is more difficult - rw_trf_cnt cannot be more
 955                   than 65536 words per transfer, so in that case we need to either
 956                   1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
 957                      the descriptors, or
 958                   2) simply do the request here, and get dma_intr to only ide_end_request on
 959                      those blocks that were actually set-up for transfer.
 960                */
 961
 962                if(ata_tot_size + size > 131072) {
 963                        printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
 964                        return 1;
 965                }
 966
 967                /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
 968                   don't handle size > 131072 only one split is necessary */
 969
 970                if(size > MAX_DESCR_SIZE) {
 971                        cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
 972                        count++;
 973                        ata_tot_size += MAX_DESCR_SIZE;
 974                        size -= MAX_DESCR_SIZE;
 975                        addr += MAX_DESCR_SIZE;
 976                }
 977
 978                cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
 979                count++;
 980                ata_tot_size += size;
 981        }
 982
 983        if (count) {
 984                /* return and say all is ok */
 985                return 0;
 986        }
 987
 988        printk("%s: empty DMA table?\n", drive->name);
 989        return 1;       /* let the PIO routines handle this weirdness */
 990}
 991
 992/*
 993 * cris_dma_intr() is the handler for disk read/write DMA interrupts
 994 */
 995static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
 996{
 997        LED_DISK_READ(0);
 998        LED_DISK_WRITE(0);
 999
1000        return ide_dma_intr(drive);
1001}
1002
1003/*
1004 * Functions below initiates/aborts DMA read/write operations on a drive.
1005 *
1006 * The caller is assumed to have selected the drive and programmed the drive's
1007 * sector address using CHS or LBA.  All that remains is to prepare for DMA
1008 * and then issue the actual read/write DMA/PIO command to the drive.
1009 *
1010 * For ATAPI devices, we just prepare for DMA and return. The caller should
1011 * then issue the packet command to the drive and call us again with
1012 * cris_dma_start afterwards.
1013 *
1014 * Returns 0 if all went well.
1015 * Returns 1 if DMA read/write could not be started, in which case
1016 * the caller should revert to PIO for the current request.
1017 */
1018
1019static int cris_dma_end(ide_drive_t *drive)
1020{
1021        drive->waiting_for_dma = 0;
1022        return 0;
1023}
1024
1025static int cris_dma_setup(ide_drive_t *drive)
1026{
1027        struct request *rq = drive->hwif->hwgroup->rq;
1028
1029        cris_ide_initialize_dma(!rq_data_dir(rq));
1030        if (cris_ide_build_dmatable (drive)) {
1031                ide_map_sg(drive, rq);
1032                return 1;
1033        }
1034
1035        drive->waiting_for_dma = 1;
1036        return 0;
1037}
1038
1039static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
1040{
1041        /* set the irq handler which will finish the request when DMA is done */
1042        ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL);
1043
1044        /* issue cmd to drive */
1045        cris_ide_outb(command, IDE_COMMAND_REG);
1046}
1047
1048static void cris_dma_start(ide_drive_t *drive)
1049{
1050        struct request *rq = drive->hwif->hwgroup->rq;
1051        int writing = rq_data_dir(rq);
1052        int type = TYPE_DMA;
1053
1054        if (drive->current_speed >= XFER_UDMA_0)
1055                type = TYPE_UDMA;
1056
1057        cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
1058
1059        if (writing) {
1060                LED_DISK_WRITE(1);
1061        } else {
1062                LED_DISK_READ(1);
1063        }
1064}
1065
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