LXR linux/include/asm-xtensa/pgtable.h

   1/*
   2 * linux/include/asm-xtensa/pgtable.h
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * Copyright (C) 2001 - 2005 Tensilica Inc.
   9 */
  10
  11#ifndef _XTENSA_PGTABLE_H
  12#define _XTENSA_PGTABLE_H
  13
  14#include <asm-generic/pgtable-nopmd.h>
  15#include <asm/page.h>
  16
  17/*
  18 * We only use two ring levels, user and kernel space.
  19 */
  20
  21#define USER_RING               1       /* user ring level */
  22#define KERNEL_RING             0       /* kernel ring level */
  23
  24/*
  25 * The Xtensa architecture port of Linux has a two-level page table system,
  26 * i.e. the logical three-level Linux page table layout are folded.
  27 * Each task has the following memory page tables:
  28 *
  29 *   PGD table (page directory), ie. 3rd-level page table:
  30 *      One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
  31 *      (Architectures that don't have the PMD folded point to the PMD tables)
  32 *
  33 *      The pointer to the PGD table for a given task can be retrieved from
  34 *      the task structure (struct task_struct*) t, e.g. current():
  35 *        (t->mm ? t->mm : t->active_mm)->pgd
  36 *
  37 *   PMD tables (page middle-directory), ie. 2nd-level page tables:
  38 *      Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
  39 *
  40 *   PTE tables (page table entry), ie. 1st-level page tables:
  41 *      One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
  42 *      invalid_pte_table for absent mappings.
  43 *
  44 * The individual pages are 4 kB big with special pages for the empty_zero_page.
  45 */
  46#define PGDIR_SHIFT     22
  47#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  48#define PGDIR_MASK      (~(PGDIR_SIZE-1))
  49
  50/*
  51 * Entries per page directory level: we use two-level, so
  52 * we don't really have any PMD directory physically.
  53 */
  54#define PTRS_PER_PTE            1024
  55#define PTRS_PER_PTE_SHIFT      10
  56#define PTRS_PER_PMD            1
  57#define PTRS_PER_PGD            1024
  58#define PGD_ORDER               0
  59#define PMD_ORDER               0
  60#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  61#define FIRST_USER_ADDRESS      0
  62#define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
  63
  64/* virtual memory area. We keep a distance to other memory regions to be
  65 * on the safe side. We also use this area for cache aliasing.
  66 */
  67
  68// FIXME: virtual memory area must be configuration-dependent
  69
  70#define VMALLOC_START           0xC0000000
  71#define VMALLOC_END             0xC7FF0000
  72
  73/* Xtensa Linux config PTE layout (when present):
  74 *      31-12:  PPN
  75 *      11-6:   Software
  76 *      5-4:    RING
  77 *      3-0:    CA
  78 *
  79 * Similar to the Alpha and MIPS ports, we need to keep track of the ref
  80 * and mod bits in software.  We have a software "you can read
  81 * from this page" bit, and a hardware one which actually lets the
  82 * process read from the page.  On the same token we have a software
  83 * writable bit and the real hardware one which actually lets the
  84 * process write to the page.
  85 *
  86 * See further below for PTE layout for swapped-out pages.
  87 */
  88
  89#define _PAGE_VALID             (1<<0)  /* hardware: page is accessible */
  90#define _PAGE_WRENABLE          (1<<1)  /* hardware: page is writable */
  91
  92/* None of these cache modes include MP coherency:  */
  93#define _PAGE_NO_CACHE          (0<<2)  /* bypass, non-speculative */
  94#if XCHAL_DCACHE_IS_WRITEBACK
  95# define _PAGE_WRITEBACK        (1<<2)  /* write back */
  96# define _PAGE_WRITETHRU        (2<<2)  /* write through */
  97#else
  98# define _PAGE_WRITEBACK        (1<<2)  /* assume write through */
  99# define _PAGE_WRITETHRU        (1<<2)
 100#endif
 101#define _PAGE_NOALLOC           (3<<2)  /* don't allocate cache,if not cached */
 102#define _CACHE_MASK             (3<<2)
 103
 104#define _PAGE_USER              (1<<4)  /* user access (ring=1) */
 105#define _PAGE_KERNEL            (0<<4)  /* kernel access (ring=0) */
 106
 107/* Software */
 108#define _PAGE_RW                (1<<6)  /* software: page writable */
 109#define _PAGE_DIRTY             (1<<7)  /* software: page dirty */
 110#define _PAGE_ACCESSED          (1<<8)  /* software: page accessed (read) */
 111#define _PAGE_FILE              (1<<9)  /* nonlinear file mapping*/
 112
 113#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _CACHE_MASK | _PAGE_DIRTY)
 114#define _PAGE_PRESENT   ( _PAGE_VALID | _PAGE_WRITEBACK | _PAGE_ACCESSED)
 115
 116#ifdef CONFIG_MMU
 117
 118# define PAGE_NONE      __pgprot(_PAGE_PRESENT)
 119# define PAGE_SHARED    __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_RW)
 120# define PAGE_COPY      __pgprot(_PAGE_PRESENT | _PAGE_USER)
 121# define PAGE_READONLY  __pgprot(_PAGE_PRESENT | _PAGE_USER)
 122# define PAGE_KERNEL    __pgprot(_PAGE_PRESENT | _PAGE_KERNEL | _PAGE_WRENABLE)
 123# define PAGE_INVALID   __pgprot(_PAGE_USER)
 124
 125# if (DCACHE_WAY_SIZE > PAGE_SIZE)
 126#  define PAGE_DIRECTORY  __pgprot(_PAGE_VALID | _PAGE_ACCESSED | _PAGE_KERNEL)
 127# else
 128#  define PAGE_DIRECTORY  __pgprot(_PAGE_PRESENT | _PAGE_KERNEL)
 129# endif
 130
 131#else /* no mmu */
 132
 133# define PAGE_NONE       __pgprot(0)
 134# define PAGE_SHARED     __pgprot(0)
 135# define PAGE_COPY       __pgprot(0)
 136# define PAGE_READONLY   __pgprot(0)
 137# define PAGE_KERNEL     __pgprot(0)
 138
 139#endif
 140
 141/*
 142 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 143 * the MMU can't do page protection for execute, and considers that the same as
 144 * read.  Also, write permissions may imply read permissions.
 145 * What follows is the closest we can get by reasonable means..
 146 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 147 */
 148#define __P000  PAGE_NONE       /* private --- */
 149#define __P001  PAGE_READONLY   /* private --r */
 150#define __P010  PAGE_COPY       /* private -w- */
 151#define __P011  PAGE_COPY       /* private -wr */
 152#define __P100  PAGE_READONLY   /* private x-- */
 153#define __P101  PAGE_READONLY   /* private x-r */
 154#define __P110  PAGE_COPY       /* private xw- */
 155#define __P111  PAGE_COPY       /* private xwr */
 156
 157#define __S000  PAGE_NONE       /* shared  --- */
 158#define __S001  PAGE_READONLY   /* shared  --r */
 159#define __S010  PAGE_SHARED     /* shared  -w- */
 160#define __S011  PAGE_SHARED     /* shared  -wr */
 161#define __S100  PAGE_READONLY   /* shared  x-- */
 162#define __S101  PAGE_READONLY   /* shared  x-r */
 163#define __S110  PAGE_SHARED     /* shared  xw- */
 164#define __S111  PAGE_SHARED     /* shared  xwr */
 165
 166#ifndef __ASSEMBLY__
 167
 168#define pte_ERROR(e) \
 169        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 170#define pgd_ERROR(e) \
 171        printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 172
 173extern unsigned long empty_zero_page[1024];
 174
 175#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 176
 177extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
 178
 179/*
 180 * The pmd contains the kernel virtual address of the pte page.
 181 */
 182#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
 183#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
 184
 185/*
 186 * The following only work if pte_present() is true.
 187 */
 188#define pte_none(pte)    (!(pte_val(pte) ^ _PAGE_USER))
 189#define pte_present(pte) (pte_val(pte) & _PAGE_VALID)
 190#define pte_clear(mm,addr,ptep)                                         \
 191        do { update_pte(ptep, __pte(_PAGE_USER)); } while(0)
 192
 193#define pmd_none(pmd)    (!pmd_val(pmd))
 194#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
 195#define pmd_clear(pmdp)  do { set_pmd(pmdp, __pmd(0)); } while (0)
 196#define pmd_bad(pmd)     (pmd_val(pmd) & ~PAGE_MASK)
 197
 198/* Note: We use the _PAGE_USER bit to indicate write-protect kernel memory */
 199
 200static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_USER; }
 201static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
 202static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
 203static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
 204static inline int pte_file(pte_t pte)  { return pte_val(pte) & _PAGE_FILE; }
 205static inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) &= ~(_PAGE_RW | _PAGE_WRENABLE); return pte; }
 206static inline pte_t pte_rdprotect(pte_t pte)    { pte_val(pte) &= ~_PAGE_USER; return pte; }
 207static inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
 208static inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 209static inline pte_t pte_mkread(pte_t pte)       { pte_val(pte) |= _PAGE_USER; return pte; }
 210static inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 211static inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 212static inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) |= _PAGE_RW; return pte; }
 213
 214/*
 215 * Conversion functions: convert a page and protection to a page entry,
 216 * and a page entry and page directory to the page they refer to.
 217 */
 218#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 219#define pte_same(a,b)           (pte_val(a) == pte_val(b))
 220#define pte_page(x)             pfn_to_page(pte_pfn(x))
 221#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 222#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 223
 224static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 225{
 226        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 227}
 228
 229/*
 230 * Certain architectures need to do special things when pte's
 231 * within a page table are directly modified.  Thus, the following
 232 * hook is made available.
 233 */
 234static inline void update_pte(pte_t *ptep, pte_t pteval)
 235{
 236        *ptep = pteval;
 237#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 238        __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (ptep));
 239#endif
 240}
 241
 242struct mm_struct;
 243
 244static inline void
 245set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
 246{
 247        update_pte(ptep, pteval);
 248}
 249
 250
 251static inline void
 252set_pmd(pmd_t *pmdp, pmd_t pmdval)
 253{
 254        *pmdp = pmdval;
 255#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 256        __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
 257#endif
 258}
 259
 260struct vm_area_struct;
 261
 262static inline int
 263ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
 264                          pte_t *ptep)
 265{
 266        pte_t pte = *ptep;
 267        if (!pte_young(pte))
 268                return 0;
 269        update_pte(ptep, pte_mkold(pte));
 270        return 1;
 271}
 272
 273static inline int
 274ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr,
 275                          pte_t *ptep)
 276{
 277        pte_t pte = *ptep;
 278        if (!pte_dirty(pte))
 279                return 0;
 280        update_pte(ptep, pte_mkclean(pte));
 281        return 1;
 282}
 283
 284static inline pte_t
 285ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 286{
 287        pte_t pte = *ptep;
 288        pte_clear(mm, addr, ptep);
 289        return pte;
 290}
 291
 292static inline void
 293ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 294{
 295        pte_t pte = *ptep;
 296        update_pte(ptep, pte_wrprotect(pte));
 297}
 298
 299/* to find an entry in a kernel page-table-directory */
 300#define pgd_offset_k(address)   pgd_offset(&init_mm, address)
 301
 302/* to find an entry in a page-table-directory */
 303#define pgd_offset(mm,address)  ((mm)->pgd + pgd_index(address))
 304
 305#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
 306
 307/* Find an entry in the second-level page table.. */
 308#define pmd_offset(dir,address) ((pmd_t*)(dir))
 309
 310/* Find an entry in the third-level page table.. */
 311#define pte_index(address)      (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 312#define pte_offset_kernel(dir,addr)                                     \
 313        ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
 314#define pte_offset_map(dir,addr)        pte_offset_kernel((dir),(addr))
 315#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
 316
 317#define pte_unmap(pte)          do { } while (0)
 318#define pte_unmap_nested(pte)   do { } while (0)
 319
 320
 321/*
 322 * Encode and decode a swap entry.
 323 * Each PTE in a process VM's page table is either:
 324 *   "present" -- valid and not swapped out, protection bits are meaningful;
 325 *   "not present" -- which further subdivides in these two cases:
 326 *      "none" -- no mapping at all; identified by pte_none(), set by pte_clear(
 327 *      "swapped out" -- the page is swapped out, and the SWP macros below
 328 *                      are used to store swap file info in the PTE itself.
 329 *
 330 * In the Xtensa processor MMU, any PTE entries in user space (or anywhere
 331 * in virtual memory that can map differently across address spaces)
 332 * must have a correct ring value that represents the RASID field that
 333 * is changed when switching address spaces.  Eg. such PTE entries cannot
 334 * be set to ring zero, because that can cause a (global) kernel ASID
 335 * entry to be created in the TLBs (even with invalid cache attribute),
 336 * potentially causing a multihit exception when going back to another
 337 * address space that mapped the same virtual address at another ring.
 338 *
 339 * SO: we avoid using ring bits (_PAGE_RING_MASK) in "not present" PTEs.
 340 * We also avoid using the _PAGE_VALID bit which must be zero for non-present
 341 * pages.
 342 *
 343 * We end up with the following available bits:  1..3 and 7..31.
 344 * We don't bother with 1..3 for now (we can use them later if needed),
 345 * and chose to allocate 6 bits for SWP_TYPE and the remaining 19 bits
 346 * for SWP_OFFSET.  At least 5 bits are needed for SWP_TYPE, because it
 347 * is currently implemented as an index into swap_info[MAX_SWAPFILES]
 348 * and MAX_SWAPFILES is currently defined as 32 in <linux/swap.h>.
 349 * However, for some reason all other architectures in the 2.4 kernel
 350 * reserve either 6, 7, or 8 bits so I'll not detract from that for now.  :)
 351 * SWP_OFFSET is an offset into the swap file in page-size units, so
 352 * with 4 kB pages, 19 bits supports a maximum swap file size of 2 GB.
 353 *
 354 * FIXME:  2 GB isn't very big.  Other bits can be used to allow
 355 * larger swap sizes.  In the meantime, it appears relatively easy to get
 356 * around the 2 GB limitation by simply using multiple swap files.
 357 */
 358
 359#define __swp_type(entry)       (((entry).val >> 7) & 0x3f)
 360#define __swp_offset(entry)     ((entry).val >> 13)
 361#define __swp_entry(type,offs)  ((swp_entry_t) {((type) << 7) | ((offs) << 13)})
 362#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 363#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 364
 365#define PTE_FILE_MAX_BITS       29
 366#define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 367#define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 368
 369
 370#endif /*  !defined (__ASSEMBLY__) */
 371
 372
 373#ifdef __ASSEMBLY__
 374
 375/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 376 *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 377 *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 378 *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 379 *
 380 * Note: We require an additional temporary register which can be the same as
 381 *       the register that holds the address.
 382 *
 383 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 384 *
 385 */
 386#define _PGD_INDEX(rt,rs)       extui   rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
 387#define _PTE_INDEX(rt,rs)       extui   rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
 388
 389#define _PGD_OFFSET(mm,adr,tmp)         l32i    mm, mm, MM_PGD;         \
 390                                        _PGD_INDEX(tmp, adr);           \
 391                                        addx4   mm, tmp, mm
 392
 393#define _PTE_OFFSET(pmd,adr,tmp)        _PTE_INDEX(tmp, adr);           \
 394                                        srli    pmd, pmd, PAGE_SHIFT;   \
 395                                        slli    pmd, pmd, PAGE_SHIFT;   \
 396                                        addx4   pmd, tmp, pmd
 397
 398#else
 399
 400extern void paging_init(void);
 401
 402#define kern_addr_valid(addr)   (1)
 403
 404extern  void update_mmu_cache(struct vm_area_struct * vma,
 405                              unsigned long address, pte_t pte);
 406
 407/*
 408 * remap a physical page `pfn' of size `size' with page protection `prot'
 409 * into virtual address `from'
 410 */
 411#define io_remap_pfn_range(vma,from,pfn,size,prot) \
 412                remap_pfn_range(vma, from, pfn, size, prot)
 413
 414
 415/* No page table caches to init */
 416
 417#define pgtable_cache_init()    do { } while (0)
 418
 419typedef pte_t *pte_addr_t;
 420
 421#endif /* !defined (__ASSEMBLY__) */
 422
 423#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 424#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 425#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 426#define __HAVE_ARCH_PTEP_SET_WRPROTECT
 427#define __HAVE_ARCH_PTEP_MKDIRTY
 428#define __HAVE_ARCH_PTE_SAME
 429
 430#include <asm-generic/pgtable.h>
 431
 432#endif /* _XTENSA_PGTABLE_H */
 433