LXR linux/arch/i386/pci/pci.h

   1/*
   2 *      Low-Level PCI Access for i386 machines.
   3 *
   4 *      (c) 1999 Martin Mares <mj@ucw.cz>
   5 */
   6
   7#undef DEBUG
   8
   9#ifdef DEBUG
  10#define DBG(x...) printk(x)
  11#else
  12#define DBG(x...)
  13#endif
  14
  15#define PCI_PROBE_BIOS          0x0001
  16#define PCI_PROBE_CONF1         0x0002
  17#define PCI_PROBE_CONF2         0x0004
  18#define PCI_PROBE_MMCONF        0x0008
  19#define PCI_PROBE_MASK          0x000f
  20#define PCI_PROBE_NOEARLY       0x0010
  21
  22#define PCI_NO_SORT             0x0100
  23#define PCI_BIOS_SORT           0x0200
  24#define PCI_NO_CHECKS           0x0400
  25#define PCI_USE_PIRQ_MASK       0x0800
  26#define PCI_ASSIGN_ROMS         0x1000
  27#define PCI_BIOS_IRQ_SCAN       0x2000
  28#define PCI_ASSIGN_ALL_BUSSES   0x4000
  29
  30extern unsigned int pci_probe;
  31extern unsigned long pirq_table_addr;
  32
  33enum pci_bf_sort_state {
  34        pci_bf_sort_default,
  35        pci_force_nobf,
  36        pci_force_bf,
  37        pci_dmi_bf,
  38};
  39
  40/* pci-i386.c */
  41
  42extern unsigned int pcibios_max_latency;
  43
  44void pcibios_resource_survey(void);
  45int pcibios_enable_resources(struct pci_dev *, int);
  46
  47/* pci-pc.c */
  48
  49extern int pcibios_last_bus;
  50extern struct pci_bus *pci_root_bus;
  51extern struct pci_ops pci_root_ops;
  52
  53/* pci-irq.c */
  54
  55struct irq_info {
  56        u8 bus, devfn;                  /* Bus, device and function */
  57        struct {
  58                u8 link;                /* IRQ line ID, chipset dependent, 0=not routed */
  59                u16 bitmap;             /* Available IRQs */
  60        } __attribute__((packed)) irq[4];
  61        u8 slot;                        /* Slot number, 0=onboard */
  62        u8 rfu;
  63} __attribute__((packed));
  64
  65struct irq_routing_table {
  66        u32 signature;                  /* PIRQ_SIGNATURE should be here */
  67        u16 version;                    /* PIRQ_VERSION */
  68        u16 size;                       /* Table size in bytes */
  69        u8 rtr_bus, rtr_devfn;          /* Where the interrupt router lies */
  70        u16 exclusive_irqs;             /* IRQs devoted exclusively to PCI usage */
  71        u16 rtr_vendor, rtr_device;     /* Vendor and device ID of interrupt router */
  72        u32 miniport_data;              /* Crap */
  73        u8 rfu[11];
  74        u8 checksum;                    /* Modulo 256 checksum must give zero */
  75        struct irq_info slots[0];
  76} __attribute__((packed));
  77
  78extern unsigned int pcibios_irq_mask;
  79
  80extern int pcibios_scanned;
  81extern spinlock_t pci_config_lock;
  82
  83extern int (*pcibios_enable_irq)(struct pci_dev *dev);
  84extern void (*pcibios_disable_irq)(struct pci_dev *dev);
  85
  86extern int pci_conf1_write(unsigned int seg, unsigned int bus,
  87                           unsigned int devfn, int reg, int len, u32 value);
  88extern int pci_conf1_read(unsigned int seg, unsigned int bus,
  89                          unsigned int devfn, int reg, int len, u32 *value);
  90
  91extern int pci_direct_probe(void);
  92extern void pci_direct_init(int type);
  93extern void pci_pcbios_init(void);
  94extern void pci_mmcfg_init(int type);
  95extern void pcibios_sort(void);
  96
  97/* pci-mmconfig.c */
  98
  99/* Verify the first 16 busses. We assume that systems with more busses
 100   get MCFG right. */
 101#define PCI_MMCFG_MAX_CHECK_BUS 16
 102extern DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
 103
 104extern int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
 105                                           unsigned int devfn);
 106extern int __init pci_mmcfg_arch_init(void);
 107