LXR linux/arch/i386/pci/mmconfig.c

   1/*
   2 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
   3 * Copyright (C) 2004 Intel Corp.
   4 *
   5 * This code is released under the GNU General Public License version 2.
   6 */
   7
   8/*
   9 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
  10 */
  11
  12#include <linux/pci.h>
  13#include <linux/init.h>
  14#include <linux/acpi.h>
  15#include <asm/e820.h>
  16#include "pci.h"
  17
  18/* Assume systems with more busses have correct MCFG */
  19#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
  20
  21/* The base address of the last MMCONFIG device accessed */
  22static u32 mmcfg_last_accessed_device;
  23static int mmcfg_last_accessed_cpu;
  24
  25/*
  26 * Functions for accessing PCI configuration space with MMCONFIG accesses
  27 */
  28static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
  29{
  30        struct acpi_mcfg_allocation *cfg;
  31        int cfg_num;
  32
  33        if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
  34            test_bit(PCI_SLOT(devfn) + 32*bus, pci_mmcfg_fallback_slots))
  35                return 0;
  36
  37        for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
  38                cfg = &pci_mmcfg_config[cfg_num];
  39                if (cfg->pci_segment == seg &&
  40                    (cfg->start_bus_number <= bus) &&
  41                    (cfg->end_bus_number >= bus))
  42                        return cfg->address;
  43        }
  44
  45        /* Fall back to type 0 */
  46        return 0;
  47}
  48
  49/*
  50 * This is always called under pci_config_lock
  51 */
  52static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
  53{
  54        u32 dev_base = base | (bus << 20) | (devfn << 12);
  55        int cpu = smp_processor_id();
  56        if (dev_base != mmcfg_last_accessed_device ||
  57            cpu != mmcfg_last_accessed_cpu) {
  58                mmcfg_last_accessed_device = dev_base;
  59                mmcfg_last_accessed_cpu = cpu;
  60                set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
  61        }
  62}
  63
  64static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
  65                          unsigned int devfn, int reg, int len, u32 *value)
  66{
  67        unsigned long flags;
  68        u32 base;
  69
  70        if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
  71                *value = -1;
  72                return -EINVAL;
  73        }
  74
  75        base = get_base_addr(seg, bus, devfn);
  76        if (!base)
  77                return pci_conf1_read(seg,bus,devfn,reg,len,value);
  78
  79        spin_lock_irqsave(&pci_config_lock, flags);
  80
  81        pci_exp_set_dev_base(base, bus, devfn);
  82
  83        switch (len) {
  84        case 1:
  85                *value = readb(mmcfg_virt_addr + reg);
  86                break;
  87        case 2:
  88                *value = readw(mmcfg_virt_addr + reg);
  89                break;
  90        case 4:
  91                *value = readl(mmcfg_virt_addr + reg);
  92                break;
  93        }
  94
  95        spin_unlock_irqrestore(&pci_config_lock, flags);
  96
  97        return 0;
  98}
  99
 100static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
 101                           unsigned int devfn, int reg, int len, u32 value)
 102{
 103        unsigned long flags;
 104        u32 base;
 105
 106        if ((bus > 255) || (devfn > 255) || (reg > 4095))
 107                return -EINVAL;
 108
 109        base = get_base_addr(seg, bus, devfn);
 110        if (!base)
 111                return pci_conf1_write(seg,bus,devfn,reg,len,value);
 112
 113        spin_lock_irqsave(&pci_config_lock, flags);
 114
 115        pci_exp_set_dev_base(base, bus, devfn);
 116
 117        switch (len) {
 118        case 1:
 119                writeb(value, mmcfg_virt_addr + reg);
 120                break;
 121        case 2:
 122                writew(value, mmcfg_virt_addr + reg);
 123                break;
 124        case 4:
 125                writel(value, mmcfg_virt_addr + reg);
 126                break;
 127        }
 128
 129        spin_unlock_irqrestore(&pci_config_lock, flags);
 130
 131        return 0;
 132}
 133
 134static struct pci_raw_ops pci_mmcfg = {
 135        .read =         pci_mmcfg_read,
 136        .write =        pci_mmcfg_write,
 137};
 138
 139int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
 140                                    unsigned int devfn)
 141{
 142        return get_base_addr(seg, bus, devfn) != 0;
 143}
 144
 145int __init pci_mmcfg_arch_init(void)
 146{
 147        printk(KERN_INFO "PCI: Using MMCONFIG\n");
 148        raw_pci_ops = &pci_mmcfg;
 149        return 1;
 150}
 151