LXR linux/include/asm-sh/irq.h

   1#ifndef __ASM_SH_IRQ_H
   2#define __ASM_SH_IRQ_H
   3
   4/*
   5 *
   6 * linux/include/asm-sh/irq.h
   7 *
   8 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   9 * Copyright (C) 2000  Kazumoto Kojima
  10 * Copyright (C) 2003  Paul Mundt
  11 *
  12 */
  13
  14#include <linux/config.h>
  15#include <asm/machvec.h>
  16#include <asm/ptrace.h>         /* for pt_regs */
  17
  18#if defined(CONFIG_SH_HP600) || \
  19    defined(CONFIG_SH_RTS7751R2D) || \
  20    defined(CONFIG_SH_HS7751RVOIP)
  21#include <asm/mach/ide.h>
  22#endif
  23
  24#if defined(CONFIG_CPU_SH3)
  25#define INTC_IPRA       0xfffffee2UL
  26#define INTC_IPRB       0xfffffee4UL
  27#elif defined(CONFIG_CPU_SH4)
  28#define INTC_IPRA       0xffd00004UL
  29#define INTC_IPRB       0xffd00008UL
  30#define INTC_IPRC       0xffd0000cUL
  31#define INTC_IPRD       0xffd00010UL
  32#endif
  33
  34#ifdef CONFIG_IDE
  35# ifndef IRQ_CFCARD
  36#  define IRQ_CFCARD    14
  37# endif
  38# ifndef IRQ_PCMCIA
  39#  define IRQ_PCMCIA    15
  40# endif
  41#endif
  42
  43#define TIMER_IRQ       16
  44#define TIMER_IPR_ADDR  INTC_IPRA
  45#define TIMER_IPR_POS    3
  46#define TIMER_PRIORITY   2
  47
  48#define TIMER1_IRQ      17
  49#define TIMER1_IPR_ADDR INTC_IPRA
  50#define TIMER1_IPR_POS   2
  51#define TIMER1_PRIORITY  4
  52
  53#define RTC_IRQ         22
  54#define RTC_IPR_ADDR    INTC_IPRA
  55#define RTC_IPR_POS      0
  56#define RTC_PRIORITY    TIMER_PRIORITY
  57
  58#if defined(CONFIG_CPU_SH3)
  59#define DMTE0_IRQ       48
  60#define DMTE1_IRQ       49
  61#define DMTE2_IRQ       50
  62#define DMTE3_IRQ       51
  63#define DMA_IPR_ADDR    INTC_IPRE
  64#define DMA_IPR_POS     3
  65#define DMA_PRIORITY    7
  66#if defined(CONFIG_CPU_SUBTYPE_SH7300)
  67/* TMU2 */
  68#define TIMER2_IRQ      18
  69#define TIMER2_IPR_ADDR INTC_IPRA
  70#define TIMER2_IPR_POS   1
  71#define TIMER2_PRIORITY  2
  72
  73/* WDT */
  74#define WDT_IRQ         27
  75#define WDT_IPR_ADDR    INTC_IPRB
  76#define WDT_IPR_POS      3
  77#define WDT_PRIORITY     2
  78
  79/* SIM (SIM Card Module) */
  80#define SIM_ERI_IRQ     23
  81#define SIM_RXI_IRQ     24
  82#define SIM_TXI_IRQ     25
  83#define SIM_TEND_IRQ    26
  84#define SIM_IPR_ADDR    INTC_IPRB
  85#define SIM_IPR_POS      1
  86#define SIM_PRIORITY     2
  87
  88/* VIO (Video I/O) */
  89#define VIO_IRQ         52
  90#define VIO_IPR_ADDR    INTC_IPRE
  91#define VIO_IPR_POS      2
  92#define VIO_PRIORITY     2
  93
  94/* MFI (Multi Functional Interface) */
  95#define MFI_IRQ         56
  96#define MFI_IPR_ADDR    INTC_IPRE
  97#define MFI_IPR_POS      1
  98#define MFI_PRIORITY     2
  99
 100/* VPU (Video Processing Unit) */
 101#define VPU_IRQ         60
 102#define VPU_IPR_ADDR    INTC_IPRE
 103#define VPU_IPR_POS      0
 104#define VPU_PRIORITY     2
 105
 106/* KEY (Key Scan Interface) */
 107#define KEY_IRQ         79
 108#define KEY_IPR_ADDR    INTC_IPRF
 109#define KEY_IPR_POS      3
 110#define KEY_PRIORITY     2
 111
 112/* CMT (Compare Match Timer) */
 113#define CMT_IRQ         104
 114#define CMT_IPR_ADDR    INTC_IPRF
 115#define CMT_IPR_POS      0
 116#define CMT_PRIORITY     2
 117
 118/* DMAC(1) */
 119#define DMTE0_IRQ       48
 120#define DMTE1_IRQ       49
 121#define DMTE2_IRQ       50
 122#define DMTE3_IRQ       51
 123#define DMA1_IPR_ADDR   INTC_IPRE
 124#define DMA1_IPR_POS    3
 125#define DMA1_PRIORITY   7
 126
 127/* DMAC(2) */
 128#define DMTE4_IRQ       76
 129#define DMTE5_IRQ       77
 130#define DMA2_IPR_ADDR   INTC_IPRF
 131#define DMA2_IPR_POS    2
 132#define DMA2_PRIORITY   7
 133
 134/* SIOF0 */
 135#define SIOF0_IRQ       84
 136#define SIOF0_IPR_ADDR  INTC_IPRH
 137#define SIOF0_IPR_POS   3
 138#define SIOF0_PRIORITY  3
 139
 140/* FLCTL (Flash Memory Controller) */
 141#define FLSTE_IRQ       92
 142#define FLTEND_IRQ      93
 143#define FLTRQ0_IRQ      94
 144#define FLTRQ1_IRQ      95
 145#define FLCTL_IPR_ADDR  INTC_IPRH
 146#define FLCTL_IPR_POS   1
 147#define FLCTL_PRIORITY  3
 148
 149/* IIC (IIC Bus Interface) */
 150#define IIC_ALI_IRQ     96
 151#define IIC_TACKI_IRQ   97
 152#define IIC_WAITI_IRQ   98
 153#define IIC_DTEI_IRQ    99
 154#define IIC_IPR_ADDR    INTC_IPRH
 155#define IIC_IPR_POS     0
 156#define IIC_PRIORITY    3
 157
 158/* SIO0 */
 159#define SIO0_IRQ        88
 160#define SIO0_IPR_ADDR   INTC_IPRI
 161#define SIO0_IPR_POS    3
 162#define SIO0_PRIORITY   3
 163
 164/* SIU (Sound Interface Unit) */
 165#define SIU_IRQ         108
 166#define SIU_IPR_ADDR    INTC_IPRJ
 167#define SIU_IPR_POS     1
 168#define SIU_PRIORITY    3
 169
 170#endif
 171#elif defined(CONFIG_CPU_SH4)
 172#define DMTE0_IRQ       34
 173#define DMTE1_IRQ       35
 174#define DMTE2_IRQ       36
 175#define DMTE3_IRQ       37
 176#define DMTE4_IRQ       44      /* 7751R only */
 177#define DMTE5_IRQ       45      /* 7751R only */
 178#define DMTE6_IRQ       46      /* 7751R only */
 179#define DMTE7_IRQ       47      /* 7751R only */
 180#define DMAE_IRQ        38
 181#define DMA_IPR_ADDR    INTC_IPRC
 182#define DMA_IPR_POS     2
 183#define DMA_PRIORITY    7
 184#endif
 185
 186#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
 187    defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
 188    defined (CONFIG_CPU_SUBTYPE_SH7751)
 189#define SCI_ERI_IRQ     23
 190#define SCI_RXI_IRQ     24
 191#define SCI_TXI_IRQ     25
 192#define SCI_IPR_ADDR    INTC_IPRB
 193#define SCI_IPR_POS     1
 194#define SCI_PRIORITY    3
 195#endif
 196
 197#if defined(CONFIG_CPU_SUBTYPE_SH7300)
 198#define SCIF0_IRQ       80
 199#define SCIF0_IPR_ADDR  INTC_IPRG
 200#define SCIF0_IPR_POS   3
 201#define SCIF0_PRIORITY  3
 202#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 203      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 204      defined(CONFIG_CPU_SUBTYPE_SH7709)
 205#define SCIF_ERI_IRQ    56
 206#define SCIF_RXI_IRQ    57
 207#define SCIF_BRI_IRQ    58
 208#define SCIF_TXI_IRQ    59
 209#define SCIF_IPR_ADDR   INTC_IPRE
 210#define SCIF_IPR_POS    1
 211#define SCIF_PRIORITY   3
 212
 213#define IRDA_ERI_IRQ    52
 214#define IRDA_RXI_IRQ    53
 215#define IRDA_BRI_IRQ    54
 216#define IRDA_TXI_IRQ    55
 217#define IRDA_IPR_ADDR   INTC_IPRE
 218#define IRDA_IPR_POS    2
 219#define IRDA_PRIORITY   3
 220#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 221      defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 222#define SCIF_ERI_IRQ    40
 223#define SCIF_RXI_IRQ    41
 224#define SCIF_BRI_IRQ    42
 225#define SCIF_TXI_IRQ    43
 226#define SCIF_IPR_ADDR   INTC_IPRC
 227#define SCIF_IPR_POS    1
 228#define SCIF_PRIORITY   3
 229#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 230#define SCIF1_ERI_IRQ   23
 231#define SCIF1_RXI_IRQ   24
 232#define SCIF1_BRI_IRQ   25
 233#define SCIF1_TXI_IRQ   26
 234#define SCIF1_IPR_ADDR  INTC_IPRB
 235#define SCIF1_IPR_POS   1
 236#define SCIF1_PRIORITY  3
 237#endif
 238#endif
 239
 240/* NR_IRQS is made from three components:
 241 *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
 242 *   2. PINT_NR_IRQS   - number of PINT interrupts
 243 *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
 244 */
 245
 246/* 1. ONCHIP_NR_IRQS */
 247#ifdef CONFIG_SH_GENERIC
 248# define ONCHIP_NR_IRQS 144
 249#else
 250# if defined(CONFIG_CPU_SUBTYPE_SH7604)
 251#  define ONCHIP_NR_IRQS 24     // Actually 21
 252# elif defined(CONFIG_CPU_SUBTYPE_SH7707)
 253#  define ONCHIP_NR_IRQS 64
 254#  define PINT_NR_IRQS   16
 255# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
 256#  define ONCHIP_NR_IRQS 32
 257# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 258       defined(CONFIG_CPU_SUBTYPE_SH7705)
 259#  define ONCHIP_NR_IRQS 64     // Actually 61
 260#  define PINT_NR_IRQS   16
 261# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
 262#  define ONCHIP_NR_IRQS 48     // Actually 44
 263# elif defined(CONFIG_CPU_SUBTYPE_SH7751)
 264#  define ONCHIP_NR_IRQS 72
 265# elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 266#  define ONCHIP_NR_IRQS 110
 267# elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 268#  define ONCHIP_NR_IRQS 72
 269# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 270#  define ONCHIP_NR_IRQS 144
 271# elif defined(CONFIG_CPU_SUBTYPE_SH7300)
 272#  define ONCHIP_NR_IRQS 109
 273# endif
 274#endif
 275
 276/* 2. PINT_NR_IRQS */
 277#ifdef CONFIG_SH_GENERIC
 278# define PINT_NR_IRQS 16
 279#else
 280# ifndef PINT_NR_IRQS
 281#  define PINT_NR_IRQS 0
 282# endif
 283#endif
 284
 285#if PINT_NR_IRQS > 0
 286# define PINT_IRQ_BASE  ONCHIP_NR_IRQS
 287#endif
 288
 289/* 3. OFFCHIP_NR_IRQS */
 290#ifdef CONFIG_SH_GENERIC
 291# define OFFCHIP_NR_IRQS 16
 292#else
 293# if defined(CONFIG_HD64461)
 294#  define OFFCHIP_NR_IRQS 18
 295# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
 296#  define OFFCHIP_NR_IRQS 48
 297# elif defined(CONFIG_HD64465)
 298#  define OFFCHIP_NR_IRQS 16
 299# elif defined (CONFIG_SH_EC3104)
 300#  define OFFCHIP_NR_IRQS 16
 301# elif defined (CONFIG_SH_DREAMCAST)
 302#  define OFFCHIP_NR_IRQS 96
 303# else
 304#  define OFFCHIP_NR_IRQS 0
 305# endif
 306#endif
 307
 308#if OFFCHIP_NR_IRQS > 0
 309# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
 310#endif
 311
 312/* NR_IRQS. 1+2+3 */
 313#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
 314
 315/* In a generic kernel, NR_IRQS is an upper bound, and we should use
 316 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
 317 */
 318#ifdef CONFIG_SH_GENERIC
 319# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
 320#else
 321# define ACTUAL_NR_IRQS NR_IRQS
 322#endif
 323
 324
 325extern void disable_irq(unsigned int);
 326extern void disable_irq_nosync(unsigned int);
 327extern void enable_irq(unsigned int);
 328
 329/*
 330 * Simple Mask Register Support
 331 */
 332extern void make_maskreg_irq(unsigned int irq);
 333extern unsigned short *irq_mask_register;
 334
 335/*
 336 * Function for "on chip support modules".
 337 */
 338extern void make_ipr_irq(unsigned int irq, unsigned int addr,
 339                         int pos,  int priority);
 340extern void make_imask_irq(unsigned int irq);
 341
 342#if defined(CONFIG_CPU_SUBTYPE_SH7300)
 343#undef INTC_IPRA
 344#undef INTC_IPRB
 345#define INTC_IPRA       0xA414FEE2UL
 346#define INTC_IPRB       0xA414FEE4UL
 347#define INTC_IPRC       0xA4140016UL
 348#define INTC_IPRD       0xA4140018UL
 349#define INTC_IPRE       0xA414001AUL
 350#define INTC_IPRF       0xA4080000UL
 351#define INTC_IPRG       0xA4080002UL
 352#define INTC_IPRH       0xA4080004UL
 353#define INTC_IPRI       0xA4080006UL
 354#define INTC_IPRJ       0xA4080008UL
 355
 356#define INTC_IMR0       0xA4080040UL
 357#define INTC_IMR1       0xA4080042UL
 358#define INTC_IMR2       0xA4080044UL
 359#define INTC_IMR3       0xA4080046UL
 360#define INTC_IMR4       0xA4080048UL
 361#define INTC_IMR5       0xA408004AUL
 362#define INTC_IMR6       0xA408004CUL
 363#define INTC_IMR7       0xA408004EUL
 364#define INTC_IMR8       0xA4080050UL
 365#define INTC_IMR9       0xA4080052UL
 366#define INTC_IMR10      0xA4080054UL
 367
 368#define INTC_IMCR0      0xA4080060UL
 369#define INTC_IMCR1      0xA4080062UL
 370#define INTC_IMCR2      0xA4080064UL
 371#define INTC_IMCR3      0xA4080066UL
 372#define INTC_IMCR4      0xA4080068UL
 373#define INTC_IMCR5      0xA408006AUL
 374#define INTC_IMCR6      0xA408006CUL
 375#define INTC_IMCR7      0xA408006EUL
 376#define INTC_IMCR8      0xA4080070UL
 377#define INTC_IMCR9      0xA4080072UL
 378#define INTC_IMCR10     0xA4080074UL
 379
 380#define INTC_ICR0       0xA414FEE0UL
 381#define INTC_ICR1       0xA4140010UL
 382
 383#define INTC_IRR0       0xA4140004UL
 384
 385#define PORT_PACR       0xA4050100UL
 386#define PORT_PBCR       0xA4050102UL
 387#define PORT_PCCR       0xA4050104UL
 388#define PORT_PDCR       0xA4050106UL
 389#define PORT_PECR       0xA4050108UL
 390#define PORT_PFCR       0xA405010AUL
 391#define PORT_PGCR       0xA405010CUL
 392#define PORT_PHCR       0xA405010EUL
 393#define PORT_PJCR       0xA4050110UL
 394#define PORT_PKCR       0xA4050112UL
 395#define PORT_PLCR       0xA4050114UL
 396#define PORT_SCPCR      0xA4050116UL
 397#define PORT_PMCR       0xA4050118UL
 398#define PORT_PNCR       0xA405011AUL
 399#define PORT_PQCR       0xA405011CUL
 400
 401#define PORT_PSELA      0xA4050140UL
 402#define PORT_PSELB      0xA4050142UL
 403#define PORT_PSELC      0xA4050144UL
 404
 405#define PORT_HIZCRA     0xA4050146UL
 406#define PORT_HIZCRB     0xA4050148UL
 407#define PORT_DRVCR      0xA4050150UL
 408
 409#define PORT_PADR       0xA4050120UL
 410#define PORT_PBDR       0xA4050122UL
 411#define PORT_PCDR       0xA4050124UL
 412#define PORT_PDDR       0xA4050126UL
 413#define PORT_PEDR       0xA4050128UL
 414#define PORT_PFDR       0xA405012AUL
 415#define PORT_PGDR       0xA405012CUL
 416#define PORT_PHDR       0xA405012EUL
 417#define PORT_PJDR       0xA4050130UL
 418#define PORT_PKDR       0xA4050132UL
 419#define PORT_PLDR       0xA4050134UL
 420#define PORT_SCPDR      0xA4050136UL
 421#define PORT_PMDR       0xA4050138UL
 422#define PORT_PNDR       0xA405013AUL
 423#define PORT_PQDR       0xA405013CUL
 424
 425#define IRQ0_IRQ        32
 426#define IRQ1_IRQ        33
 427#define IRQ2_IRQ        34
 428#define IRQ3_IRQ        35
 429#define IRQ4_IRQ        36
 430#define IRQ5_IRQ        37
 431
 432#define IRQ0_IPR_ADDR   INTC_IPRC
 433#define IRQ1_IPR_ADDR   INTC_IPRC
 434#define IRQ2_IPR_ADDR   INTC_IPRC
 435#define IRQ3_IPR_ADDR   INTC_IPRC
 436#define IRQ4_IPR_ADDR   INTC_IPRD
 437#define IRQ5_IPR_ADDR   INTC_IPRD
 438
 439#define IRQ0_IPR_POS    0
 440#define IRQ1_IPR_POS    1
 441#define IRQ2_IPR_POS    2
 442#define IRQ3_IPR_POS    3
 443#define IRQ4_IPR_POS    0
 444#define IRQ5_IPR_POS    1
 445
 446#define IRQ0_PRIORITY   1
 447#define IRQ1_PRIORITY   1
 448#define IRQ2_PRIORITY   1
 449#define IRQ3_PRIORITY   1
 450#define IRQ4_PRIORITY   1
 451#define IRQ5_PRIORITY   1
 452
 453extern int ipr_irq_demux(int irq);
 454#define __irq_demux(irq) ipr_irq_demux(irq)
 455
 456#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
 457#define INTC_IPRA       0xfffffee2UL
 458#define INTC_IPRB       0xfffffe60UL
 459
 460#define INTC_VCRA       0xfffffe62UL
 461#define INTC_VCRB       0xfffffe64UL
 462#define INTC_VCRC       0xfffffe66UL
 463#define INTC_VCRD       0xfffffe68UL
 464
 465#define INTC_VCRWDT     0xfffffee4UL
 466#define INTC_VCRDIV     0xffffff0cUL
 467#define INTC_VCRDMA0    0xffffffa0UL
 468#define INTC_VCRDMA1    0xffffffa8UL
 469
 470#define INTC_ICR        0xfffffee0UL
 471#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 472      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 473      defined(CONFIG_CPU_SUBTYPE_SH7709)
 474#define INTC_IRR0       0xa4000004UL
 475#define INTC_IRR1       0xa4000006UL
 476#define INTC_IRR2       0xa4000008UL
 477
 478#define INTC_ICR0       0xfffffee0UL
 479#define INTC_ICR1       0xa4000010UL
 480#define INTC_ICR2       0xa4000012UL
 481#define INTC_INTER      0xa4000014UL
 482
 483#define INTC_IPRC       0xa4000016UL
 484#define INTC_IPRD       0xa4000018UL
 485#define INTC_IPRE       0xa400001aUL
 486#if defined(CONFIG_CPU_SUBTYPE_SH7707)
 487#define INTC_IPRF       0xa400001cUL
 488#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 489#define INTC_IPRF       0xa4080000UL
 490#define INTC_IPRG       0xa4080002UL
 491#define INTC_IPRH       0xa4080004UL
 492#endif
 493
 494#define PORT_PACR       0xa4000100UL
 495#define PORT_PBCR       0xa4000102UL
 496#define PORT_PCCR       0xa4000104UL
 497#define PORT_PFCR       0xa400010aUL
 498#define PORT_PADR       0xa4000120UL
 499#define PORT_PBDR       0xa4000122UL
 500#define PORT_PCDR       0xa4000124UL
 501#define PORT_PFDR       0xa400012aUL
 502
 503#define IRQ0_IRQ        32
 504#define IRQ1_IRQ        33
 505#define IRQ2_IRQ        34
 506#define IRQ3_IRQ        35
 507#define IRQ4_IRQ        36
 508#define IRQ5_IRQ        37
 509
 510#define IRQ0_IPR_ADDR   INTC_IPRC
 511#define IRQ1_IPR_ADDR   INTC_IPRC
 512#define IRQ2_IPR_ADDR   INTC_IPRC
 513#define IRQ3_IPR_ADDR   INTC_IPRC
 514#define IRQ4_IPR_ADDR   INTC_IPRD
 515#define IRQ5_IPR_ADDR   INTC_IPRD
 516
 517#define IRQ0_IPR_POS    0
 518#define IRQ1_IPR_POS    1
 519#define IRQ2_IPR_POS    2
 520#define IRQ3_IPR_POS    3
 521#define IRQ4_IPR_POS    0
 522#define IRQ5_IPR_POS    1
 523
 524#define IRQ0_PRIORITY   1
 525#define IRQ1_PRIORITY   1
 526#define IRQ2_PRIORITY   1
 527#define IRQ3_PRIORITY   1
 528#define IRQ4_PRIORITY   1
 529#define IRQ5_PRIORITY   1
 530
 531#define PINT0_IRQ       40
 532#define PINT8_IRQ       41
 533
 534#define PINT0_IPR_ADDR  INTC_IPRD
 535#define PINT8_IPR_ADDR  INTC_IPRD
 536
 537#define PINT0_IPR_POS   3
 538#define PINT8_IPR_POS   2
 539#define PINT0_PRIORITY  2
 540#define PINT8_PRIORITY  2
 541
 542extern int ipr_irq_demux(int irq);
 543#define __irq_demux(irq) ipr_irq_demux(irq)
 544
 545#else
 546#define __irq_demux(irq) irq
 547#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
 548
 549#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 550    defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 551#define INTC_ICR        0xffd00000
 552#define INTC_ICR_NMIL   (1<<15)
 553#define INTC_ICR_MAI    (1<<14)
 554#define INTC_ICR_NMIB   (1<<9)
 555#define INTC_ICR_NMIE   (1<<8)
 556#define INTC_ICR_IRLM   (1<<7)
 557#endif
 558
 559#ifdef CONFIG_CPU_SUBTYPE_ST40STB1
 560
 561#define INTC2_FIRST_IRQ 64
 562#define NR_INTC2_IRQS 25
 563
 564#define INTC2_BASE      0xfe080000
 565#define INTC2_INTC2MODE (INTC2_BASE+0x80)
 566
 567#define INTC2_INTPRI_OFFSET     0x00
 568#define INTC2_INTREQ_OFFSET     0x20
 569#define INTC2_INTMSK_OFFSET     0x40
 570#define INTC2_INTMSKCLR_OFFSET  0x60
 571
 572void make_intc2_irq(unsigned int irq,
 573                    unsigned int ipr_offset, unsigned int ipr_shift,
 574                    unsigned int msk_offset, unsigned int msk_shift,
 575                    unsigned int priority);
 576void init_IRQ_intc2(void);
 577void intc2_add_clear_irq(int irq, int (*fn)(int));
 578
 579#endif  /* CONFIG_CPU_SUBTYPE_ST40STB1 */
 580
 581static inline int generic_irq_demux(int irq)
 582{
 583        return irq;
 584}
 585
 586#define irq_canonicalize(irq)   (irq)
 587#define irq_demux(irq)          __irq_demux(sh_mv.mv_irq_demux(irq))
 588
 589struct irqaction;
 590struct pt_regs;
 591int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
 592
 593#if defined(CONFIG_CPU_SUBTYPE_SH73180)
 594#include <asm/irq-sh73180.h>
 595#endif
 596
 597#endif /* __ASM_SH_IRQ_H */
 598