LXR linux/include/asm-parisc/pgtable.h

   1#ifndef _PARISC_PGTABLE_H
   2#define _PARISC_PGTABLE_H
   3
   4#include <asm-generic/4level-fixup.h>
   5
   6#include <linux/config.h>
   7#include <asm/fixmap.h>
   8
   9#ifndef __ASSEMBLY__
  10/*
  11 * we simulate an x86-style page table for the linux mm code
  12 */
  13
  14#include <linux/spinlock.h>
  15#include <asm/processor.h>
  16#include <asm/cache.h>
  17#include <asm/bitops.h>
  18
  19/*
  20 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
  21 * memory.  For the return value to be meaningful, ADDR must be >=
  22 * PAGE_OFFSET.  This operation can be relatively expensive (e.g.,
  23 * require a hash-, or multi-level tree-lookup or something of that
  24 * sort) but it guarantees to return TRUE only if accessing the page
  25 * at that address does not cause an error.  Note that there may be
  26 * addresses for which kern_addr_valid() returns FALSE even though an
  27 * access would not cause an error (e.g., this is typically true for
  28 * memory mapped I/O regions.
  29 *
  30 * XXX Need to implement this for parisc.
  31 */
  32#define kern_addr_valid(addr)   (1)
  33
  34/* Certain architectures need to do special things when PTEs
  35 * within a page table are directly modified.  Thus, the following
  36 * hook is made available.
  37 */
  38#define set_pte(pteptr, pteval)                                 \
  39        do{                                                     \
  40                *(pteptr) = (pteval);                           \
  41        } while(0)
  42
  43#endif /* !__ASSEMBLY__ */
  44
  45#define pte_ERROR(e) \
  46        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
  47#define pmd_ERROR(e) \
  48        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
  49#define pgd_ERROR(e) \
  50        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
  51
  52 /* Note: If you change ISTACK_SIZE, you need to change the corresponding
  53  * values in vmlinux.lds and vmlinux64.lds (init_istack section). Also,
  54  * the "order" and size need to agree.
  55  */
  56
  57#define  ISTACK_SIZE  32768 /* Interrupt Stack Size */
  58#define  ISTACK_ORDER 3
  59
  60/* This is the size of the initially mapped kernel memory (i.e. currently
  61 * 0 to 1<<23 == 8MB */
  62#ifdef CONFIG_64BIT
  63#define KERNEL_INITIAL_ORDER    24
  64#else
  65#define KERNEL_INITIAL_ORDER    23
  66#endif
  67#define KERNEL_INITIAL_SIZE     (1 << KERNEL_INITIAL_ORDER)
  68
  69#ifdef CONFIG_64BIT
  70#define PT_NLEVELS      3
  71#define PGD_ORDER       1 /* Number of pages per pgd */
  72#define PMD_ORDER       1 /* Number of pages per pmd */
  73#define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
  74#else
  75#define PT_NLEVELS      2
  76#define PGD_ORDER       1 /* Number of pages per pgd */
  77#define PGD_ALLOC_ORDER PGD_ORDER
  78#endif
  79
  80/* Definitions for 3rd level (we use PLD here for Page Lower directory
  81 * because PTE_SHIFT is used lower down to mean shift that has to be
  82 * done to get usable bits out of the PTE) */
  83#define PLD_SHIFT       PAGE_SHIFT
  84#define PLD_SIZE        PAGE_SIZE
  85#define BITS_PER_PTE    (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
  86#define PTRS_PER_PTE    (1UL << BITS_PER_PTE)
  87
  88/* Definitions for 2nd level */
  89#define pgtable_cache_init()    do { } while (0)
  90
  91#define PMD_SHIFT       (PLD_SHIFT + BITS_PER_PTE)
  92#define PMD_SIZE        (1UL << PMD_SHIFT)
  93#define PMD_MASK        (~(PMD_SIZE-1))
  94#if PT_NLEVELS == 3
  95#define BITS_PER_PMD    (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
  96#else
  97#define BITS_PER_PMD    0
  98#endif
  99#define PTRS_PER_PMD    (1UL << BITS_PER_PMD)
 100
 101/* Definitions for 1st level */
 102#define PGDIR_SHIFT     (PMD_SHIFT + BITS_PER_PMD)
 103#define BITS_PER_PGD    (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
 104#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 105#define PGDIR_MASK      (~(PGDIR_SIZE-1))
 106#define PTRS_PER_PGD    (1UL << BITS_PER_PGD)
 107#define USER_PTRS_PER_PGD       PTRS_PER_PGD
 108
 109#define MAX_ADDRBITS    (PGDIR_SHIFT + BITS_PER_PGD)
 110#define MAX_ADDRESS     (1UL << MAX_ADDRBITS)
 111
 112#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
 113
 114/* This calculates the number of initial pages we need for the initial
 115 * page tables */
 116#define PT_INITIAL      (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
 117
 118/*
 119 * pgd entries used up by user/kernel:
 120 */
 121
 122#define FIRST_USER_PGD_NR       0
 123
 124#ifndef __ASSEMBLY__
 125extern  void *vmalloc_start;
 126#define PCXL_DMA_MAP_SIZE   (8*1024*1024)
 127#define VMALLOC_START   ((unsigned long)vmalloc_start)
 128/* this is a fixmap remnant, see fixmap.h */
 129#define VMALLOC_END     (KERNEL_MAP_END)
 130#endif
 131
 132/* NB: The tlb miss handlers make certain assumptions about the order */
 133/*     of the following bits, so be careful (One example, bits 25-31  */
 134/*     are moved together in one instruction).                        */
 135
 136#define _PAGE_READ_BIT     31   /* (0x001) read access allowed */
 137#define _PAGE_WRITE_BIT    30   /* (0x002) write access allowed */
 138#define _PAGE_EXEC_BIT     29   /* (0x004) execute access allowed */
 139#define _PAGE_GATEWAY_BIT  28   /* (0x008) privilege promotion allowed */
 140#define _PAGE_DMB_BIT      27   /* (0x010) Data Memory Break enable (B bit) */
 141#define _PAGE_DIRTY_BIT    26   /* (0x020) Page Dirty (D bit) */
 142#define _PAGE_FILE_BIT  _PAGE_DIRTY_BIT /* overload this bit */
 143#define _PAGE_REFTRAP_BIT  25   /* (0x040) Page Ref. Trap enable (T bit) */
 144#define _PAGE_NO_CACHE_BIT 24   /* (0x080) Uncached Page (U bit) */
 145#define _PAGE_ACCESSED_BIT 23   /* (0x100) Software: Page Accessed */
 146#define _PAGE_PRESENT_BIT  22   /* (0x200) Software: translation valid */
 147#define _PAGE_FLUSH_BIT    21   /* (0x400) Software: translation valid */
 148                                /*             for cache flushing only */
 149#define _PAGE_USER_BIT     20   /* (0x800) Software: User accessible page */
 150
 151/* N.B. The bits are defined in terms of a 32 bit word above, so the */
 152/*      following macro is ok for both 32 and 64 bit.                */
 153
 154#define xlate_pabit(x) (31 - x)
 155
 156/* this defines the shift to the usable bits in the PTE it is set so
 157 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
 158 * to zero */
 159#define PTE_SHIFT               xlate_pabit(_PAGE_USER_BIT)
 160
 161/* this is how many bits may be used by the file functions */
 162#define PTE_FILE_MAX_BITS       (BITS_PER_LONG - PTE_SHIFT)
 163
 164#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
 165#define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE })
 166
 167#define _PAGE_READ     (1 << xlate_pabit(_PAGE_READ_BIT))
 168#define _PAGE_WRITE    (1 << xlate_pabit(_PAGE_WRITE_BIT))
 169#define _PAGE_RW       (_PAGE_READ | _PAGE_WRITE)
 170#define _PAGE_EXEC     (1 << xlate_pabit(_PAGE_EXEC_BIT))
 171#define _PAGE_GATEWAY  (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
 172#define _PAGE_DMB      (1 << xlate_pabit(_PAGE_DMB_BIT))
 173#define _PAGE_DIRTY    (1 << xlate_pabit(_PAGE_DIRTY_BIT))
 174#define _PAGE_REFTRAP  (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
 175#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
 176#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
 177#define _PAGE_PRESENT  (1 << xlate_pabit(_PAGE_PRESENT_BIT))
 178#define _PAGE_FLUSH    (1 << xlate_pabit(_PAGE_FLUSH_BIT))
 179#define _PAGE_USER     (1 << xlate_pabit(_PAGE_USER_BIT))
 180#define _PAGE_FILE     (1 << xlate_pabit(_PAGE_FILE_BIT))
 181
 182#define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE |  _PAGE_DIRTY | _PAGE_ACCESSED)
 183#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 184#define _PAGE_KERNEL    (_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
 185
 186/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
 187 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
 188 * for a few meta-information bits, so we shift the address to be
 189 * able to effectively address 40-bits of physical address space. */
 190#define _PxD_PRESENT_BIT   31
 191#define _PxD_ATTACHED_BIT  30
 192#define _PxD_VALID_BIT     29
 193
 194#define PxD_FLAG_PRESENT  (1 << xlate_pabit(_PxD_PRESENT_BIT))
 195#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
 196#define PxD_FLAG_VALID    (1 << xlate_pabit(_PxD_VALID_BIT))
 197#define PxD_FLAG_MASK     (0xf)
 198#define PxD_FLAG_SHIFT    (4)
 199#define PxD_VALUE_SHIFT   (8)
 200
 201#ifndef __ASSEMBLY__
 202
 203#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
 204#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
 205/* Others seem to make this executable, I don't know if that's correct
 206   or not.  The stack is mapped this way though so this is necessary
 207   in the short term - dhd@linuxcare.com, 2000-08-08 */
 208#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
 209#define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
 210#define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
 211#define PAGE_COPY       PAGE_EXECREAD
 212#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
 213#define PAGE_KERNEL     __pgprot(_PAGE_KERNEL)
 214#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
 215#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
 216#define PAGE_GATEWAY    __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
 217#define PAGE_FLUSH      __pgprot(_PAGE_FLUSH)
 218
 219
 220/*
 221 * We could have an execute only page using "gateway - promote to priv
 222 * level 3", but that is kind of silly. So, the way things are defined
 223 * now, we must always have read permission for pages with execute
 224 * permission. For the fun of it we'll go ahead and support write only
 225 * pages.
 226 */
 227
 228         /*xwr*/
 229#define __P000  PAGE_NONE
 230#define __P001  PAGE_READONLY
 231#define __P010  __P000 /* copy on write */
 232#define __P011  __P001 /* copy on write */
 233#define __P100  PAGE_EXECREAD
 234#define __P101  PAGE_EXECREAD
 235#define __P110  __P100 /* copy on write */
 236#define __P111  __P101 /* copy on write */
 237
 238#define __S000  PAGE_NONE
 239#define __S001  PAGE_READONLY
 240#define __S010  PAGE_WRITEONLY
 241#define __S011  PAGE_SHARED
 242#define __S100  PAGE_EXECREAD
 243#define __S101  PAGE_EXECREAD
 244#define __S110  PAGE_RWX
 245#define __S111  PAGE_RWX
 246
 247extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
 248
 249/* initial page tables for 0-8MB for kernel */
 250
 251extern pte_t pg0[];
 252
 253/* zero page used for uninitialized stuff */
 254
 255extern unsigned long *empty_zero_page;
 256
 257/*
 258 * ZERO_PAGE is a global shared page that is always zero: used
 259 * for zero-mapped memory areas etc..
 260 */
 261
 262#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 263
 264#define pte_none(x)     ((pte_val(x) == 0) || (pte_val(x) & _PAGE_FLUSH))
 265#define pte_present(x)  (pte_val(x) & _PAGE_PRESENT)
 266#define pte_clear(xp)   do { pte_val(*(xp)) = 0; } while (0)
 267
 268#define pmd_flag(x)     (pmd_val(x) & PxD_FLAG_MASK)
 269#define pmd_address(x)  ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
 270#define pgd_flag(x)     (pgd_val(x) & PxD_FLAG_MASK)
 271#define pgd_address(x)  ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
 272
 273#ifdef CONFIG_64BIT
 274/* The first entry of the permanent pmd is not there if it contains
 275 * the gateway marker */
 276#define pmd_none(x)     (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
 277#else
 278#define pmd_none(x)     (!pmd_val(x))
 279#endif
 280#define pmd_bad(x)      (!(pmd_flag(x) & PxD_FLAG_VALID))
 281#define pmd_present(x)  (pmd_flag(x) & PxD_FLAG_PRESENT)
 282static inline void pmd_clear(pmd_t *pmd) {
 283#ifdef CONFIG_64BIT
 284        if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
 285                /* This is the entry pointing to the permanent pmd
 286                 * attached to the pgd; cannot clear it */
 287                __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
 288        else
 289#endif
 290                __pmd_val_set(*pmd,  0);
 291}
 292
 293
 294
 295#if PT_NLEVELS == 3
 296#define pgd_page(pgd) ((unsigned long) __va(pgd_address(pgd)))
 297
 298/* For 64 bit we have three level tables */
 299
 300#define pgd_none(x)     (!pgd_val(x))
 301#define pgd_bad(x)      (!(pgd_flag(x) & PxD_FLAG_VALID))
 302#define pgd_present(x)  (pgd_flag(x) & PxD_FLAG_PRESENT)
 303static inline void pgd_clear(pgd_t *pgd) {
 304#ifdef CONFIG_64BIT
 305        if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
 306                /* This is the permanent pmd attached to the pgd; cannot
 307                 * free it */
 308                return;
 309#endif
 310        __pgd_val_set(*pgd, 0);
 311}
 312#else
 313/*
 314 * The "pgd_xxx()" functions here are trivial for a folded two-level
 315 * setup: the pgd is never bad, and a pmd always exists (as it's folded
 316 * into the pgd entry)
 317 */
 318extern inline int pgd_none(pgd_t pgd)           { return 0; }
 319extern inline int pgd_bad(pgd_t pgd)            { return 0; }
 320extern inline int pgd_present(pgd_t pgd)        { return 1; }
 321extern inline void pgd_clear(pgd_t * pgdp)      { }
 322#endif
 323
 324/*
 325 * The following only work if pte_present() is true.
 326 * Undefined behaviour if not..
 327 */
 328extern inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_READ; }
 329extern inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 330extern inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 331extern inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_WRITE; }
 332extern inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 333extern inline int pte_user(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 334
 335extern inline pte_t pte_rdprotect(pte_t pte)    { pte_val(pte) &= ~_PAGE_READ; return pte; }
 336extern inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
 337extern inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 338extern inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
 339extern inline pte_t pte_mkread(pte_t pte)       { pte_val(pte) |= _PAGE_READ; return pte; }
 340extern inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 341extern inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 342extern inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) |= _PAGE_WRITE; return pte; }
 343
 344/*
 345 * Conversion functions: convert a page and protection to a page entry,
 346 * and a page entry and page directory to the page they refer to.
 347 */
 348#define __mk_pte(addr,pgprot) \
 349({                                                                      \
 350        pte_t __pte;                                                    \
 351                                                                        \
 352        pte_val(__pte) = ((addr)+pgprot_val(pgprot));                   \
 353                                                                        \
 354        __pte;                                                          \
 355})
 356
 357#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 358
 359static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 360{
 361        pte_t pte;
 362        pte_val(pte) = (pfn << PAGE_SHIFT) | pgprot_val(pgprot);
 363        return pte;
 364}
 365
 366/* This takes a physical page address that is used by the remapping functions */
 367#define mk_pte_phys(physpage, pgprot) \
 368({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
 369
 370extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 371{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
 372
 373/* Permanent address of a page.  On parisc we don't have highmem. */
 374
 375#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
 376
 377#define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
 378
 379#define pmd_page_kernel(pmd)    ((unsigned long) __va(pmd_address(pmd)))
 380
 381#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
 382#define pmd_page(pmd)   virt_to_page((void *)__pmd_page(pmd))
 383
 384#define pgd_index(address) ((address) >> PGDIR_SHIFT)
 385
 386/* to find an entry in a page-table-directory */
 387#define pgd_offset(mm, address) \
 388((mm)->pgd + ((address) >> PGDIR_SHIFT))
 389
 390/* to find an entry in a kernel page-table-directory */
 391#define pgd_offset_k(address) pgd_offset(&init_mm, address)
 392
 393/* Find an entry in the second-level page table.. */
 394
 395#if PT_NLEVELS == 3
 396#define pmd_offset(dir,address) \
 397((pmd_t *) pgd_page(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
 398#else
 399#define pmd_offset(dir,addr) ((pmd_t *) dir)
 400#endif
 401
 402/* Find an entry in the third-level page table.. */ 
 403#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
 404#define pte_offset_kernel(pmd, address) \
 405        ((pte_t *) pmd_page_kernel(*(pmd)) + pte_index(address))
 406#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
 407#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
 408#define pte_unmap(pte) do { } while (0)
 409#define pte_unmap_nested(pte) do { } while (0)
 410
 411#define pte_unmap(pte)                  do { } while (0)
 412#define pte_unmap_nested(pte)           do { } while (0)
 413
 414extern void paging_init (void);
 415
 416/* Used for deferring calls to flush_dcache_page() */
 417
 418#define PG_dcache_dirty         PG_arch_1
 419
 420struct vm_area_struct; /* forward declaration (include/linux/mm.h) */
 421extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
 422
 423/* Encode and de-code a swap entry */
 424
 425#define __swp_type(x)                     ((x).val & 0x1f)
 426#define __swp_offset(x)                   ( (((x).val >> 6) &  0x7) | \
 427                                          (((x).val >> 8) & ~0x7) )
 428#define __swp_entry(type, offset)         ((swp_entry_t) { (type) | \
 429                                            ((offset &  0x7) << 6) | \
 430                                            ((offset & ~0x7) << 8) })
 431#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 432#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 433
 434static inline int ptep_test_and_clear_young(pte_t *ptep)
 435{
 436#ifdef CONFIG_SMP
 437        if (!pte_young(*ptep))
 438                return 0;
 439        return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
 440#else
 441        pte_t pte = *ptep;
 442        if (!pte_young(pte))
 443                return 0;
 444        set_pte(ptep, pte_mkold(pte));
 445        return 1;
 446#endif
 447}
 448
 449static inline int ptep_test_and_clear_dirty(pte_t *ptep)
 450{
 451#ifdef CONFIG_SMP
 452        if (!pte_dirty(*ptep))
 453                return 0;
 454        return test_and_clear_bit(xlate_pabit(_PAGE_DIRTY_BIT), &pte_val(*ptep));
 455#else
 456        pte_t pte = *ptep;
 457        if (!pte_dirty(pte))
 458                return 0;
 459        set_pte(ptep, pte_mkclean(pte));
 460        return 1;
 461#endif
 462}
 463
 464extern spinlock_t pa_dbit_lock;
 465
 466static inline pte_t ptep_get_and_clear(pte_t *ptep)
 467{
 468        pte_t old_pte;
 469        pte_t pte;
 470
 471        spin_lock(&pa_dbit_lock);
 472        pte = old_pte = *ptep;
 473        pte_val(pte) &= ~_PAGE_PRESENT;
 474        pte_val(pte) |= _PAGE_FLUSH;
 475        set_pte(ptep,pte);
 476        spin_unlock(&pa_dbit_lock);
 477
 478        return old_pte;
 479}
 480
 481static inline void ptep_set_wrprotect(pte_t *ptep)
 482{
 483#ifdef CONFIG_SMP
 484        unsigned long new, old;
 485
 486        do {
 487                old = pte_val(*ptep);
 488                new = pte_val(pte_wrprotect(__pte (old)));
 489        } while (cmpxchg((unsigned long *) ptep, old, new) != old);
 490#else
 491        pte_t old_pte = *ptep;
 492        set_pte(ptep, pte_wrprotect(old_pte));
 493#endif
 494}
 495
 496static inline void ptep_mkdirty(pte_t *ptep)
 497{
 498#ifdef CONFIG_SMP
 499        set_bit(xlate_pabit(_PAGE_DIRTY_BIT), &pte_val(*ptep));
 500#else
 501        pte_t old_pte = *ptep;
 502        set_pte(ptep, pte_mkdirty(old_pte));
 503#endif
 504}
 505
 506#define pte_same(A,B)   (pte_val(A) == pte_val(B))
 507
 508#endif /* !__ASSEMBLY__ */
 509
 510#define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
 511                remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
 512
 513/* We provide our own get_unmapped_area to provide cache coherency */
 514
 515#define HAVE_ARCH_UNMAPPED_AREA
 516
 517#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 518#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 519#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 520#define __HAVE_ARCH_PTEP_SET_WRPROTECT
 521#define __HAVE_ARCH_PTEP_MKDIRTY
 522#define __HAVE_ARCH_PTE_SAME
 523#include <asm-generic/pgtable.h>
 524
 525#endif /* _PARISC_PGTABLE_H */
 526