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20#include <linux/config.h>
21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/console.h>
25#include <linux/initrd.h>
26#include <linux/root_dev.h>
27#include <linux/delay.h>
28#include <linux/seq_file.h>
29#include <linux/smp.h>
30#include <linux/mv643xx.h>
31#ifdef CONFIG_BOOTIMG
32#include <linux/bootimg.h>
33#endif
34#include <asm/page.h>
35#include <asm/time.h>
36#include <asm/smp.h>
37#include <asm/todc.h>
38#include <asm/bootinfo.h>
39#include <asm/mv64x60.h>
40#include <platforms/katana.h>
41
42static struct mv64x60_handle bh;
43static katana_id_t katana_id;
44static u32 cpld_base;
45static u32 sram_base;
46
47
48static int __init
49katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
50{
51 static char pci_irq_table[][4] = {
52
53
54
55
56
57 { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
58 KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
59
60 { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
61 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
62
63 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
64 };
65 const long min_idsel = 4, max_idsel = 6, irqs_per_slot = 4;
66
67 return PCI_IRQ_TABLE_LOOKUP;
68}
69
70static int __init
71katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
72{
73 static char pci_irq_table[][4] = {
74
75
76
77
78 { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 },
79 { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 },
80 { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 },
81 };
82 const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
83
84 return PCI_IRQ_TABLE_LOOKUP;
85}
86
87static int __init
88katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
89{
90 switch (katana_id) {
91 case KATANA_ID_750I:
92 case KATANA_ID_752I:
93 return katana_irq_lookup_750i(idsel, pin);
94
95 case KATANA_ID_3750:
96 return katana_irq_lookup_3750(idsel, pin);
97
98 default:
99 printk(KERN_ERR "Bogus board ID\n");
100 return 0;
101 }
102}
103
104
105void __init
106katana_get_board_id(void)
107{
108 switch (in_8((volatile char *)(cpld_base + KATANA_CPLD_PRODUCT_ID))) {
109 case KATANA_PRODUCT_ID_3750:
110 katana_id = KATANA_ID_3750;
111 break;
112
113 case KATANA_PRODUCT_ID_750i:
114 katana_id = KATANA_ID_750I;
115 break;
116
117 case KATANA_PRODUCT_ID_752i:
118 katana_id = KATANA_ID_752I;
119 break;
120
121 default:
122 printk(KERN_ERR "Unsupported board\n");
123 }
124}
125
126int __init
127katana_get_proc_num(void)
128{
129 u16 val;
130 u8 save_exclude;
131 static int proc = -1;
132 static u8 first_time = 1;
133
134 if (first_time) {
135 if (katana_id != KATANA_ID_3750)
136 proc = 0;
137 else {
138 save_exclude = mv64x60_pci_exclude_bridge;
139 mv64x60_pci_exclude_bridge = 0;
140
141 early_read_config_word(bh.hose_a, 0,
142 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
143
144 mv64x60_pci_exclude_bridge = save_exclude;
145
146 switch(val) {
147 case PCI_DEVICE_ID_KATANA_3750_PROC0:
148 proc = 0;
149 break;
150
151 case PCI_DEVICE_ID_KATANA_3750_PROC1:
152 proc = 1;
153 break;
154
155 case PCI_DEVICE_ID_KATANA_3750_PROC2:
156 proc = 2;
157 break;
158
159 default:
160 printk(KERN_ERR "Bogus Device ID\n");
161 }
162 }
163
164 first_time = 0;
165 }
166
167 return proc;
168}
169
170static inline int
171katana_is_monarch(void)
172{
173 return in_8((volatile char *)(cpld_base + KATANA_CPLD_BD_CFG_3)) &
174 KATANA_CPLD_BD_CFG_3_MONARCH;
175}
176
177static void __init
178katana_enable_ipmi(void)
179{
180 u8 reset_out;
181
182
183 reset_out = in_8((volatile char *)(cpld_base + KATANA_CPLD_RESET_OUT));
184 reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
185 out_8((volatile void *)(cpld_base + KATANA_CPLD_RESET_OUT), reset_out);
186 return;
187}
188
189static unsigned long
190katana_bus_freq(void)
191{
192 u8 bd_cfg_0;
193
194 bd_cfg_0 = in_8((volatile char *)(cpld_base + KATANA_CPLD_BD_CFG_0));
195
196 switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
197 case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
198 return 200000000;
199 break;
200
201 case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
202 return 166666666;
203 break;
204
205 case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
206 return 133333333;
207 break;
208
209 case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
210 return 100000000;
211 break;
212
213 default:
214 return 133333333;
215 break;
216 }
217}
218
219
220void __init
221katana_intr_setup(void)
222{
223
224 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
225
226
227 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
228 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
229
230
231
232
233
234 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
235 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
236
237 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
238 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
239 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
240 }
241
242
243 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
244
245
246 mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
247 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
248
249
250
251
252
253 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
254 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
255
256 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
257 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
258 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
259 }
260
261
262
263
264
265 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
266 return;
267}
268
269void __init
270katana_setup_peripherals(void)
271{
272 u32 base, size_0, size_1;
273
274
275 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
276 KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
277 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
278
279
280 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base, &size_0);
281
282 if (size_0 > 0) {
283 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
284 KATANA_SOLDERED_FLASH_BASE, size_0, 0);
285 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
286 }
287
288 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base, &size_1);
289
290 if (size_1 > 0) {
291 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
292 (KATANA_SOLDERED_FLASH_BASE + size_0), size_1, 0);
293 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
294 }
295
296 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
297 KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
298 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
299
300 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
301 KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
302 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
303 cpld_base = (u32)ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
304
305 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
306 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
307 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
308 sram_base = (u32)ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
309
310
311 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
312 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
313 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
314
315
316 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
317 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
318 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
319
320 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
321 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
322 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
323
324
325 katana_get_board_id();
326
327
328 if (katana_get_proc_num() == 0)
329 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
330
331#if defined(CONFIG_NOT_COHERENT_CACHE)
332 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
333#else
334 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
335#endif
336
337
338
339
340
341
342 memset((void *)sram_base, 0, MV64360_SRAM_SIZE);
343
344
345 if (katana_get_proc_num() == 0)
346 katana_intr_setup();
347
348 return;
349}
350
351static void __init
352katana_setup_bridge(void)
353{
354 struct mv64x60_setup_info si;
355 int i;
356
357 memset(&si, 0, sizeof(si));
358
359 si.phys_reg_base = KATANA_BRIDGE_REG_BASE;
360
361 si.pci_1.enable_bus = 1;
362 si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
363 si.pci_1.pci_io.pci_base_hi = 0;
364 si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
365 si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
366 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
367 si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
368 si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
369 si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
370 si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
371 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
372 si.pci_1.pci_cmd_bits = 0;
373 si.pci_1.latency_timer = 0x80;
374
375 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
376#if defined(CONFIG_NOT_COHERENT_CACHE)
377 si.cpu_prot_options[i] = 0;
378 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
379 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
380 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
381
382 si.pci_1.acc_cntl_options[i] =
383 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
384 MV64360_PCI_ACC_CNTL_SWAP_NONE |
385 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
386 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
387#else
388 si.cpu_prot_options[i] = 0;
389 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
390 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
391 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
392
393 si.pci_1.acc_cntl_options[i] =
394 MV64360_PCI_ACC_CNTL_SNOOP_WB |
395 MV64360_PCI_ACC_CNTL_SWAP_NONE |
396 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
397 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
398#endif
399 }
400
401
402 if (mv64x60_init(&bh, &si))
403 printk(KERN_WARNING "Bridge initialization failed.\n");
404
405 pci_dram_offset = 0;
406 ppc_md.pci_swizzle = common_swizzle;
407 ppc_md.pci_map_irq = katana_map_irq;
408 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
409
410 mv64x60_set_bus(&bh, 1, 0);
411 bh.hose_b->first_busno = 0;
412 bh.hose_b->last_busno = 0xff;
413
414 return;
415}
416
417static void __init
418katana_setup_arch(void)
419{
420 if (ppc_md.progress)
421 ppc_md.progress("katana_setup_arch: enter", 0);
422
423 set_tb(0, 0);
424
425#ifdef CONFIG_BLK_DEV_INITRD
426 if (initrd_start)
427 ROOT_DEV = Root_RAM0;
428 else
429#endif
430#ifdef CONFIG_ROOT_NFS
431 ROOT_DEV = Root_NFS;
432#else
433 ROOT_DEV = Root_SDA2;
434#endif
435
436
437
438
439
440
441
442
443 if (PVR_REV(mfspr(PVR)) == 0x0200) {
444 printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
445 "to Writethrough mode\n");
446 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
447 }
448 else
449 _set_L2CR(L2CR_L2E | L2CR_L2PE);
450
451 if (ppc_md.progress)
452 ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
453
454 katana_setup_bridge();
455 katana_setup_peripherals();
456 katana_enable_ipmi();
457
458 printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
459 if (ppc_md.progress)
460 ppc_md.progress("katana_setup_arch: exit", 0);
461 return;
462}
463
464
465#if defined(CONFIG_SERIAL_MPSC)
466static void __init
467katana_fixup_mpsc_pdata(struct platform_device *pdev)
468{
469 struct mpsc_pdata *pdata;
470
471 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
472
473 pdata->max_idle = 40;
474 pdata->default_baud = KATANA_DEFAULT_BAUD;
475 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
476 pdata->brg_clk_freq = KATANA_MPSC_CLK_FREQ;
477
478 return;
479}
480#endif
481
482#if defined(CONFIG_MV643XX_ETH)
483static void __init
484katana_fixup_eth_pdata(struct platform_device *pdev)
485{
486 struct mv64xxx_eth_platform_data *eth_pd;
487 static u16 phy_addr[] = {
488 KATANA_ETH0_PHY_ADDR,
489 KATANA_ETH1_PHY_ADDR,
490 KATANA_ETH2_PHY_ADDR,
491 };
492 int rx_size = KATANA_ETH_RX_QUEUE_SIZE * MV64340_ETH_DESC_SIZE;
493 int tx_size = KATANA_ETH_TX_QUEUE_SIZE * MV64340_ETH_DESC_SIZE;
494
495 eth_pd = pdev->dev.platform_data;
496 eth_pd->force_phy_addr = 1;
497 eth_pd->phy_addr = phy_addr[pdev->id];
498 eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
499 eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
500 eth_pd->tx_sram_addr = mv643xx_sram_alloc(tx_size);
501
502 if (eth_pd->tx_sram_addr)
503 eth_pd->tx_sram_size = tx_size;
504 else
505 printk(KERN_ERR "mv643xx_sram_alloc failed\n");
506
507 eth_pd->rx_sram_addr = mv643xx_sram_alloc(rx_size);
508 if (eth_pd->rx_sram_addr)
509 eth_pd->rx_sram_size = rx_size;
510 else
511 printk(KERN_ERR "mv643xx_sram_alloc failed\n");
512}
513#endif
514
515static int __init
516katana_platform_notify(struct device *dev)
517{
518 static struct {
519 char *bus_id;
520 void ((*rtn)(struct platform_device *pdev));
521 } dev_map[] = {
522#if defined(CONFIG_SERIAL_MPSC)
523 { MPSC_CTLR_NAME "0", katana_fixup_mpsc_pdata },
524 { MPSC_CTLR_NAME "1", katana_fixup_mpsc_pdata },
525#endif
526#if defined(CONFIG_MV643XX_ETH)
527 { MV64XXX_ETH_NAME "0", katana_fixup_eth_pdata },
528 { MV64XXX_ETH_NAME "1", katana_fixup_eth_pdata },
529 { MV64XXX_ETH_NAME "2", katana_fixup_eth_pdata },
530#endif
531 };
532 struct platform_device *pdev;
533 int i;
534
535 if (dev && dev->bus_id)
536 for (i=0; i<ARRAY_SIZE(dev_map); i++)
537 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
538 BUS_ID_SIZE)) {
539
540 pdev = container_of(dev,
541 struct platform_device, dev);
542 dev_map[i].rtn(pdev);
543 }
544
545 return 0;
546}
547
548static void
549katana_restart(char *cmd)
550{
551 volatile ulong i = 10000000;
552
553
554 out_8((volatile char *)(cpld_base + KATANA_CPLD_RST_CMD),
555 KATANA_CPLD_RST_CMD_HR);
556
557 while (i-- > 0) ;
558 panic("restart failed\n");
559}
560
561static void
562katana_halt(void)
563{
564 while (1) ;
565
566}
567
568static void
569katana_power_off(void)
570{
571 katana_halt();
572
573}
574
575static int
576katana_show_cpuinfo(struct seq_file *m)
577{
578 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
579
580 seq_printf(m, "board\t\t: ");
581
582 switch (katana_id) {
583 case KATANA_ID_3750:
584 seq_printf(m, "Katana 3750\n");
585 break;
586
587 case KATANA_ID_750I:
588 seq_printf(m, "Katana 750i\n");
589 break;
590
591 case KATANA_ID_752I:
592 seq_printf(m, "Katana 752i\n");
593 break;
594
595 default:
596 seq_printf(m, "Unknown\n");
597 break;
598 }
599
600 seq_printf(m, "product ID\t: 0x%x\n",
601 in_8((volatile char *)(cpld_base + KATANA_CPLD_PRODUCT_ID)));
602 seq_printf(m, "hardware rev\t: 0x%x\n",
603 in_8((volatile char *)(cpld_base+KATANA_CPLD_HARDWARE_VER)));
604 seq_printf(m, "PLD rev\t\t: 0x%x\n",
605 in_8((volatile char *)(cpld_base + KATANA_CPLD_PLD_VER)));
606 seq_printf(m, "PLB freq\t: %ldMhz\n", katana_bus_freq() / 1000000);
607 seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-");
608
609 return 0;
610}
611
612static void __init
613katana_calibrate_decr(void)
614{
615 ulong freq;
616
617 freq = katana_bus_freq() / 4;
618
619 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
620 freq / 1000000, freq % 1000000);
621
622 tb_ticks_per_jiffy = freq / HZ;
623 tb_to_us = mulhwu_scale_factor(freq, 1000000);
624
625 return;
626}
627
628unsigned long __init
629katana_find_end_of_memory(void)
630{
631 return mv64x60_get_mem_size(KATANA_BRIDGE_REG_BASE,
632 MV64x60_TYPE_MV64360);
633}
634
635static inline void
636katana_set_bat(void)
637{
638 mb();
639 mtspr(DBAT2U, 0xf0001ffe);
640 mtspr(DBAT2L, 0xf000002a);
641 mb();
642
643 return;
644}
645
646#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
647static void __init
648katana_map_io(void)
649{
650 io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
651}
652#endif
653
654void __init
655platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
656 unsigned long r6, unsigned long r7)
657{
658 parse_bootinfo(find_bootinfo());
659
660 isa_mem_base = 0;
661
662 ppc_md.setup_arch = katana_setup_arch;
663 ppc_md.show_cpuinfo = katana_show_cpuinfo;
664 ppc_md.init_IRQ = mv64360_init_irq;
665 ppc_md.get_irq = mv64360_get_irq;
666 ppc_md.restart = katana_restart;
667 ppc_md.power_off = katana_power_off;
668 ppc_md.halt = katana_halt;
669 ppc_md.find_end_of_memory = katana_find_end_of_memory;
670 ppc_md.calibrate_decr = katana_calibrate_decr;
671
672#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
673 ppc_md.setup_io_mappings = katana_map_io;
674 ppc_md.progress = mv64x60_mpsc_progress;
675 mv64x60_progress_init(KATANA_BRIDGE_REG_BASE);
676#endif
677
678#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
679 platform_notify = katana_platform_notify;
680#endif
681
682 katana_set_bat();
683 return;
684}
685
