1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/config.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <linux/ide.h>
17#include <linux/irq.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
20#include <linux/console.h>
21#include <linux/initrd.h>
22#include <linux/root_dev.h>
23#include <linux/mv643xx.h>
24#include <asm/bootinfo.h>
25#include <asm/machdep.h>
26#include <asm/todc.h>
27#include <asm/time.h>
28#include <asm/mv64x60.h>
29#include <platforms/cpci690.h>
30
31#define BOARD_VENDOR "Force"
32#define BOARD_MACHINE "CPCI690"
33
34
35#define SET_PCI_IDE_NATIVE
36
37static struct mv64x60_handle bh;
38static u32 cpci690_br_base;
39
40static const unsigned int cpu_7xx[16] = {
41 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
42};
43
44TODC_ALLOC();
45
46static int __init
47cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
48{
49 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
50
51 if (hose->index == 0) {
52 static char pci_irq_table[][4] =
53
54
55
56
57 {
58 { 90, 91, 88, 89},
59 };
60
61 const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
62 return PCI_IRQ_TABLE_LOOKUP;
63 }
64 else {
65 static char pci_irq_table[][4] =
66
67
68
69
70 {
71 { 93, 94, 95, 92},
72 { 0, 0, 0, 0},
73 { 94, 95, 92, 93},
74 };
75
76 const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
77 return PCI_IRQ_TABLE_LOOKUP;
78 }
79}
80
81static int
82cpci690_get_bus_speed(void)
83{
84 return 133333333;
85}
86
87static int
88cpci690_get_cpu_speed(void)
89{
90 unsigned long hid1;
91
92 hid1 = mfspr(HID1) >> 28;
93 return cpci690_get_bus_speed() * cpu_7xx[hid1]/2;
94}
95
96#define KB (1024UL)
97#define MB (1024UL * KB)
98#define GB (1024UL * MB)
99
100unsigned long __init
101cpci690_find_end_of_memory(void)
102{
103 u32 mem_ctlr_size;
104 static u32 board_size;
105 static u8 first_time = 1;
106
107 if (first_time) {
108
109 switch (in_8((u8 *) (cpci690_br_base +
110 CPCI690_BR_MEM_CTLR)) & 0x07) {
111 case 0x01:
112 board_size = 256*MB;
113 break;
114 case 0x02:
115 board_size = 512*MB;
116 break;
117 case 0x03:
118 board_size = 768*MB;
119 break;
120 case 0x04:
121 board_size = 1*GB;
122 break;
123 case 0x05:
124 board_size = 1*GB + 512*MB;
125 break;
126 case 0x06:
127 board_size = 2*GB;
128 break;
129 default:
130 board_size = 0xffffffff;
131 }
132
133 mem_ctlr_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
134 MV64x60_TYPE_GT64260A);
135
136
137 if (board_size != mem_ctlr_size) {
138 printk(KERN_WARNING "Board register & memory controller"
139 "mem size disagree (board reg: 0x%lx, "
140 "mem ctlr: 0x%lx)\n",
141 (ulong)board_size, (ulong)mem_ctlr_size);
142 board_size = min(board_size, mem_ctlr_size);
143 }
144
145 first_time = 0;
146 }
147
148 return board_size;
149}
150
151static void __init
152cpci690_setup_bridge(void)
153{
154 struct mv64x60_setup_info si;
155 int i;
156
157 memset(&si, 0, sizeof(si));
158
159 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
160
161 si.pci_0.enable_bus = 1;
162 si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR;
163 si.pci_0.pci_io.pci_base_hi = 0;
164 si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR;
165 si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE;
166 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
167 si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR;
168 si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR;
169 si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR;
170 si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE;
171 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
172 si.pci_0.pci_cmd_bits = 0;
173 si.pci_0.latency_timer = 0x80;
174
175 si.pci_1.enable_bus = 1;
176 si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR;
177 si.pci_1.pci_io.pci_base_hi = 0;
178 si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR;
179 si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE;
180 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
181 si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR;
182 si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR;
183 si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR;
184 si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE;
185 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
186 si.pci_1.pci_cmd_bits = 0;
187 si.pci_1.latency_timer = 0x80;
188
189 for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
190 si.cpu_prot_options[i] = 0;
191 si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
192 si.pci_0.acc_cntl_options[i] =
193 GT64260_PCI_ACC_CNTL_DREADEN |
194 GT64260_PCI_ACC_CNTL_RDPREFETCH |
195 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
196 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
197 GT64260_PCI_ACC_CNTL_SWAP_NONE |
198 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
199 si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
200 si.pci_1.acc_cntl_options[i] =
201 GT64260_PCI_ACC_CNTL_DREADEN |
202 GT64260_PCI_ACC_CNTL_RDPREFETCH |
203 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
204 GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
205 GT64260_PCI_ACC_CNTL_SWAP_NONE |
206 GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
207 si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
208 }
209
210
211 if (mv64x60_init(&bh, &si))
212 printk(KERN_ERR "Bridge initialization failed.\n");
213
214 pci_dram_offset = 0;
215 ppc_md.pci_swizzle = common_swizzle;
216 ppc_md.pci_map_irq = cpci690_map_irq;
217 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
218
219 mv64x60_set_bus(&bh, 0, 0);
220 bh.hose_a->first_busno = 0;
221 bh.hose_a->last_busno = 0xff;
222 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
223
224 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
225 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
226 bh.hose_b->last_busno = 0xff;
227 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
228 bh.hose_b->first_busno);
229
230 return;
231}
232
233static void __init
234cpci690_setup_peripherals(void)
235{
236
237 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
238 CPCI690_BR_SIZE, 0);
239 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
240 cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
241
242 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
243 CPCI690_TODC_SIZE, 0);
244 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
245 TODC_INIT(TODC_TYPE_MK48T35, 0, 0,
246 ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);
247
248 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,
249 CPCI690_IPMI_SIZE, 0);
250 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
251
252 mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
253 mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
254
255 mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9));
256
257
258
259
260
261
262 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
263 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
264 mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
265 ((1<<0) | (1<<8) | (1<<16) | (1<<24)));
266
267
268
269
270
271 mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
272
273#define GPP_EXTERNAL_INTERRUPTS \
274 ((1<<24) | (1<<25) | (1<<26) | (1<<27) | \
275 (1<<28) | (1<<29) | (1<<30) | (1<<31))
276
277 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
278
279 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
280
281
282 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
283 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
284
285
286 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
287 mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
288
289 return;
290}
291
292static void __init
293cpci690_setup_arch(void)
294{
295 if (ppc_md.progress)
296 ppc_md.progress("cpci690_setup_arch: enter", 0);
297#ifdef CONFIG_BLK_DEV_INITRD
298 if (initrd_start)
299 ROOT_DEV = Root_RAM0;
300 else
301#endif
302#ifdef CONFIG_ROOT_NFS
303 ROOT_DEV = Root_NFS;
304#else
305 ROOT_DEV = Root_SDA2;
306#endif
307
308 if (ppc_md.progress)
309 ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0);
310
311
312 _set_L2CR(_get_L2CR() | L2CR_L2E);
313 _set_L3CR(_get_L3CR() | L3CR_L3E);
314
315 if (ppc_md.progress)
316 ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0);
317
318 cpci690_setup_bridge();
319 cpci690_setup_peripherals();
320
321 if (ppc_md.progress)
322 ppc_md.progress("cpci690_setup_arch: bridge init complete", 0);
323
324 printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. "
325 "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
326
327 if (ppc_md.progress)
328 ppc_md.progress("cpci690_setup_arch: exit", 0);
329
330 return;
331}
332
333
334#if defined(CONFIG_SERIAL_MPSC)
335static void __init
336cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
337{
338 struct mpsc_pdata *pdata;
339
340 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
341
342 pdata->max_idle = 40;
343 pdata->default_baud = 9600;
344 pdata->brg_clk_src = 8;
345 pdata->brg_clk_freq = 133000000;
346
347 return;
348}
349
350static int __init
351cpci690_platform_notify(struct device *dev)
352{
353 static struct {
354 char *bus_id;
355 void ((*rtn)(struct platform_device *pdev));
356 } dev_map[] = {
357 { MPSC_CTLR_NAME "0", cpci690_fixup_mpsc_pdata },
358 { MPSC_CTLR_NAME "1", cpci690_fixup_mpsc_pdata },
359 };
360 struct platform_device *pdev;
361 int i;
362
363 if (dev && dev->bus_id)
364 for (i=0; i<ARRAY_SIZE(dev_map); i++)
365 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
366 BUS_ID_SIZE)) {
367
368 pdev = container_of(dev,
369 struct platform_device, dev);
370 dev_map[i].rtn(pdev);
371 }
372
373 return 0;
374}
375#endif
376
377static void
378cpci690_reset_board(void)
379{
380 u32 i = 10000;
381
382 local_irq_disable();
383 out_8((u8 *)(cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
384
385 while (i != 0) i++;
386 panic("restart failed\n");
387}
388
389static void
390cpci690_restart(char *cmd)
391{
392 cpci690_reset_board();
393}
394
395static void
396cpci690_halt(void)
397{
398 while (1);
399
400}
401
402static void
403cpci690_power_off(void)
404{
405 cpci690_halt();
406
407}
408
409static int
410cpci690_show_cpuinfo(struct seq_file *m)
411{
412 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
413 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
414 seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000);
415 seq_printf(m, "bus MHz\t\t: %d\n", cpci690_get_bus_speed()/1000/1000);
416
417 return 0;
418}
419
420static void __init
421cpci690_calibrate_decr(void)
422{
423 ulong freq;
424
425 freq = cpci690_get_bus_speed()/4;
426
427 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
428 freq/1000000, freq%1000000);
429
430 tb_ticks_per_jiffy = freq / HZ;
431 tb_to_us = mulhwu_scale_factor(freq, 1000000);
432
433 return;
434}
435
436static __inline__ void
437cpci690_set_bat(u32 addr, u32 size)
438{
439 addr &= 0xfffe0000;
440 size &= 0x1ffe0000;
441 size = ((size >> 17) - 1) << 2;
442
443 mb();
444 mtspr(DBAT1U, addr | size | 0x2);
445 mtspr(DBAT1L, addr | 0x2a);
446 mb();
447
448 return;
449}
450
451#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
452static void __init
453cpci690_map_io(void)
454{
455 io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
456 128 * KB, _PAGE_IO);
457}
458#endif
459
460void __init
461platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
462 unsigned long r6, unsigned long r7)
463{
464#ifdef CONFIG_BLK_DEV_INITRD
465 initrd_start=initrd_end=0;
466 initrd_below_start_ok=0;
467#endif
468
469 parse_bootinfo(find_bootinfo());
470
471 loops_per_jiffy = cpci690_get_cpu_speed() / HZ;
472
473 isa_mem_base = 0;
474
475 ppc_md.setup_arch = cpci690_setup_arch;
476 ppc_md.show_cpuinfo = cpci690_show_cpuinfo;
477 ppc_md.init_IRQ = gt64260_init_irq;
478 ppc_md.get_irq = gt64260_get_irq;
479 ppc_md.restart = cpci690_restart;
480 ppc_md.power_off = cpci690_power_off;
481 ppc_md.halt = cpci690_halt;
482 ppc_md.find_end_of_memory = cpci690_find_end_of_memory;
483 ppc_md.time_init = todc_time_init;
484 ppc_md.set_rtc_time = todc_set_rtc_time;
485 ppc_md.get_rtc_time = todc_get_rtc_time;
486 ppc_md.nvram_read_val = todc_direct_read_val;
487 ppc_md.nvram_write_val = todc_direct_write_val;
488 ppc_md.calibrate_decr = cpci690_calibrate_decr;
489
490
491
492
493
494 cpci690_set_bat(CPCI690_BR_BASE, 32 * MB);
495 cpci690_br_base = CPCI690_BR_BASE;
496
497#ifdef CONFIG_SERIAL_TEXT_DEBUG
498 ppc_md.setup_io_mappings = cpci690_map_io;
499 ppc_md.progress = mv64x60_mpsc_progress;
500 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
501#endif
502#ifdef CONFIG_KGDB
503 ppc_md.setup_io_mappings = cpci690_map_io;
504 ppc_md.early_serial_map = cpci690_early_serial_map;
505#endif
506
507#if defined(CONFIG_SERIAL_MPSC)
508 platform_notify = cpci690_platform_notify;
509#endif
510
511 return;
512}
513
