LXR coreboot-v3/southbridge/nvidia/mcp55/stage1

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2004 Tyan Computer
   5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6 * Copyright (C) 2006,2007 AMD
   7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 */
  23
  24#include <mainboard.h>
  25#define EHCI_BAR_INDEX  0x10
  26#define EHCI_BAR        0xFEF00000
  27#define EHCI_DEBUG_OFFSET       0x98
  28
  29#include "pci.h"
  30static void set_debug_port(unsigned port)
  31{
  32        u32 dword;
  33        u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1);
  34        dword = pci_conf1_read_config32(bdf, 0x74);
  35        dword &= ~(0xf<<12);
  36        dword |= (port<<12);
  37        pci_conf1_write_config32(bdf, 0x74, dword);
  38
  39}
  40
  41static void mcp55_enable_usbdebug_direct(unsigned port)
  42{
  43        u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1);
  44        set_debug_port(port);
  45        pci_conf1_write_config32(bdf, EHCI_BAR_INDEX, EHCI_BAR);
  46        pci_conf1_write_config8(bdf, 0x04, 0x2); // mem space enable
  47}
  48
  49