LXR coreboot-v3/southbridge/nvidia/mcp55/sata.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2004 Tyan Computer
   5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6 * Copyright (C) 2006,2007 AMD
   7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 */
  23
  24#include <types.h>
  25#include <lib.h>
  26#include <console.h>
  27#include <device/pci.h>
  28#include <msr.h>
  29#include <legacy.h>
  30#include <device/pci_ids.h>
  31#include <statictree.h>
  32#include <config.h>
  33#include "mcp55.h"
  34
  35
  36static void sata_init(struct device *dev)
  37{
  38        u32 dword;
  39
  40        struct southbridge_nvidia_mcp55_sata_config *conf =
  41            (struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration;
  42
  43        dword = pci_read_config32(dev, 0x50);
  44        /* Ensure prefetch is disabled */
  45        dword &= ~((1 << 15) | (1 << 13));
  46        if(conf) {
  47                if (conf->sata1_enable) {
  48                        dword |= (1<<0);
  49                        printk(BIOS_DEBUG, "Enable secondary SATA interface\t");
  50                }
  51                if (conf->sata0_enable) {
  52                        dword |= (1<<1);
  53                        printk(BIOS_DEBUG, "Enable primary SATA interface\n");
  54                }
  55        } else {
  56                dword |= (1<<1) | (1<<0);
  57                printk(BIOS_DEBUG, "Enable primary and secondary SATA interfaces\n");
  58        }
  59
  60
  61#if 1
  62        dword &= ~(0x1f<<24);
  63        dword |= (0x15<<24);
  64#endif
  65        pci_write_config32(dev, 0x50, dword);
  66
  67        dword = pci_read_config32(dev, 0xf8);
  68        dword |= 2;
  69        pci_write_config32(dev, 0xf8, dword);
  70}
  71
  72struct device_operations mcp55_sata = {
  73        .id = {.type = DEVICE_ID_PCI,
  74                {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
  75                              .device = PCI_DEVICE_ID_NVIDIA_MCP55_SATA1}}},
  76        .constructor             = default_device_constructor,
  77        .phase3_scan             = 0,
  78        .phase4_read_resources   = pci_dev_read_resources,
  79        .phase4_set_resources    = pci_set_resources,
  80        .phase5_enable_resources = pci_dev_enable_resources,
  81        .phase6_init             = sata_init,
  82        .ops_pci                 = &mcp55_pci_dev_ops_pci,
  83};
  84