LXR coreboot-v3/southbridge/amd/amd8151/amd8151

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2003 Yinghai Lu, Tyan
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; version 2 of the License.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 */
  19#include <types.h>
  20#include <lib.h>
  21#include <console.h>
  22#include <device/pci.h>
  23#include <msr.h>
  24#include <legacy.h>
  25#include <device/pci_ids.h>
  26#include <statictree.h>
  27#include <config.h>
  28
  29static void agp3bridge_init(struct device * dev)
  30{
  31        u8 byte;
  32
  33        /* Enable BM, MEM and IO */
  34        /* this config32 is arguably wrong but I won't change until we can test. */
  35        byte = pci_read_config32(dev, PCI_COMMAND);
  36        byte |= 0x07;
  37        pci_write_config8(dev, PCI_COMMAND, byte);
  38
  39        return;
  40}
  41
  42struct device_operations amd8151_agp3bridge = {
  43        .id = {.type = DEVICE_ID_PCI,
  44                {.pci = {.vendor = PCI_VENDOR_ID_AMD,
  45                         .device = PCI_DEVICE_ID_AMD_8151_AGP}}},
  46        .constructor             = default_device_constructor,
  47        .phase3_scan             = pci_scan_bridge,
  48        .phase4_read_resources   = pci_bus_read_resources,
  49        .phase4_set_resources    = pci_set_resources,
  50        .phase5_enable_resources = pci_bus_enable_resources,
  51        .phase6_init             = agp3bridge_init,
  52};
  53
  54static void agp3dev_enable(struct device * dev)
  55{
  56        u32 value;
  57        
  58        /* AGP enable */
  59        value = pci_read_config32(dev, 0xa8);
  60        value |= (3<<8)|2; //AGP 8x
  61        pci_write_config32(dev, 0xa8, value);
  62
  63        /* enable BM and MEM */
  64        value = pci_read_config32(dev, PCI_COMMAND);
  65        value |= 6;
  66        pci_write_config32(dev, PCI_COMMAND, value);
  67#if 0
  68        /* FIXME: should we add agp aperture base and size here ?
  69         * or it is done by AGP drivers */
  70#endif
  71}
  72
  73static struct pci_operations pci_ops_pci_dev = {
  74        .set_subsystem    = pci_dev_set_subsystem,
  75};
  76
  77struct device_operations amd8151_agp3dev = {
  78        .id = {.type = DEVICE_ID_PCI,
  79                {.pci = {.vendor = PCI_VENDOR_ID_AMD,
  80                         .device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}},
  81        .constructor             = default_device_constructor,
  82        .phase3_enable           = agp3dev_enable,
  83        .phase4_read_resources   = pci_dev_read_resources,
  84        .phase4_set_resources    = pci_set_resources,
  85        .phase5_enable_resources = pci_dev_enable_resources,
  86        .phase6_init             = NULL,
  87        .ops_pci                 = &pci_dev_ops_pci,
  88};
  89