LXR coreboot-v3/southbridge/amd/amd8111/stage1_enable

   1/*
   2 *
   3 * This file is part of the coreboot project.
   4 * Copyright (C) 2003 Linux NetworX
   5 * Copyright (C) 2004 Ollie Lo
   6 * Copyright (C) 2006 YingHai Lu
   7 * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; version 2 of the License.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  21 */
  22#include <types.h>
  23#include <lib.h>
  24#include <console.h>
  25#include <device/pci.h>
  26#include <msr.h>
  27#include <legacy.h>
  28#include <device/pci_ids.h>
  29#include <statictree.h>
  30#include <config.h>
  31
  32/**
  33 * Enable the 5 MB address space for the ROM
  34 */
  35void amd8111_enable_rom(void)
  36{
  37        u8 byte;
  38        u32 dev;
  39
  40        /* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
  41        /* Locate the amd8111 */
  42        pci_conf1_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA, 
  43                                &dev);
  44        /* Set the 5MB enable bits */
  45        byte = pci_conf1_read_config8(dev, 0x43);
  46        byte |= 0xC0;
  47        pci_conf1_write_config8(dev, 0x43, byte);
  48}
  49