1/* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21/{ 22 mainboard_vendor = "PC Engines"; 23 mainboard_name = "ALIX.2C3"; 24 cpus { }; 25 apic@0 { 26 /config/("northbridge/amd/geodelx/apic"); 27 }; 28 domain@0 { 29 /config/("northbridge/amd/geodelx/domain"); 30 pci@1,0 { 31 /config/("northbridge/amd/geodelx/pci"); 32 }; 33 pci@f,0 { 34 /config/("southbridge/amd/cs5536/dts"); 35 /* Interrupt enables for LPC bus. 36 * Each bit is an IRQ 0-15. */ 37 lpc_serirq_enable = "0x00001002"; 38 /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ 39 lpc_serirq_polarity = "0x0000EFFD"; 40 /* 0:continuous 1:quiet */ 41 lpc_serirq_mode = "1"; 42 /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 43 * See virtual PIC spec. */ 44 enable_gpio_int_route = "0x0D0C0700"; 45 /* COM1 settings */ 46 com1_enable = "1"; 47 com1_address = "0x3f8"; 48 com1_irq = "4"; 49 /* this board does not really have vga; disable it (pci device 00:01.1) */ 50 unwanted_vpci = < 80000900 0 >; 51 }; 52 pci@f,2 { 53 /config/("southbridge/amd/cs5536/ide"); 54 }; 55 }; 56}; 57