LXR coreboot-v3/mainboard/artecgroup/dbe62/initram.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5 * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 */
  21
  22#define _MAINOBJECT
  23
  24#include <types.h>
  25#include <lib.h>
  26#include <console.h>
  27#include <device/device.h>
  28#include <device/pci.h>
  29#include <string.h>
  30#include <msr.h>
  31#include <io.h>
  32#include <amd_geodelx.h>
  33#include <northbridge/amd/geodelx/raminit.h>
  34#include <spd.h>
  35
  36#define MANUALCONF 0            /* Do manual strapped PLL config */
  37#define PLLMSRHI 0x000003d9     /* manual settings for the PLL */
  38#define PLLMSRLO 0x07de0080     /* from factory bios */
  39#define DIMM0 ((u8) 0xA0)
  40#define DIMM1 ((u8) 0xA2)
  41
  42/* The part is a Micron MT46V16M16 P 5B 
  43 * 4 M x 16 x 5 Banks, 200 Mhz, Plastic package, TSOP, DDR400B, 5 ns CL3
  44 * Commercial rating. 
  45 * @ 200 ns, data-out window, 1.6; access, +- 70 ns; dqs-dq skew: .4ns
  46 * http://www.micron.com/products/partdetail?part=MT46V16M16P-5B
  47 */
  48
  49struct spd_entry {
  50        u8 address;
  51        u8 data;
  52};
  53
  54/* Save space by using a short list of SPD values used by Geode LX Memory init */
  55static const struct spd_entry spd_table[] = {
  56        {SPD_MEMORY_TYPE, 7},
  57        {SPD_NUM_ROWS, 13},
  58        {SPD_tRFC, 0x4b},
  59        {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
  60        {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x40},
  61        {SPD_tRAS, 0x2d},
  62        {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x7}, /*0x <= 7},*/
  63        {SPD_MIN_RAS_TO_CAS_DELAY, 0x58},
  64        {SPD_tRRD, 0x3c},
  65        {SPD_tRP, 0x58},
  66        {SPD_PRIMARY_SDRAM_WIDTH, 8},
  67        {SPD_NUM_BANKS_PER_SDRAM, 0x4},
  68        {SPD_NUM_COLUMNS, 0xa}, /* 8kB */
  69        {SPD_NUM_DIMM_BANKS, 0x1},
  70        {SPD_REFRESH, 0x82},
  71        {SPD_SDRAM_CYCLE_TIME_2ND, 0x0},
  72        {SPD_SDRAM_CYCLE_TIME_3RD, 0x0},
  73};
  74
  75/**
  76 * Given an SMBUS device, and an address in that device, return the value of SPD
  77 * for that device. In this mainboard, the only one that can return is DIMM0. 
  78 * @param device The device number
  79 * @param address The address in SPD rom to return the value of
  80 * @returns The value
  81 */ 
  82u8 spd_read_byte(u16 device, u8 address)
  83{
  84        int i;
  85        /* returns 0xFF on any failures */
  86        u8 ret = 0xff;
  87
  88        printk(BIOS_DEBUG, "spd_read_byte dev %04x", device);
  89        if (device == DIMM0) {
  90                for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
  91                        if (spd_table[i].address == address) {
  92                                ret = spd_table[i].data;
  93                                break;
  94                        }
  95                }
  96
  97                if (i == ARRAY_SIZE(spd_table))
  98                        printk(BIOS_DEBUG, " addr %02x does not exist in SPD table",
  99                                address);
 100        }
 101
 102        printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret);
 103        return ret;
 104}
 105
 106/**
 107  * Placeholder in case we ever need it. Since this file is a
 108  * template for other motherboards, we want this here and we want the
 109  * call in the right place.
 110  */
 111
 112static void mb_gpio_init(void)
 113{
 114        /* Early mainboard specific GPIO setup */
 115}
 116
 117/** 
 118  * main for initram for the Artec Group ThinCan DBE62. It might seem that
 119  * you could somehow do these functions in, e.g., the cpu code, but the
 120  * order of operations and what those operations are is VERY strongly
 121  * mainboard dependent. It's best to leave it in the mainboard code.
 122  */
 123int main(void)
 124{
 125        printk(BIOS_DEBUG, "Hi there from stage1\n");
 126        post_code(POST_START_OF_MAIN);
 127
 128        system_preinit();
 129        printk(BIOS_DEBUG, "done preinit\n");
 130
 131        mb_gpio_init();
 132        printk(BIOS_DEBUG, "done gpio init\n");
 133
 134        pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
 135        printk(BIOS_DEBUG, "done pll reset\n");
 136
 137        cpu_reg_init(0, DIMM0, DIMM1, DRAM_UNTERMINATED);
 138        printk(BIOS_DEBUG, "done cpu reg init\n");
 139
 140        sdram_set_registers();
 141        printk(BIOS_DEBUG, "done sdram set registers\n");
 142
 143        sdram_set_spd_registers(DIMM0, DIMM1);
 144        printk(BIOS_DEBUG, "done sdram set spd registers\n");
 145
 146        sdram_enable(DIMM0, DIMM1);
 147        printk(BIOS_DEBUG, "done sdram enable\n");
 148
 149        printk(BIOS_DEBUG, "stage1 returns\n");
 150        return 0;
 151}
 152