LXR coreboot-v3/mainboard/amd/db800/dts

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21/{
  22        mainboard_vendor = "AMD";
  23        mainboard_name = "DB800";
  24        mainboard_pci_subsystem_vendor = "0x1022";
  25        mainboard_pci_subsystem_device = "0x2323";
  26        cpus { };
  27        apic@0 {
  28                /config/("northbridge/amd/geodelx/apic");
  29        };
  30        domain@0 {
  31                /config/("northbridge/amd/geodelx/domain");
  32                pci@1,0 {
  33                        /config/("northbridge/amd/geodelx/pci");
  34                        /* Video RAM has to be in 2MB chunks. */
  35                        geode_video_mb = "8";
  36                };
  37                pci@1,1 { /* Graphics */
  38                };
  39                pci@1,2 { /* AES */
  40                };
  41                pci@f,0 {
  42                        /config/("southbridge/amd/cs5536/dts");
  43                        /* Interrupt enables for LPC bus.
  44                         *  Each bit is an IRQ 0-15. */
  45                        lpc_serirq_enable = "0x000010da";
  46                        /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
  47                        lpc_serirq_polarity = "0x0000EF25";
  48                        /* 0:continuous 1:quiet */
  49                        lpc_serirq_mode = "1";
  50                        /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 
  51                         * See virtual PIC spec. */
  52                        enable_gpio_int_route = "0x0D0C0700";
  53                        enable_USBP4_device = "1";
  54                };
  55                pci@f,2 {
  56                        /config/("southbridge/amd/cs5536/ide");
  57                };
  58                ioport@2e {
  59                        /config/("superio/winbond/w83627hf/dts");
  60                        com1enable = "1";
  61                };
  62        };
  63};
  64