LXR coreboot-v3/southbridge/via/vt8237/vt8237.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License v2 as published by
   8 * the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 */
  19
  20#include <types.h>
  21#include <console.h>
  22#include <device/pci.h>
  23#include <device/pci_ids.h>
  24#include <statictree.h>
  25#include <config.h>
  26#include "vt8237.h"
  27
  28/*
  29 * Datasheet: http://www.via.com.tw/en/downloads/datasheets/chipsets/
  30 *              VT8237R_SouthBridge_Revision2.06_Lead-Free.zip
  31 */
  32
  33void vt8237_enable(struct device *dev)
  34{
  35        struct device *lpc_dev;
  36        u16 sb_fn_ctrl;
  37
  38        const u8 func = dev->path.pci.devfn & 0x7;
  39        const u8 device = dev->path.pci.devfn >> 3;
  40        const int d16_index[6] = {12, 13, 10, 8, 9, 7};
  41
  42
  43        printk(BIOS_DEBUG, "Enabling/Disabling device 0x%x function 0x%x.\n",
  44                                                        device, func);
  45
  46        if(dev->id.pci.vendor != PCI_VENDOR_ID_VIA)
  47                return;
  48
  49        lpc_dev = dev_find_slot(0, PCI_BDF(0, 17, 0));
  50        sb_fn_ctrl = pci_read_config8(lpc_dev, 0x50) << 8;
  51        sb_fn_ctrl |= pci_read_config8(lpc_dev, 0x51);
  52
  53        if (device == 16)
  54        {
  55                /* If any port is enabled, the first port needs to be enabled */
  56                if (dev->enabled)
  57                {
  58                        sb_fn_ctrl &= ~(1 << d16_index[0]);
  59                        sb_fn_ctrl &= ~(1 << d16_index[func]);
  60                }
  61                else
  62                {
  63                        sb_fn_ctrl |= (1 << d16_index[func]);
  64                }
  65        }
  66        else if (device == 17)
  67        {
  68                if (func == 5)
  69                {
  70                        sb_fn_ctrl &= ~(dev->enabled << 14);
  71                        sb_fn_ctrl |= (!dev->enabled << 14); 
  72                }
  73                else if (func == 6)
  74                {
  75                        sb_fn_ctrl &= ~(dev->enabled << 15);
  76                        sb_fn_ctrl |= (!dev->enabled << 15);
  77                }
  78        }
  79                        
  80        pci_write_config8(dev, 0x50, (sb_fn_ctrl >> 8) & 0xff);
  81        pci_write_config8(dev, 0x51, sb_fn_ctrl & 0xff);
  82
  83        /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
  84}
  85