coreboot-v3/southbridge/nvidia/mcp55/stage1_enable_rom.c
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   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2004 Tyan Computer
   5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6 * Copyright (C) 2006,2007 AMD
   7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 */
  23#include <mainboard.h>
  24#include <types.h>
  25#include <lib.h>
  26#include <device/device.h>
  27#include <device/pci.h>
  28void mcp55_enable_rom(void)
  29{
  30        u8 byte;
  31        u16 word;
  32        u32 addr;
  33
  34        /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
  35        addr = PCI_BDF(0, (MCP55_DEVN_BASE+1), 0);
  36
  37        /* Set the 4MB enable bit bit */
  38        byte = pci_conf1_read_config8(addr, 0x88);
  39        byte |= 0xff; //256K
  40        pci_conf1_write_config8(addr, 0x88, byte);
  41        byte = pci_conf1_read_config8(addr, 0x8c);
  42        byte |= 0xff; //1M
  43        pci_conf1_write_config8(addr, 0x8c, byte);
  44        word = pci_conf1_read_config16(addr, 0x90);
  45        word |= 0x7fff; //15M
  46        pci_conf1_write_config16(addr, 0x90, word);
  47}
  48
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