LXR coreboot-v3/mainboard/pcengines/alix1c/initram.c

   1/*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 */
  20
  21#define _MAINOBJECT
  22
  23#include <types.h>
  24#include <lib.h>
  25#include <console.h>
  26#include <device/device.h>
  27#include <device/pci.h>
  28#include <string.h>
  29#include <msr.h>
  30#include <io.h>
  31#include <amd_geodelx.h>
  32#include <northbridge/amd/geodelx/raminit.h>
  33#include <spd.h>
  34
  35#define MANUALCONF 0            /* Do automatic strapped PLL config */
  36#define PLLMSRHI 0x00001490     /* manual settings for the PLL */
  37#define PLLMSRLO 0x02000030
  38#define DIMM0 ((u8) 0xA0)
  39#define DIMM1 ((u8) 0xA2)
  40
  41/* The part is a Hynix hy5du121622ctp-d43.
  42 *
  43 * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
  44 * Hynix
  45 * DDR SDRAM (5D)
  46 * VDD 2.5 VDDQ 2.5 (U)
  47 * 512M 8K REFRESH (12)
  48 * x16 (16)
  49 * 4banks (2)
  50 * SSTL_2 (2)
  51 * 4th GEN die (C)
  52 * Normal Power Consumption (<blank> )
  53 * TSOP (T)
  54 * Single Die (<blank>)
  55 * Lead Free (P)
  56 * DDR400 3-3-3 (D43)
  57 */
  58
  59struct spd_entry {
  60        u8 address;
  61        u8 data;
  62};
  63
  64/* Save space by using a short list of SPD values used by Geode LX Memory init */
  65static const struct spd_entry spd_table[] = {
  66        {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
  67        {SPD_BANK_DENSITY, 0x40},
  68        {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
  69        {SPD_MEMORY_TYPE, 7},
  70        {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
  71        {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
  72        {SPD_NUM_BANKS_PER_SDRAM, 4},
  73        {SPD_PRIMARY_SDRAM_WIDTH, 8},
  74        {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */
  75        {SPD_NUM_COLUMNS, 0xa},
  76        {SPD_NUM_ROWS, 3},
  77        {SPD_REFRESH, 0x3a},
  78        {SPD_SDRAM_CYCLE_TIME_2ND, 60},
  79        {SPD_SDRAM_CYCLE_TIME_3RD, 75},
  80        {SPD_tRAS, 40},
  81        {SPD_tRCD, 15},
  82        {SPD_tRFC, 70},
  83        {SPD_tRP, 15},
  84        {SPD_tRRD, 10},
  85};
  86
  87/**
  88 * Given an SMBUS device, and an address in that device, return the value of SPD
  89 * for that device. In this mainboard, the only one that can return is DIMM0. 
  90 * @param device The device number
  91 * @param address The address in SPD rom to return the value of
  92 * @returns The value
  93 */ 
  94u8 spd_read_byte(u16 device, u8 address)
  95{
  96        int i;
  97        /* returns 0xFF on any failures */
  98        u8 ret = 0xff;
  99
 100        printk(BIOS_DEBUG, "spd_read_byte dev %04x", device);
 101        if (device == DIMM0) {
 102                for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
 103                        if (spd_table[i].address == address) {
 104                                ret = spd_table[i].data;
 105                                break;
 106                        }
 107                }
 108                if (i == ARRAY_SIZE(spd_table))
 109                        printk(BIOS_DEBUG, " addr %02x does not exist in SPD table",
 110                                address);
 111        }
 112
 113        printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret);
 114        return ret;
 115}
 116
 117/**
 118  * Placeholder in case we ever need it. Since this file is a
 119  * template for other motherboards, we want this here and we want the
 120  * call in the right place.
 121  */
 122
 123static void mb_gpio_init(void)
 124{
 125        /* Early mainboard specific GPIO setup */
 126}
 127
 128/** 
 129  * main for initram for the PC Engines Alix 1C.  It might seem that you
 130  * could somehow do these functions in, e.g., the cpu code, but the
 131  * order of operations and what those operations are is VERY strongly
 132  * mainboard dependent. It's best to leave it in the mainboard code.
 133  */
 134int main(void)
 135{
 136        printk(BIOS_DEBUG, "Hi there from stage1\n");
 137        post_code(POST_START_OF_MAIN);
 138
 139        system_preinit();
 140        printk(BIOS_DEBUG, "done preinit\n");
 141
 142        mb_gpio_init();
 143        printk(BIOS_DEBUG, "done gpio init\n");
 144
 145        pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
 146        printk(BIOS_DEBUG, "done pll reset\n");
 147
 148        cpu_reg_init(0, DIMM0, DIMM1, DRAM_TERMINATED);
 149        printk(BIOS_DEBUG, "done cpu reg init\n");
 150
 151        sdram_set_registers();
 152        printk(BIOS_DEBUG, "done sdram set registers\n");
 153
 154        sdram_set_spd_registers(DIMM0, DIMM1);
 155        printk(BIOS_DEBUG, "done sdram set spd registers\n");
 156
 157        sdram_enable(DIMM0, DIMM1);
 158        printk(BIOS_DEBUG, "done sdram enable\n");
 159
 160        /* Check low memory */
 161        /*ram_check(0x00000000, 640*1024); */
 162
 163        printk(BIOS_DEBUG, "stage1 returns\n");
 164        return 0;
 165}
 166